use it as a current input ;-)
This current mirror mirror takes care, that on the left side a current flows from + to grd, while on the right side a current flows from + to ground. If there is a little voltage V6 introduced, the symmetrie is hurt and the missing current is squeezed out to the right. Where it can be fed into the charge balancer. Gives a fast shunt amplifier. Take care 100R to 10K is not appropriate, just do a spice simulation
I've noticed that the 100x magnification mode, being almost purely current-driven at a ~50mV span, is very reactive. Low-voltage, low-impedance, AC-coupled signals can be resolved especially well, because they don't go through the big ~450k resistor. I wonder how that mode can be practically exploited.
Maybe that resistor is a significant noise source ? (both from noise within the resistor, and worse rejection of femto-farad level cross coupling )
What happens if you replace that R externally, in the high range, and check noise floor ?
Re the 450k, I make that a load of ~ 5uA when measuring a diode drop ( (0.6+3.3/2)/450k = 5.0e-6 )
which means injection current should be >> 5uA, so 100uA~500uA look to be ok. eg (4.9-3.3)/15k = 106.6uA
Done. I've chopped off 320 & 340 MHz because there was some odd values in the 320 MHz table.
EDIT: I've just replaced the files (Pin 58 didn't appear in the key)
Interesting 'snail trails'...
Curious how the lower quadrant has similar slopes/shapes, with higher dX than dY, whilst the upper quadrant has much smaller dX for dY ?
MHz direction is not shown - is that maybe the same as the identified 'higher thermal effects on lower graph corner pins' ?
Generally speaking, (excluding that 320MHz ?), Clock speed does not seem to matter much, with between pin variations still (much) larger than MHz variations.
I noticed that the ADC was petering out at over 300MHz. It's just too fast for the 3.3V digital circuitry to toggle at. Maybe raise 3.3V to 3.6V for hotter bias.
Hmm, I guess every chip is going to have a different look to that spread. It looks linear enough to be able to apply a simple scale to all inputs and get a decent return and still maintain full sample rate. EDIT: Just by using one ADC as thermal measurement for all the others.
Although, still want to gather behaviour over wide temperature too.
I've noticed that the 100x magnification mode, being almost purely current-driven at a ~50mV span, is very reactive. Low-voltage, low-impedance, AC-coupled signals can be resolved especially well, because they don't go through the big ~450k resistor. I wonder how that mode can be practically exploited.
There is plenty of instrumentation that needs high gain anyway. So may as well make use of that.
I've noticed that the 100x magnification mode, being almost purely current-driven at a ~50mV span, is very reactive. Low-voltage, low-impedance, AC-coupled signals can be resolved especially well, because they don't go through the big ~450k resistor. I wonder how that mode can be practically exploited.
Do you have equivalent LSB numbers, in microvolts on that range ?
Current sensors, or thermocouples could be read using a series CAP + 1G3157 Analog SW Chopper, for a 2 pin, high gain Analog reading.
More primitive could be to use a IO pin in open drain, as a shunt-short on a RC filter, but that brings the internal ground noise into the measurement. Might be ok for some current sense applications ?
A benefit of a 1G3157 Analog SW Chopper, is it can have multiple channels, with a single chopper pin.
Jmg, I don't have any numbers, but I've input signals of 30mV peak-to-peak amplitude and it resolved them in 100x mode with lots of detail, just as if we were sampling full 3.3V-span signals in 1x mode. I'm suspecting we are even better off, though, because we don't have that 450k resistor messing up our signal integrity. We are operating more in current mode, instead of voltage mode.
Jmg, I don't have any numbers, but I've input signals of 30mV peak-to-peak amplitude and it resolved them in 100x mode with lots of detail, just as if we were sampling full 3.3V-span signals in 1x mode. I'm suspecting we are even better off, though, because we don't have that 450k resistor messing up our signal integrity. We are operating more in current mode, instead of voltage mode.
You could quickly check that with a ~ 1kHz function generator feeding 3.3V into a sync pin, and then a 100:1 (eg 1k/10 ohms) divider PAD for 33mV right at the analog pin, and then sync reading pairs of the HI/LO and plot the difference noise. 500Hz~1kHz seem common chopper frequencies.
Did someone ever tried to correlate available measurement data with physical pin positioning/distance from the nearest VDD/GND, VIO/GIO paired connections (pad ring/ gold wire/ wire frame) that can be clearly seen at the following assembled die picture?
The sequence is as follows (counterclockwise, departing from wireframe/chip pin 1) (IC denotes internally connected to surrounding GND copper ring (before down stepping till the exposed pad)):
- Note : Since my sight is limited to the posted image (s), I cannot see any other connection details, so I decided to list GND and GIO physical connections separately, althought they can also be tyed togheter at the die metal layers level, besides they're visibly connectied to the surrounding GND copper ring.
- * Only P00 thru P07 listed, within their neighboring connections.
Exceptions to the above sequencing will be found at pin-100 (RESN), pin-1 (TEST), pin-50 (XO) and pin-51 (XI), but, since they are "merged" between valid sequences, their positions should be noted, in order to verify any further and localized interference.
The corner pins (eg P15,, 16, 31, 32, 47, 48) are the ones to watch for interesting effects.
Add 63 and 0 to the list and you'll find that geometry solely by itself is having its chance to play with our minds.
Two main reasons, at least, for it to happen, both related to inductance:
- The pins at the corners of the die are the ones whose connecting gold wires (between pad ring and wire frame) and wire frame lanes are longer than the ones near the center of each side (e.g., P7, P23, P24, P39, P55, P56).
Amkor's tabulated data, available thru its July 2018 linecard, shows a ~24% increase in loop inductance (3.78 nH at the corner pins versus 3.04 nH at the center ones), considering just the wire frame lanes; any extra inductance, added by the gold wires individual lenghts need to be considered too, and will vary according to silicon die dimmensions and its positioning inside package;
- Despite layout efforts were clearly been done, trying to alleviate it someway, the sudden 90º change in direction of power distribution/routing, near the borders of the die, does represent another series inductance, added to the same lines, to be considered.
DC current has no problem crossing the barriers, both at the wires and at the corners too, but as frequency increases so increases the chances for associated series inductances to interfere at the measurements.
As static and dynamic currents tend to follow the shortest available paths, unless they are plagged by presenting high series impedance to their flow, perhaps it'll be interesting to verify if doing any rotation of the Cog # were the tests are running could show any new and singular effects at all, that could be related to the distance that VDD and GND (mainly) needs to traverse, thru die's superficial metal layers, causing slight imbalances at the surrounding GND metal ring, whose will turn (perhaps) in another interesting set of measurements.
Science is nothing but experimentation and thought (not always in that order); that is the reason it is so funny and interesting to deal with.
In either chip, i don't see why even 40mA would be a problem. Maybe on start-up, high clamp currents could induce latchup, but the pins can take it. The danger of over-VDD voltages into I/O pins comes from lifting up the power supply.
Chip, I've only taken the pins to ~500uA as per P1 absolute max guidelines. Any reason to expect P2 to be different?
For temp sense, the injection current only needs to be well above the uncertainty of the Analog-In current.
With the resistors value Chip quoted, Analog Current is ~ 5uA, and if that is 20% variant, that's 1uA of uncertainty.
An injection of 105uA should give a diode current variation of 1%, 55uA is 2% etc
Can you check differing pins for 105uA(+), and differing parts ? ( ~430mV, -2mV / 'C ? )
I've found 'same device' pins were very well matched (1-2mV difference) and between device quite well matched, if same vendor/same batch.
In either chip, i don't see why even 40mA would be a problem. Maybe on start-up, high clamp currents could induce latchup, but the pins can take it. The danger of over-VDD voltages into I/O pins comes from lifting up the power supply.
As currents increase, you can trigger the PNPN SCR == latch-up, and that needs some care to avoid damage of the P2.
It will crowbar Vio-Vss, so large caps should be removed, and a modest current limit applied for testing.
If you inject current negative, you avoid lifting Vio up. An RC circuit can be used to inject > 100mA, as it does not need to last long to trigger a SCR.
( an RC + SPDT switch can also inject current relative to Vio, and so avoid pulling Vio up)
Usually latch-up is > 100mA, and on the CMOS parts I've tested the SCR is actually 'quite good' with a low holding current of < 20mA
I've not tried Crow-bar + hiccup power supply, but that may work to recover from an ESD related latchup.
Besides the brick-wall effect of crowbar at high clamp currents, there is also a more subtle analog effect at smaller clamp currents.
That effect is lateral currents, where the Diode is actually the E-B junction of a lateral PNP, and that can inject currents into adjacent pins, that can disturb analog operation.
You can measure the gain of that lateral transistor, by injecting eg 10mA into one pin, and measuring the currents coming out of adjacent pins in uA
I also ran an extended test 300 to 340 MHz in 4MHz increments. I had a large oscillating fan blowing toward the pcb.
Hmm.. Quite a variation. does the 320MHz outlier/garbage effect go away ?
Maybe the fan explains the drop in dX on the new plot ? (less temperature change)
I notice the pins bounce about a lot (assuming the same symbol tags apply), but generally a Lower left pin is still found lower left, and UR is found UR, but they can move almost half a screen in X
Getting temperature from that device-device variation is looking like a lot of work ?
The diode numbers are looking much better.
Yes I think a larger board or contstant cpu cooler fan might help keep things stable. There might also be ways of interleaving the tests to maintain a more constant temperature.
Here's a comparison of average GIO by pin number (p0..59) on two different boards (from OzPropDev's data too). Both frequencies 80 MHz. There doesn't appear to be much consistency.
Here's a comparison of average GIO by pin number (p0..59) on two different boards (from OzPropDev's data too). Both frequencies 80 MHz. There doesn't appear to be much consistency.
Right, which is why I think the most can be gained just by doing a startup calibration of each GIO reading.
To additionally compensate for thermal drift, a small extension to this method relies on all ADC's having same relative movement of GIO reading. Working from a single unconnected ADC as the reference to apply an additional thermal offset to all connected ADC readings.
I think this direct mapped offset for drift compensation is a reasonable assumption. I'm hoping at least 90% reduction in drift effect. Obviously not as good as Chip's method but a decent compromise for maintaining full sampling speed.
@ErNa
Tubular and I were testing ADC and Goertzel stuff on the P2 silicon today.
Here's 8192 samples of the ADC noise for analysis if anyone is interested.
I'm coming back to the data in Tubulars measurement.
The data is processed as follows: first, to have small numbers, I remove the offset: b= a -690
Next I calculate the derivative over two samples: C(3) = (B(3)-B(1))/2
Then I integrate: D2 = D1+C1 what gives a nicely filtered signal with a little phase shift.
The difference, that is the filtered noise, is high frequency and shows sharp spikes. Those are very likely created by the phase shift of one sample.
Comments
This current mirror mirror takes care, that on the left side a current flows from + to grd, while on the right side a current flows from + to ground. If there is a little voltage V6 introduced, the symmetrie is hurt and the missing current is squeezed out to the right. Where it can be fed into the charge balancer. Gives a fast shunt amplifier. Take care 100R to 10K is not appropriate, just do a spice simulation
Maybe that resistor is a significant noise source ? (both from noise within the resistor, and worse rejection of femto-farad level cross coupling )
What happens if you replace that R externally, in the high range, and check noise floor ?
Re the 450k, I make that a load of ~ 5uA when measuring a diode drop ( (0.6+3.3/2)/450k = 5.0e-6 )
which means injection current should be >> 5uA, so 100uA~500uA look to be ok. eg (4.9-3.3)/15k = 106.6uA
Curious how the lower quadrant has similar slopes/shapes, with higher dX than dY, whilst the upper quadrant has much smaller dX for dY ?
MHz direction is not shown - is that maybe the same as the identified 'higher thermal effects on lower graph corner pins' ?
Generally speaking, (excluding that 320MHz ?), Clock speed does not seem to matter much, with between pin variations still (much) larger than MHz variations.
jmg, the effect of higher MHz is to "pull towards centroid" - higher MHz values make things better. I'm also curious what happens at 320 MHz
Yeah, when I deleted the 320/340 points it was the upper-right end of those long trails that vanished.
Although, still want to gather behaviour over wide temperature too.
There is plenty of instrumentation that needs high gain anyway. So may as well make use of that.
Do you have equivalent LSB numbers, in microvolts on that range ?
Current sensors, or thermocouples could be read using a series CAP + 1G3157 Analog SW Chopper, for a 2 pin, high gain Analog reading.
More primitive could be to use a IO pin in open drain, as a shunt-short on a RC filter, but that brings the internal ground noise into the measurement. Might be ok for some current sense applications ?
A benefit of a 1G3157 Analog SW Chopper, is it can have multiple channels, with a single chopper pin.
That looks sane. How far off are the 320MHz outliers ? What if you include those ?
You could quickly check that with a ~ 1kHz function generator feeding 3.3V into a sync pin, and then a 100:1 (eg 1k/10 ohms) divider PAD for 33mV right at the analog pin, and then sync reading pairs of the HI/LO and plot the difference noise. 500Hz~1kHz seem common chopper frequencies.
https://forums.parallax.com/discussion/download/123688/IMG_5301.jpg
The sequence is as follows (counterclockwise, departing from wireframe/chip pin 1) (IC denotes internally connected to surrounding GND copper ring (before down stepping till the exposed pad)):
- Note : Since my sight is limited to the posted image (s), I cannot see any other connection details, so I decided to list GND and GIO physical connections separately, althought they can also be tyed togheter at the die metal layers level, besides they're visibly connectied to the surrounding GND copper ring.
01 - TEST
02 - VDD
(IC) GND
03 - P00
04 - P01
05 - VIO [00:03]
(IC) GIO [00:03]
06 - P02
07 - P03
08 - VDD
(IC) GND
09 - P04
10 - P05
11 - VIO [04:07]
(IC) GIO [04:07]
12 - P06
13 - P07
14 - VDD
(IC) GND
- * Only P00 thru P07 listed, within their neighboring connections.
Exceptions to the above sequencing will be found at pin-100 (RESN), pin-1 (TEST), pin-50 (XO) and pin-51 (XI), but, since they are "merged" between valid sequences, their positions should be noted, in order to verify any further and localized interference.
Hope it helps
Henrique
PS: I'd pick pin 47 as the most off-the-slope trail in that graph.
Add 63 and 0 to the list and you'll find that geometry solely by itself is having its chance to play with our minds.
Two main reasons, at least, for it to happen, both related to inductance:
- The pins at the corners of the die are the ones whose connecting gold wires (between pad ring and wire frame) and wire frame lanes are longer than the ones near the center of each side (e.g., P7, P23, P24, P39, P55, P56).
Amkor's tabulated data, available thru its July 2018 linecard, shows a ~24% increase in loop inductance (3.78 nH at the corner pins versus 3.04 nH at the center ones), considering just the wire frame lanes; any extra inductance, added by the gold wires individual lenghts need to be considered too, and will vary according to silicon die dimmensions and its positioning inside package;
- Despite layout efforts were clearly been done, trying to alleviate it someway, the sudden 90º change in direction of power distribution/routing, near the borders of the die, does represent another series inductance, added to the same lines, to be considered.
https://forums.parallax.com/discussion/download/123690/z1.jpg
DC current has no problem crossing the barriers, both at the wires and at the corners too, but as frequency increases so increases the chances for associated series inductances to interfere at the measurements.
As static and dynamic currents tend to follow the shortest available paths, unless they are plagged by presenting high series impedance to their flow, perhaps it'll be interesting to verify if doing any rotation of the Cog # were the tests are running could show any new and singular effects at all, that could be related to the distance that VDD and GND (mainly) needs to traverse, thru die's superficial metal layers, causing slight imbalances at the surrounding GND metal ring, whose will turn (perhaps) in another interesting set of measurements.
Science is nothing but experimentation and thought (not always in that order); that is the reason it is so funny and interesting to deal with.
Henrique
Thans Brian. Here's the results from Board2.
I also ran an extended test 300 to 340 MHz in 4MHz increments. I had a large oscillating fan blowing toward the pcb.
Here are some graphs. Going above the 3v3 rail has a diode voltage about 0.035v lower, compared with going below the Gnd rail, for the same current
Chip, I've only taken the pins to ~500uA as per P1 absolute max guidelines. Any reason to expect P2 to be different?
These tests at room temperature, about 18 C / 65 F
For temp sense, the injection current only needs to be well above the uncertainty of the Analog-In current.
With the resistors value Chip quoted, Analog Current is ~ 5uA, and if that is 20% variant, that's 1uA of uncertainty.
An injection of 105uA should give a diode current variation of 1%, 55uA is 2% etc
Can you check differing pins for 105uA(+), and differing parts ? ( ~430mV, -2mV / 'C ? )
I've found 'same device' pins were very well matched (1-2mV difference) and between device quite well matched, if same vendor/same batch.
As currents increase, you can trigger the PNPN SCR == latch-up, and that needs some care to avoid damage of the P2.
It will crowbar Vio-Vss, so large caps should be removed, and a modest current limit applied for testing.
If you inject current negative, you avoid lifting Vio up. An RC circuit can be used to inject > 100mA, as it does not need to last long to trigger a SCR.
( an RC + SPDT switch can also inject current relative to Vio, and so avoid pulling Vio up)
Usually latch-up is > 100mA, and on the CMOS parts I've tested the SCR is actually 'quite good' with a low holding current of < 20mA
I've not tried Crow-bar + hiccup power supply, but that may work to recover from an ESD related latchup.
Besides the brick-wall effect of crowbar at high clamp currents, there is also a more subtle analog effect at smaller clamp currents.
That effect is lateral currents, where the Diode is actually the E-B junction of a lateral PNP, and that can inject currents into adjacent pins, that can disturb analog operation.
You can measure the gain of that lateral transistor, by injecting eg 10mA into one pin, and measuring the currents coming out of adjacent pins in uA
Hmm.. Quite a variation. does the 320MHz outlier/garbage effect go away ?
Maybe the fan explains the drop in dX on the new plot ? (less temperature change)
I notice the pins bounce about a lot (assuming the same symbol tags apply), but generally a Lower left pin is still found lower left, and UR is found UR, but they can move almost half a screen in X
Getting temperature from that device-device variation is looking like a lot of work ?
The diode numbers are looking much better.
Here's a comparison of average GIO by pin number (p0..59) on two different boards (from OzPropDev's data too). Both frequencies 80 MHz. There doesn't appear to be much consistency.
No problem. Thanks for plotting those, evanh.
Right, which is why I think the most can be gained just by doing a startup calibration of each GIO reading.
To additionally compensate for thermal drift, a small extension to this method relies on all ADC's having same relative movement of GIO reading. Working from a single unconnected ADC as the reference to apply an additional thermal offset to all connected ADC readings.
I think this direct mapped offset for drift compensation is a reasonable assumption. I'm hoping at least 90% reduction in drift effect. Obviously not as good as Chip's method but a decent compromise for maintaining full sampling speed.
The data is processed as follows: first, to have small numbers, I remove the offset: b= a -690
Next I calculate the derivative over two samples: C(3) = (B(3)-B(1))/2
Then I integrate: D2 = D1+C1 what gives a nicely filtered signal with a little phase shift.
The difference, that is the filtered noise, is high frequency and shows sharp spikes. Those are very likely created by the phase shift of one sample.