I have found that using the highest 100x magnification setting, it can resolve a lot of detail. It is mainly in current mode, at that point. I wonder if that eliminates some of the noise source. The resistor is almost gone.
I just checked. I can get it for $2 / pound close by the house. They will discount on larger quantities.
I can see it now. We've got boards with a little bin and plenum to guide the cold right where it needs to be. Those boards have the sensors needed too.
"Low coolant, system clock capped at 250Mhz, plz fill chamber"
https://en.wikipedia.org/wiki/Johnson%E2%80%93Nyquist_noise
Certainly, there is always noise, we can not omit. But all the semiconductor structures will generate noise, we could influence, optimizing the structures. A task, we can not contribute to.
As I said above, we balance the charge in a capacitor. The resolution can not be more, then the number of charge quanta, we feed back into the cap. The next question is, what is the deviation in the quanta. As the charge is integrated current over the clock time and the current is voltage over resistance, every fluctuation of voltage or switching time changes the charge. If the sampling rate is a given number of clocks, the deviation is averaged by number of clocks and the standard deviation reduced by square root of that number.
So it could be interesting to read out the register at very high rate (input and store in array) to have a count value as small as possible, analyse the noise (this will be very noisy) and then average to bring down the sampling rate, what should result in a better noise figure. The square root law should apply. Then, the noise is white noise, otherwise it may be a systematical error which could be corrected.
But again: I don't recommend to redesign the ADC, as we know what we have, but don't know, what we get. It is like: if we know, that Chip systematically lies to us, we should consider to exchange him. But as this is not the case, we keep him ;-)
@cgracey : please don't take that to personally ;-)
So it could be interesting to read out the register at very high rate (input and store in array) to have a count value as small as possible, analyse the noise (this will be very noisy) and then average to bring down the sampling rate, what should result in a better noise figure.
Chip's calibration requires stopping the bitstream accumulator, selecting new voltage source - GIO, restarting the accumulator to get GIO value, same again for VIO, and finally back again to the actual input.
The problem with this calibration is that repeatedly, which appears to be required, performing it rips a big one into any overall sampling rate.
Yes, and that is why I believe, calibration doesn't really make sense. 90% of applications. Most signals are relative, that is, you need to measure the change of a signal. This is the case in voice. Or speed. Or whatever. I just don't have a signal ready, where the absolute value is necessary. And that is adequate for the propeller. Certainly we will not demodulate G5 mobile phone signals. In motor control, ADC's are very fast and very precise. But the current in PWM varies +-5% and is very spiky. Moreover, the torque easily varies by 10% during a fracture of a revolution at constant current. That just means: high precision adcs are typically overengineered. We should not try to compete AnalogDevices or LinearTechnology, there is a reason, why they merged
Is the thermal drift different at different ADCs? I didn't watch in detail. If yes, why not use one adc to determine drift and have the others running continuously.
I ran a test last night sweeping 80 to 340 MHz taking 1000 samples on pins 0 to 58.
I haven't had a chance to look at it closely yet but here they are anyway.
Could you please explain in a few words, what the values in the rows stand for and how the compensation process, Chip implemented, worked? So I have not to scroll back? The data here in display is the last row (range) and it is definitally periodical..and noisy.
The next graph shows the original signal, original averaged with neighbours a filtered components about 60 samples period, the blue segment is enlarged above to show the result of filtering more precisely
If we look to the noise of gio and vio, they are in the same range. The difference is less, that could mean, that gio and vio deviate in the same direction,what again points to a difference in the switching level of the comparator. This behavior is not linked to the clock rate, in the plot above the line bundles show the variation in the clock rate, while the end points of the bundles are related to the counts of an individual pin.The variation in the range reflects the difference, so the behavior is the same. As Chip pointed to: this is just to do instrumentation. Not to measure AC signal, so we can live with this comfortably.
Crazy question but has there ever been such a thing as taking alternating samples, one of the inherent noise without the source connected to the pin and the apply some method of bias to the actual signal to remove the noise present at the particular sample. I assume this is not doable but just curious if there is a digital version of noise cancellation.
Noise means: difference from sample to sample, if the signal is stabil, and the noise comes from the ADC, it doesn't matter, which signal you measure. But measuring the signal only 50% of the time increases the noise of the signal itself be 1.414..
In the end: measurement is just to confirm an estimation. So the best way to detect a signal is to correlate the signal over time with what you expect. If the correlation factor is high, you know, that the signal is, what you expect. It's just about confirmation. Event the most ugly noise can't overlay a confirmed signal.
As Chip pointed to: this is just to do instrumentation. Not to measure AC signal, so we can live with this comfortably.
It's such a huge drop in sample rate that even instrumentation will be affected by the resulting reduction in filtered bit-depth. Not everything is a thermocouple.
As Chip pointed to: this is just to do instrumentation. Not to measure AC signal, so we can live with this comfortably.
It's such a huge drop in sample rate that even instrumentation will be affected by the resulting reduction in filtered bit-depth. Not everything is a thermocouple.
Yes, for instrumentation readings, sample rate is going to be slow. At the other end, it can put out a delta-sigma bitstream at 300MHz that can be analyzed by the Goertzel circuit.
Done. I've chopped off 320 & 340 MHz because there was some odd values in the 320 MHz table.
EDIT: I've just replaced the files (Pin 58 didn't appear in the key)
That looks interesting. What do you make of it?
I've noticed that the 100x magnification mode, being almost purely current-driven at a ~50mV span, is very reactive. Low-voltage, low-impedance, AC-coupled signals can be resolved especially well, because they don't go through the big ~450k resistor. I wonder how that mode can be practically exploited.
Evanh, are you finding that the ADC works all the way to 340MHz?
This is based on : ozpropdev " I ran a test last night sweeping 80 to 340 MHz taking 1000 samples on pins 0 to 58.
I haven't had a chance to look at it closely yet but here they are anyway.
Comments
And there was plenty of dry ice in there when I left last night, lid closed, but it had all sublimed by morning.
EDIT: Converting the US$1.29 * 2.2 / 0.65 exchange = NZ$4.37. So just over double what Chip is paying.
I can see it now. We've got boards with a little bin and plenum to guide the cold right where it needs to be. Those boards have the sensors needed too.
"Low coolant, system clock capped at 250Mhz, plz fill chamber"
Certainly, there is always noise, we can not omit. But all the semiconductor structures will generate noise, we could influence, optimizing the structures. A task, we can not contribute to.
As I said above, we balance the charge in a capacitor. The resolution can not be more, then the number of charge quanta, we feed back into the cap. The next question is, what is the deviation in the quanta. As the charge is integrated current over the clock time and the current is voltage over resistance, every fluctuation of voltage or switching time changes the charge. If the sampling rate is a given number of clocks, the deviation is averaged by number of clocks and the standard deviation reduced by square root of that number.
So it could be interesting to read out the register at very high rate (input and store in array) to have a count value as small as possible, analyse the noise (this will be very noisy) and then average to bring down the sampling rate, what should result in a better noise figure. The square root law should apply. Then, the noise is white noise, otherwise it may be a systematical error which could be corrected.
But again: I don't recommend to redesign the ADC, as we know what we have, but don't know, what we get. It is like: if we know, that Chip systematically lies to us, we should consider to exchange him. But as this is not the case, we keep him ;-)
@cgracey : please don't take that to personally ;-)
Chip's calibration requires stopping the bitstream accumulator, selecting new voltage source - GIO, restarting the accumulator to get GIO value, same again for VIO, and finally back again to the actual input.
The problem with this calibration is that repeatedly, which appears to be required, performing it rips a big one into any overall sampling rate.
I haven't had a chance to look at it closely yet but here they are anyway.
The next graph shows the original signal, original averaged with neighbours a filtered components about 60 samples period, the blue segment is enlarged above to show the result of filtering more precisely
Values are from 16-bit sampled raw data from each ADC of pins 0-58. Range = VIOavg - GIOavg.
Here's Chip's post about the calibration method - https://forums.parallax.com/discussion/comment/1449144/#Comment_1449144
Can the shapes be replaced by blue, red and yellow pin numbers?
I'm just using what Oz and Tubular posts. I'm still on the FPGA.
Tony,
Working on that. Have to re-sort the data to make it spreadsheet friendly.
Sample noise
Sample signal
Apply bias
In the end: measurement is just to confirm an estimation. So the best way to detect a signal is to correlate the signal over time with what you expect. If the correlation factor is high, you know, that the signal is, what you expect. It's just about confirmation. Event the most ugly noise can't overlay a confirmed signal.
EDIT: I've just replaced the files (Pin 58 didn't appear in the key)
Exactly what the calibration is doing. But has to be done repeatedly to stay calibrated.
PS: This particular noise is internally generated.
It's such a huge drop in sample rate that even instrumentation will be affected by the resulting reduction in filtered bit-depth. Not everything is a thermocouple.
Yes, for instrumentation readings, sample rate is going to be slow. At the other end, it can put out a delta-sigma bitstream at 300MHz that can be analyzed by the Goertzel circuit.
That looks interesting. What do you make of it?
I've noticed that the 100x magnification mode, being almost purely current-driven at a ~50mV span, is very reactive. Low-voltage, low-impedance, AC-coupled signals can be resolved especially well, because they don't go through the big ~450k resistor. I wonder how that mode can be practically exploited.
This is based on : ozpropdev " I ran a test last night sweeping 80 to 340 MHz taking 1000 samples on pins 0 to 58.
I haven't had a chance to look at it closely yet but here they are anyway.
See below comments on 'MHz dependent issues'.
Can you expand on what 'odd values' means ?
That may be indicating the MHz is getting too high for some parts of the chip, and not others ?