Has dithering and the xoroshiro128** generator anything to do with this?

Well, these pad circuits work entirely in the VIO domain, while all the xoroshiro128** activity is in the VDD domain, probably causing some noise, but maybe none that could affect the ADCs.

I checked conversion noise from two adjacent pins to see if there was any apparent correlation. I don't see any. It seems that each ADC has a life of its own.

Each smartpin gets eight bits from the xoroshiro128** generator of its own. Are they latched inside the smartpin? Have you tried outputting a constant zero to the DAC with dither enabled, to look at the random bits?

The input is now selectable by series resistors. The voltage coming through gets converted to current, as the resistor is held at ~VIO/2 by current source/sink. The feedback current to do this becomes the binary stream, as the up/down need is evaluated on each clock.
I don't have simple means to make a csv file, but I could write code to do that. That's a mini project, in itself. I may be able to get to it tomorrow night.
Thanks for thinking about this.

OK, that's what I expected.
As we are discussing hardware and ADC, we see the very complicated systems with active components and do not realize, that first principles always are the foundation of any, even the most sophisticated system.
This ADC is a perfect example.
The ADC is nothing but a balancer. It balances the current flowing from two pathes to a capacitor. The integral value of the current error (inflowing to outflowing current) is the voltage of the capacitor, as v=c*q and q = int(i). The point is: by quantizing time, what in simple words means: by reading the capacitors voltage not continuously, but at certain moments, we are able to talk about charge and current to be the same! current is charge transfered over time. If time is determined to be 1, than charge is equal to current. On the input side, we assume a constant analog voltage, what corresponds to a constant current through a resistor and having the time = 1, current is charge. On the compensation side, a constant voltage is applied over a fraction of time one, so we deliver a given charge and by keeping the voltage of the capacitor constant setting the right fraction of time, we get a digital value representing the analog input voltage (e.g. current).
What is not seen mostly: if the input resistor equals 0, we can not apply an input voltage, we rather have to have an input current, so we now have a current input adc, not a voltage input adc. The point is: we feel uncomfortable with current inputs as we normally measure voltages with ease, not so currents.
Lets come back to the first principles: have you ever seen a resistor to be a voltage controlled current source? What else is it? You have two poles, you apply a voltage to the poles and you see, that a current comes out of one pole that is proportional to the voltage you apply! The same moment, you see a resistor as a current controlled voltage source, as you drive a current trough the resistor and you can measure a voltage across.
That is what we always should be aware of, when we talk about systems, we do not understand on the first glance.

No @cgracey there is no need to have a cvs, just a row of values, preferably ascii numbers, is fine!

The scope's visible vertical range is 256 steps, so you can see this noise is confined to 1/2 a graticule, or 16 steps, which is only 4 bits. Without calibration, noise is at least twice that.

So does it means that we have a true 16 bit DAC, and a 12 bits (16 - 4?) ADC? or both ADC/DAC are 16 bits? So far this chip is AWESOME, congratulations !

What about now averaging several calibrated samples? Does that help?

Yep, that would smooth the random noise, increasing the precision (bit depth). The trade-off is cut-off frequency. It would suit instrumentation nicely, as Chip said earlier. Huge win really, and testament to how open the hardware is.

Whenever you average a signal, the standard deviation relates invers to the square root of the number of samples. So averaging always reduces random noise. The case with this type of adc is: reading the number of bits needed to balance the capacitor once a second gives clock rate possible values. That is the resolution at a sampling rate of 1/s. The same is true, when you do the readout more often, so the resolution goes down. The question is: as you read out the signal at a certain point of time, to which moment this value is related? Indeed, it is the value of the averaged signal over the sampling time. The less sampling time you have, the more noise will be.
I showed above: the input resistor is just a voltage controlled current source. The input voltage is connected to the resistor, the other side of the resistor is connected to the balancing capacitor. As the voltage at this point can not be constant, the current source can not be ideal and introduces an error. There is no way around.

Easy often is difficult. There are so many ways to get a numeral representation of a physical signal. And the Propeller's way to convert an analog voltage signal is simply to have a pipe pouring water into a pool and to have a spoon to take it out, now the amount of water is equal to the number of spoons it took to empty the pool. The rest is just technology

The only thing that grows the complexity is the compensatory circuitry to eliminate unwanted charge injection in the balancing system, so that for the briefest of feedback periods (ie 4ns at 250MHz), a clean charge injection is made to the integrator cap. That is what took most of the design effort. The solution, by necessity, was very simple and lightweight.

Doing calibration on each measurement is slower, but it gets rid of that low-frequency wandering noise, since the samples were all taken in close proximity. It also nulls out die-temperature effects and adds another bit of resolution!

Look at the lower byte of noise now. The scope's visible vertical range is 256 steps, so you can see this noise is confined to 1/2 a graticule, or 16 steps, which is only 4 bits. Without calibration, noise is at least twice that.

That looks to null most of the 1/f noise, so is a good step forward.

Did you try further averaging of the 1/f removed results ?

You could also experiment with the sample time, instead of 16b, you could make the window eg 15/14/13/12b, and then post-average those quicker 1/f-removed samples, to see if the noise floor can be improved more. ie using a 16b reading to remove 11b of noise may be wasting some measurement/average time..

@"Peter Jakacki" Hello Peter, I can imagine, one of your oneliners is needed. Do you have one, that just reads the adc and sends the values to the terminal, so Chip can simply dump the output to a file using the terminal software? Would be great

Let me expand the example a little:
firstly, the pipe not only feeds water to the pool, but also can empty the pool, whenever the outer end of the pipe is below the pool water level. So the spoon has to balance the pool level by spending or taking water.
secondly, we have to determine the pool level to decide how to balance. It is clear, the smaller the pools surface it, the more sensitive the level detector works, as, given a certain inflow, a small surface results in great level change. So a faster level change allows to faster reach the detectors switching level and a faster spoon action.
We now have to look, how the pipe is connected to the pool. Is the end open, over the pool level, so the water pourse into the pool or is it just at or below? Let us take the second case first: If the pipe is unter the pool level, the pressure driving the water is just the difference between the pipe input level and the pool level.
That is: let the pool level be to low, and the pipe level at its maximum (that is, every single cycle, the spoon takes water off the pool and the level stays constant) then anyway, for at least on spoon is filled back to the pool, and now the level starts to rise as water flows in. The detector detects high level and water is taken from the pool.
But now the pool level is a little higher and so the resultant input pressure is lower. What leads to a little less of water inflow.
This hydralic machine shows the ultimate limits of this charge balancing converter. We need a current inflow, but the current is determined by a resistor and the actual voltage difference between input and charged capacitor, while the charge and so the voltage changes continously. Imagine the detector to have 1 mV threshold level (hysteresis) then the resolution can't be better then 1/2000 at an input voltage swing of 2V. So the capacitor should be selected, that at full scale input the voltage changes exactly by as much, as the detector can detect. And the hysteresis of the detector should be a little as possible, indeed, if the detector is just a comperator, the noise of the amplifier at a given constant input should generate a noisy output. This is like dithering the signal of the ADC: If you don't know to select red or blue, just dither and get pink.

And the hysteresis of the detector should be a little as possible, indeed, if the detector is just a comperator, the noise of the amplifier at a given constant input should generate a noisy output. This is like dithering the signal of the ADC: If you don't know to select red or blue, just dither and get pink.

Would that effectively be a negative hysteresis then?

@ErNa
Tubular and I were testing ADC and Goertzel stuff on the P2 silicon today.
Here's 8192 samples of the ADC noise for analysis if anyone is interested.

@ErNa
Tubular and I were testing ADC and Goertzel stuff on the P2 silicon today.
Here's 8192 samples of the ADC noise for analysis if anyone is interested.

Brian, thanks for doing this. I was going to get on that today, but you took care of it.

Here's Ozprop's ADC data in graphical form. Looks pretty gaussian, doesn't it?

And this is what it looks like as "13 bit" by throwing the last 3 bits away...

To be followed up - the value of the ground measurement centers on value 11701, or 17.8% of full scale. My memory of the design target was that this value should be something more like 12.5%, but my memory could be wrong. There's no real problem, since we have great scaling instructions, but we should hunt a bit further and see what it shows up

Brian if you get time, could you run the same test on VIO? Curious to see how VIO compares.

Tubular, I made some late change to the ADC so that GIO and VIO are not 1/8th and 7/8th duty, but a little higher and lower. This should allow a little more headroom for measurements beyond the rails, even into clamp-diode range.

Looking forward to trying "beyond the rails". We did hook a speaker up directly to a pin the other day, which was causing some inductive spikes that extended a bit beyond both rails. Maybe we can find a speaker and frequency thats gentle enough, perhaps those standard 57mm "old PC speakers" might be ok. Then you can hear the tone generation while watching the waveform that extends beyond the rails

Tubular, I made some late change to the ADC so that GIO and VIO are not 1/8th and 7/8th duty, but a little higher and lower. This should allow a little more headroom for measurements beyond the rails, even into clamp-diode range.

I see you added "even into clamp-diode range" - how many millivolts exactly outside the rails, and are there any clamps on the resistors used to measure ?

One clamp-diode measurement idea is to drive low with 10uA (may be too small if ADC is on ?) or 100uA via a CAP, and measure during that constant current phase. If the ADC can measure at that point, it saves having to do some DC restore dance.
- all that's needed is a charge/discharge duty cycle.

Addit : I make 17.8% of 3v3 0.5874V, which might be ok for some diodes, but not quite enough for others.
See my measurements of clamp elements in CMOS devices, in the other thread - it varies with process and IP's clamp higher than I/O
650~700mV is more room temperature ball park, dropping toward 550mV when heated. P1 was lower than HCMOS, so maybe P2 will also be lower ?

Could you use one sacrificial ADC to measure GND, then just numerically subtract that from the sample of interest? (Using the same settings for both ADCs.)

Could you use one sacrificial ADC to measure GND, then just numerically subtract that from the sample of interest? (Using the same settings for both ADCs.)

Jonathan

Every ADC is slightly different, mainly due to the tiny series'd inverters used as the sense amplifer. So, calibration values don't work across ADC's.

I thought up a scheme this weekend, where I'd interleave many small GIO, pin, and VIO measurements and sum them up, but the noise became worse. It seems to favor long measurements of 16 bits. If those are interleaved and summed up, things improve, but with a very slow sample rate.

Tubular, I made some late change to the ADC so that GIO and VIO are not 1/8th and 7/8th duty, but a little higher and lower. This should allow a little more headroom for measurements beyond the rails, even into clamp-diode range.

I see you added "even into clamp-diode range" - how many millivolts exactly outside the rails, and are there any clamps on the resistors used to measure?....

Jmg, I don't know exactly, as neither the range nor the Vf of the clamp can be known. I believe it is covered pretty well, though. By 400mV, those clamps are on quite hard, if I recall.

There are no clamps on the measuring resistors, but it just occurred to me that there are ESD clamp diodes on every pin.

Could you use one sacrificial ADC to measure GND, then just numerically subtract that from the sample of interest? (Using the same settings for both ADCs.)

Yes, that's already effectively done in the 3 readings SW above, only it does not need 'one sacrificial ADC to measure GND' - every ADC has a GND and VCC MUX, so the 3 reading code uses all 3 to calibrate offset and scale, and that also reduces the 1/f noise.

## Comments

2,120Each smartpin gets eight bits from the xoroshiro128** generator of its own. Are they latched inside the smartpin? Have you tried outputting a constant zero to the DAC with dither enabled, to look at the random bits?

4,6211,742As we are discussing hardware and ADC, we see the very complicated systems with active components and do not realize, that first principles always are the foundation of any, even the most sophisticated system.

This ADC is a perfect example.

The ADC is nothing but a balancer. It balances the current flowing from two pathes to a capacitor. The integral value of the current error (inflowing to outflowing current) is the voltage of the capacitor, as v=c*q and q = int(i). The point is: by quantizing time, what in simple words means: by reading the capacitors voltage not continuously, but at certain moments, we are able to talk about charge and current to be the same! current is charge transfered over time. If time is determined to be 1, than charge is equal to current. On the input side, we assume a constant analog voltage, what corresponds to a constant current through a resistor and having the time = 1, current is charge. On the compensation side, a constant voltage is applied over a fraction of time one, so we deliver a given charge and by keeping the voltage of the capacitor constant setting the right fraction of time, we get a digital value representing the analog input voltage (e.g. current).

What is not seen mostly: if the input resistor equals 0, we can not apply an input voltage, we rather have to have an input current, so we now have a current input adc, not a voltage input adc. The point is: we feel uncomfortable with current inputs as we normally measure voltages with ease, not so currents.

Lets come back to the first principles: have you ever seen a resistor to be a voltage controlled current source? What else is it? You have two poles, you apply a voltage to the poles and you see, that a current comes out of one pole that is proportional to the voltage you apply! The same moment, you see a resistor as a current controlled voltage source, as you drive a current trough the resistor and you can measure a voltage across.

That is what we always should be aware of, when we talk about systems, we do not understand on the first glance.

No @cgracey there is no need to have a cvs, just a row of values, preferably ascii numbers, is fine!

484So does it means that we have a true 16 bit DAC, and a 12 bits (16 - 4?) ADC? or both ADC/DAC are 16 bits? So far this chip is AWESOME, congratulations !

13,84815,161Yep, that would smooth the random noise, increasing the precision (bit depth). The trade-off is cut-off frequency. It would suit instrumentation nicely, as Chip said earlier. Huge win really, and testament to how open the hardware is.

1,742I showed above: the input resistor is just a voltage controlled current source. The input voltage is connected to the resistor, the other side of the resistor is connected to the balancing capacitor. As the voltage at this point can not be constant, the current source can not be ideal and introduces an error. There is no way around.

4,1911,74215,161propeller scoops.

14,133It is very simple at the first-principles level.

The only thing that grows the complexity is the compensatory circuitry to eliminate unwanted charge injection in the balancing system, so that for the briefest of feedback periods (ie 4ns at 250MHz), a clean charge injection is made to the integrator cap. That is what took most of the design effort. The solution, by necessity, was very simple and lightweight.

15,144That looks to null most of the 1/f noise, so is a good step forward.

Did you try further averaging of the 1/f removed results ?

You could also experiment with the sample time, instead of 16b, you could make the window eg 15/14/13/12b, and then post-average those quicker 1/f-removed samples, to see if the noise floor can be improved more. ie using a 16b reading to remove 11b of noise may be wasting some measurement/average time..

Link to 1/f - flicker noise https://en.wikipedia.org/wiki/Flicker_noise

Includes a model for MOSFETs and talks about excess noise in resistors.

1,7421,742firstly, the pipe not only feeds water to the pool, but also can empty the pool, whenever the outer end of the pipe is below the pool water level. So the spoon has to balance the pool level by spending or taking water.

secondly, we have to determine the pool level to decide how to balance. It is clear, the smaller the pools surface it, the more sensitive the level detector works, as, given a certain inflow, a small surface results in great level change. So a faster level change allows to faster reach the detectors switching level and a faster spoon action.

We now have to look, how the pipe is connected to the pool. Is the end open, over the pool level, so the water pourse into the pool or is it just at or below? Let us take the second case first: If the pipe is unter the pool level, the pressure driving the water is just the difference between the pipe input level and the pool level.

That is: let the pool level be to low, and the pipe level at its maximum (that is, every single cycle, the spoon takes water off the pool and the level stays constant) then anyway, for at least on spoon is filled back to the pool, and now the level starts to rise as water flows in. The detector detects high level and water is taken from the pool.

But now the pool level is a little higher and so the resultant input pressure is lower. What leads to a little less of water inflow.

This hydralic machine shows the ultimate limits of this charge balancing converter. We need a current inflow, but the current is determined by a resistor and the actual voltage difference between input and charged capacitor, while the charge and so the voltage changes continously. Imagine the detector to have 1 mV threshold level (hysteresis) then the resolution can't be better then 1/2000 at an input voltage swing of 2V. So the capacitor should be selected, that at full scale input the voltage changes exactly by as much, as the detector can detect. And the hysteresis of the detector should be a little as possible, indeed, if the detector is just a comperator, the noise of the amplifier at a given constant input should generate a noisy output. This is like dithering the signal of the ADC: If you don't know to select red or blue, just dither and get pink.

15,161Would that effectively be a negative hysteresis then?

EDIT: Improved my grammar. Is now a sentence.

2,791Tubular and I were testing ADC and Goertzel stuff on the P2 silicon today.

Here's 8192 samples of the ADC noise for analysis if anyone is interested.

14,133Brian, thanks for doing this. I was going to get on that today, but you took care of it.

4,621And this is what it looks like as "13 bit" by throwing the last 3 bits away...

To be followed up - the value of the ground measurement centers on value 11701, or 17.8% of full scale. My memory of the design target was that this value should be something more like 12.5%, but my memory could be wrong. There's no real problem, since we have great scaling instructions, but we should hunt a bit further and see what it shows up

Brian if you get time, could you run the same test on VIO? Curious to see how VIO compares.

14,13315,1444,621Looking forward to trying "beyond the rails". We did hook a speaker up directly to a pin the other day, which was causing some inductive spikes that extended a bit beyond both rails. Maybe we can find a speaker and frequency thats gentle enough, perhaps those standard 57mm "old PC speakers" might be ok. Then you can hear the tone generation while watching the waveform that extends beyond the rails

15,144I see you added "even into clamp-diode range" - how many millivolts

exactlyoutside the rails, and are there any clamps on the resistors used to measure ?One clamp-diode measurement idea is to drive low with 10uA (may be too small if ADC is on ?) or 100uA via a CAP, and measure during that constant current phase. If the ADC can measure at that point, it saves having to do some DC restore dance.

- all that's needed is a charge/discharge duty cycle.

Addit : I make 17.8% of 3v3 0.5874V, which might be ok for some diodes, but not quite enough for others.

See my measurements of clamp elements in CMOS devices, in the other thread - it varies with process and IP's clamp higher than I/O

650~700mV is more room temperature ball park, dropping toward 550mV when heated. P1 was lower than HCMOS, so maybe P2 will also be lower ?

https://forums.parallax.com/discussion/comment/1449227/#Comment_1449227

Q: what is the nominal series R in the ADC ? When measuring close to gnd, it will approximate a current source.

917Jonathan

2,79114,133Every ADC is slightly different, mainly due to the tiny series'd inverters used as the sense amplifer. So, calibration values don't work across ADC's.

4,621Compared with GIO, VIO is a little tighter, with a standard deviation of 5.3 rather than 6.0 at 16 bit resolution.

14,133I thought up a scheme this weekend, where I'd interleave many small GIO, pin, and VIO measurements and sum them up, but the noise became worse. It seems to favor long measurements of 16 bits. If those are interleaved and summed up, things improve, but with a very slow sample rate.

10,253If it is at all similar, adding it out of phase to the input might get us a bit.

14,133Jmg, I don't know exactly, as neither the range nor the Vf of the clamp can be known. I believe it is covered pretty well, though. By 400mV, those clamps are on quite hard, if I recall.

There are no clamps on the measuring resistors, but it just occurred to me that there are ESD clamp diodes on every pin.

15,144one sacrificial ADC to measure GND' - every ADC has a GND and VCC MUX, so the 3 reading code uses all 3 to calibrate offset and scale, and that also reduces the 1/f noise.