Could you use one sacrificial ADC to measure GND, then just numerically subtract that from the sample of interest? (Using the same settings for both ADCs.)
Jonathan
Every ADC is slightly different, mainly due to the tiny series'd inverters used as the sense amplifer. So, calibration values don't work across ADC's.
It'll be interesting to see how they vary from pin to pin and chip to chip. Since those VIO and GIO calibration connections are purely internal, perhaps this is a way of obtaining a 'unique signature' of the silicon being tested. That would make for a kind of organic serial number.
Temperature and IO voltage (3v3, 3v0 etc) may affect the readings, and if they do, perhaps this paves the way to a method for not only measuring die temperature, but measuring die temperature near each pin.
I thought up a scheme this weekend, where I'd interleave many small GIO, pin, and VIO measurements and sum them up, but the noise became worse. It seems to favor long measurements of 16 bits. If those are interleaved and summed up, things improve, but with a very slow sample rate.
How small was 'many small' -- I'd expect those to need to be higher resolution than the appx noise floor, or the quantization noise will bite.
ie going from 16b to 15 or 14 or 13 ? should buy more time to do more sum/average samples, but I'm not sure going from (eg) 16b to 8b helps.
Given the plots above, I'd suggest doing slightly faster (1/2/3 fewer bits) of the 3-sample readings, and then average on the net scaled results, rather than on each of the 3 samples.
I thought up a scheme this weekend, where I'd interleave many small GIO, pin, and VIO measurements and sum them up, but the noise became worse. It seems to favor long measurements of 16 bits. If those are interleaved and summed up, things improve, but with a very slow sample rate.
Ozprop and I thought interleaving like this sequence would improve things a bit
GIO - Pinvoltage - VIO - Pinvoltage - GIO ... etc would provide a neat improvement
It feels like the VIO connection is 'lower impedance' - eg the stdev on the VIO readings was lower than GIO, and the freeze spray seemed also to affect it less. This may mean its not necessary to stare at VIO for as long,
Other improvements may come as we better understand the interactions - eg while every ADC may be slightly different, perhaps they can be measured and 'characterised', and once that model data and relationships are known, it may not be necessary to measure everything as intensively as we are currently.
It could be that different bit resolutions are slightly better than others? 16 bits is a great, optimistic starting point but things probably look more solid at 14 bits, for instance.
Then we can look at cross coupling readings, because we can read neighboring pins voltages on the ADC can't we Chip? PinB ADC modes?
You could bring same analog signal into two or more ADCs and see what happens
Really, there is so much flexibility with this chip. I think we'll still be discovering stuff years into the future.
I thought up a scheme this weekend, where I'd interleave many small GIO, pin, and VIO measurements and sum them up, but the noise became worse. It seems to favor long measurements of 16 bits. If those are interleaved and summed up, things improve, but with a very slow sample rate.
Lonesock's idea might be worth chasing, so then the ADC can be left on non-stop.
Surely the drifting behaviour is all thermal. On that assumption, it should be possible to build a thermally induced translation of a neighbouring GIO/VIO to map to the target pin's equivalent GIO/VIO. Start with a high and low temperature set of averages for each.
If it's not a linear mapping then I guess it'll be a tall order to fill, but maybe linear is good enough.
Does P2 have the D-FF output type feedback that was possible on P1 ?
It may be adding an external opamp and a '3157' SPCO analog switch could avoid the on-chip noise sources.
Of course, that's more parts, but for someone wanting 14~20 bits it can be cheaper than an external ADC.
Does P2 have the D-FF output type feedback that was possible on P1 ?
It may be adding an external opamp and a '3157' SPCO analog switch could avoid the on-chip noise sources.
Of course, that's more parts, but for someone wanting 14~20 bits it can be cheaper than an external ADC.
Yes, it can do that, but the parasitics at 200MHz are going to make a mess of things. The ADC was designed to minimize parasitics internally, in order to get the performance up. I suspect that by increasing feedback current in the internal ADC (would lower input impedance), we might be able to push the noise down. What do you think?
Chip, when the ADC PinA mode is active, are we meant to be able to also select the resistors and current sources in the HHHLLL configuration? We didn't see these coming online, when we tried that the other day?
Or are these disabled because you're trying to bias the reading node at 1.65v?
Does P2 have the D-FF output type feedback that was possible on P1 ?
It may be adding an external opamp and a '3157' SPCO analog switch could avoid the on-chip noise sources.
Of course, that's more parts, but for someone wanting 14~20 bits it can be cheaper than an external ADC.
Yes, it can do that, but the parasitics at 200MHz are going to make a mess of things.
It does not have to try to follow 200MHz, you would run an external integrator, which moves the P2 to purely digital operation.
The sampling clock on the D-FF would be adjusted for lowest noise/highest bits. and would interact a little with the OpAmp chosen.
Integrator Opamp needs to be high slew but unity gain stable, with low Vos and good CMRR.
That does thin out the field, but something like OPA320 series looks a reasonable starting point ? (10v/us, Vos 40uV typ, CMRR 114dB typ)
Question is then does that pair with a 3157 (D-FF inside P2) , or can a 74AUP1G80 external D-FF do as well ?
Addit: Looking some more, I favour the external D-ff approach (74AUP1G80) as that supports more channels at one-pin-per added channel.
It also move the ADC analog-nodes cell into a nice separate area, and CLK is user defined SysCLK/N
TI part says 'Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3 V)"
NXP says "Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V."
- which is good to tolerate the sawtooth output from the integrator. (250mV and 10V/us is 40MHz max sampling clock region )
Or, you could connect a part like AMC1035 - indicated price $1.50, So8, Accepts 9 MHz to 21 MHz ClkIn, includes a 0.2%, ±10ppm typ Vref http://www.ti.com/product/amc1035
The ADC was designed to minimize parasitics internally, in order to get the performance up. I suspect that by increasing feedback current in the internal ADC (would lower input impedance), we might be able to push the noise down. What do you think?
What value is the series resistance ?
Higher current / lower impedance would help, but my feeling is it will be diminishing returns, with the poor PSRR present in a simple CMOS buffer.
What could make the ADC better? Hard to say, as so many parameters contribute to noise. Writing this I realize: we talk about the noise figure, not about resolution, speed, linearity, offset, stability etc. I believe, it makes so sense to invest into more development efforts, as the question to me is: what can be done with what we have and will there be a widening of the scope (market) if we could do it better in any aspect. My noisy answer: NO. Just take what we have.
There is a capacitor, an input current resulting in charge over time and compensating charges to keep the capacitors voltage constant.
Where errors can come from:
Imagine the capacitor changes his value, then, at given charge, the voltage will change. What makes the cap changing? Any current in the proximity will induce a magnetic field and influence the position of the electrons in the cap, so changing voltage. The same is true for voltages around, they also will create forces acting on the electrons ..
So first point: have no influence of any condition change on the cap. Surround the cap with vacuum ;-) or with a box, that is connected to ground, so the caps one electrode is a symmetric ground plane and the active electrode is inside.
You have to take care, that a given input voltage creates proportional current flow through the resistor. So this resistor has to be "perfect" what can not be the case using doped silicon. Metal resistors certainly are better, but are not feasible in the process, I guess. Anyway, the resistors also have to be shielded.
You have to take care, that the quanta of compensation charges are equal. If you use a voltage source to feed back charge, the current depends on the cap's current voltage. So it may make sense to have a separate cap to store the quanta and then transfer them to the balancing cap. Like in a CCD.
What about the sensing comparator? All problems with comparator we know will apply.
So whatever we do: we are deep in the business of ADC development, what definitly should not be the case.
As mentioned: the most important factor is: how to make use of what we have. One method is to intensionally bring a weak component into a critical position and then just control this component to get what you want. I believe, we shouldn'd follow this way. But we have what we have and we have to answer: what to do with this. The prop allows us to determine the duration of the measurement by reading the counter in a given time interval. E.g. we measure with 1 kHz. The counters difference represent the voltage. During the interval, averaged. Now, if we read the counter with a frequecy of 10kHz, we only have a tenth of the tics and the noise factor goes up by 3. But what if we still measure 1ms, now overlapping. We get a smoothed signal, but anyway, the signals may show a trend. This method gives low noise, a trend line and a little phase shift. But if you have a trend line and from experience you know, that the signal changes slowly, you can forcast the values and so reduce phase shift. This is especially true, when you know, that your signal has periodical content...
Again: there is so much workload ahead, don't be delayed by solving problems, we don't have. We made a propeller in a common effort. Now let us use, what we have. And if we really believe, something must be corrected or optimized, we should look to use the possilities, given to us by great people!
Chip, when the ADC PinA mode is active, are we meant to be able to also select the resistors and current sources in the HHHLLL configuration? We didn't see these coming online, when we tried that the other day?
Or are these disabled because you're trying to bias the reading node at 1.65v?
Good question - it will certainly be useful to have ADC operate in pin-drive cases.
I'm not sure I've seen any numbers yet for lower current source/sink & series resistor drive mode tests ?
Chip did say a single pin Cap-Osc can be built with own-pin-feedback and current drive, but that's not analog ADC mode.
Chip, when the ADC PinA mode is active, are we meant to be able to also select the resistors and current sources in the HHHLLL configuration? We didn't see these coming online, when we tried that the other day?
Or are these disabled because you're trying to bias the reading node at 1.65v?
You need to make DIR to the pin high. In smart pin mode the pin DIR can be set high by putting %01 in WRPIN data bits D[7:6].
Here's some 16 bit ADC captures taken yesterday, for every pin P0..P61 (P62 and P63 were being used for serial).
For each Pin there is an 8192 element capture of its ADC connected to GIO (ADC connected to ground), and below that, a 8192 element capture of its ADC connected to VIO (ADC connected to local 3v3 VIO input).
For each pin, we came up with a simple 'quality score', being the sum of standard deviation of GIO data points plus standard deviation of VIO data points, to see if any pins were markedly better than others.
We found things were pretty consistent, would need to study several chips to form any meaningful conclusions. P28 seemed marginally the best (this is where the PLL is, right?, though its neighbors weren't stellar), and the corner pins may be marginally worse - needs further investigation.
ADC calibration mode VIO and GIO average values are correlated. If GIO reads low, its VIO will also generally be lower, such that the 'span' is generally consistent.
Extrapolating zero and $ffff codes for each pin yields a remarkably consistent 5v span.
This doesn't imply 5v tolerance necessarily, since currents would be large at the extremes, and a fancy diode bias arrangement would be needed for the P2
Extrapolating zero and $ffff codes for each pin yields a remarkablu consistent 5v span.
This doesn't imply 5v tolerance necessarily, since currents would be large at the extremes
Right, the clamp diodes would hit well before then.
More useful might be the 'virtual overhead' numbers, in each direction (one+, one-), = where the ADC saturates, assuming no diodes present at all.
eg, I think those above could be (roughly) (10.5k/53500)*3.3 = -0.647 below gnd (13k/55500)*3.3 = -0.7729 below gnd
edit:
I think better is the span of v-g is mapped to 3.3V, and the remainder ratios to that. (this now matches your ~5V span)
Rg=10500;Rv=53500;Vn=3.3*Rg/(Rv-Rg) Vn = -0.805V below gnd
Rg=10500;Rv=53500;Vp=3.3*(2^16-Rv)/(Rv-Rg) Vp = 0.923V above vio
So that looks good enough to measure the clamp diodes, and to allow some outside-the-rails DC measurements. Most vendors specify ~ 300mV, to keep well clear of diodes.
A stable span suggests good resistor ratio matching, which is expected within one die.
Variable offsets will be the CMOS process deviations.
You could graph the equivalent threshold point variation (average of Vio and GND measurements) ?
Tubular, that all makes sense. The first inverter in the sense amp largely determines the offset level for each ADC.
Since ADC performance is entirely wrapped up in the pin circuit, there are no digital layout dependencies. So, they should all behave more-or-less the same. Same with the DAC's. Digital timing performance should be identical, too, when clocking is enabled. Turning on clocking is another way to get around the glitch-low problem.
A couple from cluster ends :
Rg=10250;Rv=53400;Vm=3.3*(((Rv+Rg)/2)-2^15)/(Rv-Rg) Vm = -72mV
Rg=10400;Rv=53400;Vm=3.3*(((Rv+Rg)/2)-2^15)/(Rv-Rg) Vm = -66.6mV
Rg=13000;Rv=55600;Vm=3.3*(((Rv+Rg)/2)-2^15)/(Rv-Rg) Vm = +118mV
Rg=12600;Rv=55600;Vm=3.3*(((Rv+Rg)/2)-2^15)/(Rv-Rg) Vm = +102mV
and near the middle of the pack
Rg=11500;Rv=54600;Vm=3.3*(((Rv+Rg)/2)-2^15)/(Rv-Rg) Vm = 21mV
Rg=11600;Rv=54600;Vm=3.3*(((Rv+Rg)/2)-2^15)/(Rv-Rg) Vm = 25mV
and the perfect 50.0% threshold would be 54036 at Rg = 11500
Rg=11500;Rv=54036;Vm=3.3*(((Rv+Rg)/2)-2^15)/(Rv-Rg) Vm = 0
ie looks like ~ +20mV offset and ±90mV variation from there, on the effective threshold point.
On 3.3V, ±90mV is ±2.72% which to me seems a little high for same-die matching ?
That means getting tracking across many ADCs is not going to be so easy, as they are all quite independent.
Measuring near a cal point (GND or VIO) might give better results
based on the above readings, if you nudge the capture time from 2^16 to about 50,000 that will scale to a 33000 difference on full scale (0.1mV LSB)
ADC calibration mode VIO and GIO average values are correlated. If GIO reads low, its VIO will also generally be lower, such that the 'span' is generally consistent.
Good, so that reduces the triple measurement to a double.
ADC calibration mode VIO and GIO average values are correlated. If GIO reads low, its VIO will also generally be lower, such that the 'span' is generally consistent.
Good, so that reduces the triple measurement to a double.
Not entirely, as you need to calibrate Spin and Offset, as well as read the User Value.
Offset variation seems higher than expected to me, for same-die. Anyone happen to know what P1 variation across pins is ?
ADC calibration mode VIO and GIO average values are correlated. If GIO reads low, its VIO will also generally be lower, such that the 'span' is generally consistent.
Good, so that reduces the triple measurement to a double.
Not entirely, as you need to calibrate Spin and Offset, as well as read the User Value.
Offset variation seems higher than expected to me, for same-die. Anyone happen to know what P1 variation across pins is ?
The reason the offsets vary so much is because you have a near minimum-sized inverter, several of them, making the determination of whether the integrator is high or low. Threshold is going to vary one to another
As usual the devil is in the details. Eg for reducing three to two measurements, the GIO measurements have an average standard deviation of 7.7, vs VIO which have a lower average standard deviation of 5.5. So yes, if you really must only do two readings, subtract GIO from the pin ADC reading. While GIO and VIO mostly correlate, throwing away that full three way calc probably loses half a bit of resolution.
I wouldn't call the span 'unchanging' - its just quite consistent compared to other things.
One thing we should have done while the P2D2 was on dry ice yesterday, was take 'cold' noise readings. Next time
Comments
It'll be interesting to see how they vary from pin to pin and chip to chip. Since those VIO and GIO calibration connections are purely internal, perhaps this is a way of obtaining a 'unique signature' of the silicon being tested. That would make for a kind of organic serial number.
Temperature and IO voltage (3v3, 3v0 etc) may affect the readings, and if they do, perhaps this paves the way to a method for not only measuring die temperature, but measuring die temperature near each pin.
How small was 'many small' -- I'd expect those to need to be higher resolution than the appx noise floor, or the quantization noise will bite.
ie going from 16b to 15 or 14 or 13 ? should buy more time to do more sum/average samples, but I'm not sure going from (eg) 16b to 8b helps.
Given the plots above, I'd suggest doing slightly faster (1/2/3 fewer bits) of the 3-sample readings, and then average on the net scaled results, rather than on each of the 3 samples.
Ozprop and I thought interleaving like this sequence would improve things a bit
GIO - Pinvoltage - VIO - Pinvoltage - GIO ... etc would provide a neat improvement
It feels like the VIO connection is 'lower impedance' - eg the stdev on the VIO readings was lower than GIO, and the freeze spray seemed also to affect it less. This may mean its not necessary to stare at VIO for as long,
Other improvements may come as we better understand the interactions - eg while every ADC may be slightly different, perhaps they can be measured and 'characterised', and once that model data and relationships are known, it may not be necessary to measure everything as intensively as we are currently.
It could be that different bit resolutions are slightly better than others? 16 bits is a great, optimistic starting point but things probably look more solid at 14 bits, for instance.
Then we can look at cross coupling readings, because we can read neighboring pins voltages on the ADC can't we Chip? PinB ADC modes?
You could bring same analog signal into two or more ADCs and see what happens
Really, there is so much flexibility with this chip. I think we'll still be discovering stuff years into the future.
Lonesock's idea might be worth chasing, so then the ADC can be left on non-stop.
Surely the drifting behaviour is all thermal. On that assumption, it should be possible to build a thermally induced translation of a neighbouring GIO/VIO to map to the target pin's equivalent GIO/VIO. Start with a high and low temperature set of averages for each.
If it's not a linear mapping then I guess it'll be a tall order to fill, but maybe linear is good enough.
It may be adding an external opamp and a '3157' SPCO analog switch could avoid the on-chip noise sources.
Of course, that's more parts, but for someone wanting 14~20 bits it can be cheaper than an external ADC.
Yes, it can do that, but the parasitics at 200MHz are going to make a mess of things. The ADC was designed to minimize parasitics internally, in order to get the performance up. I suspect that by increasing feedback current in the internal ADC (would lower input impedance), we might be able to push the noise down. What do you think?
Or are these disabled because you're trying to bias the reading node at 1.65v?
The sampling clock on the D-FF would be adjusted for lowest noise/highest bits. and would interact a little with the OpAmp chosen.
Integrator Opamp needs to be high slew but unity gain stable, with low Vos and good CMRR.
That does thin out the field, but something like OPA320 series looks a reasonable starting point ? (10v/us, Vos 40uV typ, CMRR 114dB typ)
Question is then does that pair with a 3157 (D-FF inside P2) , or can a 74AUP1G80 external D-FF do as well ?
Addit: Looking some more, I favour the external D-ff approach (74AUP1G80) as that supports more channels at one-pin-per added channel.
It also move the ADC analog-nodes cell into a nice separate area, and CLK is user defined SysCLK/N
TI part says 'Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3 V)"
NXP says "Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V."
- which is good to tolerate the sawtooth output from the integrator. (250mV and 10V/us is 40MHz max sampling clock region )
Or, you could connect a part like AMC1035 - indicated price $1.50, So8, Accepts 9 MHz to 21 MHz ClkIn, includes a 0.2%, ±10ppm typ Vref
http://www.ti.com/product/amc1035
What value is the series resistance ?
Higher current / lower impedance would help, but my feeling is it will be diminishing returns, with the poor PSRR present in a simple CMOS buffer.
There is a capacitor, an input current resulting in charge over time and compensating charges to keep the capacitors voltage constant.
Where errors can come from:
Imagine the capacitor changes his value, then, at given charge, the voltage will change. What makes the cap changing? Any current in the proximity will induce a magnetic field and influence the position of the electrons in the cap, so changing voltage. The same is true for voltages around, they also will create forces acting on the electrons ..
So first point: have no influence of any condition change on the cap. Surround the cap with vacuum ;-) or with a box, that is connected to ground, so the caps one electrode is a symmetric ground plane and the active electrode is inside.
You have to take care, that a given input voltage creates proportional current flow through the resistor. So this resistor has to be "perfect" what can not be the case using doped silicon. Metal resistors certainly are better, but are not feasible in the process, I guess. Anyway, the resistors also have to be shielded.
You have to take care, that the quanta of compensation charges are equal. If you use a voltage source to feed back charge, the current depends on the cap's current voltage. So it may make sense to have a separate cap to store the quanta and then transfer them to the balancing cap. Like in a CCD.
What about the sensing comparator? All problems with comparator we know will apply.
So whatever we do: we are deep in the business of ADC development, what definitly should not be the case.
Again: there is so much workload ahead, don't be delayed by solving problems, we don't have. We made a propeller in a common effort. Now let us use, what we have. And if we really believe, something must be corrected or optimized, we should look to use the possilities, given to us by great people!
If you shift down to 12 bits, is the result reasonably accurate and repeatable?
Good question - it will certainly be useful to have ADC operate in pin-drive cases.
I'm not sure I've seen any numbers yet for lower current source/sink & series resistor drive mode tests ?
Chip did say a single pin Cap-Osc can be built with own-pin-feedback and current drive, but that's not analog ADC mode.
You need to make DIR to the pin high. In smart pin mode the pin DIR can be set high by putting %01 in WRPIN data bits D[7:6].
For each Pin there is an 8192 element capture of its ADC connected to GIO (ADC connected to ground), and below that, a 8192 element capture of its ADC connected to VIO (ADC connected to local 3v3 VIO input).
For each pin, we came up with a simple 'quality score', being the sum of standard deviation of GIO data points plus standard deviation of VIO data points, to see if any pins were markedly better than others.
We found things were pretty consistent, would need to study several chips to form any meaningful conclusions. P28 seemed marginally the best (this is where the PLL is, right?, though its neighbors weren't stellar), and the corner pins may be marginally worse - needs further investigation.
This doesn't imply 5v tolerance necessarily, since currents would be large at the extremes, and a fancy diode bias arrangement would be needed for the P2
More useful might be the 'virtual overhead' numbers, in each direction (one+, one-), = where the ADC saturates, assuming no diodes present at all.
eg, I think those above could be (roughly)
(10.5k/53500)*3.3 = -0.647 below gnd
(13k/55500)*3.3 = -0.7729 below gnd
edit:
I think better is the span of v-g is mapped to 3.3V, and the remainder ratios to that. (this now matches your ~5V span)
Rg=10500;Rv=53500;Vn=3.3*Rg/(Rv-Rg) Vn = -0.805V below gnd
Rg=10500;Rv=53500;Vp=3.3*(2^16-Rv)/(Rv-Rg) Vp = 0.923V above vio
Rg=13000;Rv=55500;Vn=3.3*Rg/(Rv-Rg) Vn = -1.009V below gnd
Rg=13000;Rv=55500;Vp=3.3*(2^16-Rv)/(Rv-Rg) Vp = 0.779V above vio
So that looks good enough to measure the clamp diodes, and to allow some outside-the-rails DC measurements. Most vendors specify ~ 300mV, to keep well clear of diodes.
A stable span suggests good resistor ratio matching, which is expected within one die.
Variable offsets will be the CMOS process deviations.
You could graph the equivalent threshold point variation (average of Vio and GND measurements) ?
Since ADC performance is entirely wrapped up in the pin circuit, there are no digital layout dependencies. So, they should all behave more-or-less the same. Same with the DAC's. Digital timing performance should be identical, too, when clocking is enabled. Turning on clocking is another way to get around the glitch-low problem.
Checking some mid-point variations, gives
A couple from cluster ends :
Rg=10250;Rv=53400;Vm=3.3*(((Rv+Rg)/2)-2^15)/(Rv-Rg) Vm = -72mV
Rg=10400;Rv=53400;Vm=3.3*(((Rv+Rg)/2)-2^15)/(Rv-Rg) Vm = -66.6mV
Rg=13000;Rv=55600;Vm=3.3*(((Rv+Rg)/2)-2^15)/(Rv-Rg) Vm = +118mV
Rg=12600;Rv=55600;Vm=3.3*(((Rv+Rg)/2)-2^15)/(Rv-Rg) Vm = +102mV
and near the middle of the pack
Rg=11500;Rv=54600;Vm=3.3*(((Rv+Rg)/2)-2^15)/(Rv-Rg) Vm = 21mV
Rg=11600;Rv=54600;Vm=3.3*(((Rv+Rg)/2)-2^15)/(Rv-Rg) Vm = 25mV
and the perfect 50.0% threshold would be 54036 at Rg = 11500
Rg=11500;Rv=54036;Vm=3.3*(((Rv+Rg)/2)-2^15)/(Rv-Rg) Vm = 0
ie looks like ~ +20mV offset and ±90mV variation from there, on the effective threshold point.
On 3.3V, ±90mV is ±2.72% which to me seems a little high for same-die matching ?
That means getting tracking across many ADCs is not going to be so easy, as they are all quite independent.
Measuring near a cal point (GND or VIO) might give better results
based on the above readings, if you nudge the capture time from 2^16 to about 50,000 that will scale to a 33000 difference on full scale (0.1mV LSB)
Rg=10500;Rv=53750;2^16*33000/(Rv-Rg) = 50004
Rg=11500;Rv=54750;2^16*33000/(Rv-Rg) = 50004
Rg=12750;Rv=55500;2^16*33000/(Rv-Rg) = 50589
( or 25,000 capture time will be 0.2mV LSB, and closer to the analog noise floor )
We'll likely go back and repeat at least some of the testing at a much lower frequency, when we have time.
Good, so that reduces the triple measurement to a double.
Not entirely, as you need to calibrate Spin and Offset, as well as read the User Value.
Offset variation seems higher than expected to me, for same-die. Anyone happen to know what P1 variation across pins is ?
The reason the offsets vary so much is because you have a near minimum-sized inverter, several of them, making the determination of whether the integrator is high or low. Threshold is going to vary one to another
Offset is acquired from either GIO or VIO, hence only dual measurements.
I wouldn't call the span 'unchanging' - its just quite consistent compared to other things.
One thing we should have done while the P2D2 was on dry ice yesterday, was take 'cold' noise readings. Next time