What's missing is a cap from the pin pad to VDDIO. This was always recommended in any P1 sigma-delta circuit to balance out the effects of power supply noise. Does the P2 have that cap?
Is the feedback free running or clocked? If free running one could have an up/down counter to count the switching events and so have some additional information about the capacitors charge.
And: if the feedback voltage is derived from an DAC, the ADC can multiply two values.
Is the feedback free running or clocked? If free running one could have an up/down counter to count the switching events and so have some additional information about the capacitors charge.
And: if the feedback voltage is derived from an DAC, the ADC can multiply two values.
Feedback is from the D-FF.Q and that is clocked.
The .Q acts as a 1-bit DAC, (I think Chip has mentioned a current switch, so it is a current-DAC) and the average of that matches the average input voltage, with all the noise sources contributing.
The CMOS inverters have very poor PSRR, (/2), meaning a noisy supply is merely halved onto the summing node.
If you use a low noise, precision reference supply to an external D-FF, and a true integrator opamp, some of those noise/thermal effect sources can be removed.
EDIT: More questions: When DAC level is being set by smartpin/cog/streamer, does this get clocked into the custom pin DAC register, or is the register bypassed? EDIT2: Or does that not exist in the pad ring?
In BIT_DAC mode, is OUT clocked to select DAC level?
Also in BIT_DAC mode, does IN have a job?
Is the feedback free running or clocked? If free running one could have an up/down counter to count the switching events and so have some additional information about the capacitors charge.
And: if the feedback voltage is derived from an DAC, the ADC can multiply two values.
Feedback is from the D-FF.Q and that is clocked.
The .Q acts as a 1-bit DAC, (I think Chip has mentioned a current switch, so it is a current-DAC) and the average of that matches the average input voltage, with all the noise sources contributing.
The CMOS inverters have very poor PSRR, (/2), meaning a noisy supply is merely halved onto the summing node.
If you use a low noise, precision reference supply to an external D-FF, and a true integrator opamp, some of those noise/thermal effect sources can be removed.
I do not believe, it makes sense to change something at the ADC circuit, if there is not a severe design flaw. The point is: this is a current based adc, as the voltage of the cap only changes if current flows in or out. As the cap is fed from an analog current and a digital current, at no moment the voltage of the cap is constant, there is always either surplus of charge flowing to the cap or shortage. And the comparator just detects the voltage change. If the charge quantum fed by the FF is not able to trigger the comparator, then more then one clocks will work into the same direction, so the readout will only by accident be +-1. If the charge quantum always triggers the comparator +- then readout will be more reactive. The drawback is, that the cap voltage now is not "constant", what means, the input resistor creates a current depending of input voltage and capacitor voltage, so the linearity is reduced.
I personally believe, having a small cap, so the voltage oscillates +- the comparators threshold every clock should be best, but don't know, if such a cap can be manufactured, which stray effects occur or how all the tolerances come together.
Here are some simulations I just ran of the ADC in GIO-calibration mode.
The ADC side of the 440k input resistor is held precisely at VIO/2 via an unclocked analog feedback loop, causing a live difference current to continuously drive the integrator cap up or down in opposition to the fixed-current, clocked, negative feedback.
The clocked feedback provides a constant positive or negative correction current to keep the integrator voltage at the sense-amp inverter string's threshold.
Because the input and feedback are both in current form, the exact voltage of the integrator does not matter. The inverter string used as a sense amp decides if the integrator is '0' or '1' and that state is registered in a flop whose output is used to drive the negative feedback current. The threshold voltage of the inverter string varies slightly in each pin, but by calibrating for GIO and VIO, that offset error can be removed.
Here are plots of the integrator voltage and ADC output at both 250MHz and 1MHz. At 250MHz, the integrator voltage moves ~4mV per clock cycle most of the time, while at 1MHz, the voltage moves ~1.0V most of the time. At 250x the clock period there is 250x the voltage movement, as should be.
I don't think I really considered 1MHz ADC operation during design, but it's fortunate that due to the high linearity of the circuit, it actually works over such broad frequency range.
I reduced the integrator capacitance to 1/8th its current value and, sure enough, there is a lot more voltage swing on the integrator cap at 250MHz. It would now perform at 8MHz like the silicon currently does at 1MHz.
At 250MHz with 1/8th the integrator capacitance, the sample stream is less clumpy, since the inverter-chain sense-amp can resolve faster, with more voltage change.
I have a question: Have you guys noticed any difference in the ADC's resolving power relative to clock frequency? In theory, there shouldn't be much difference, but I wonder. It seems to be flat, from what we've all observed, so far. The reality is that with more voltage swing, precision current sources should exhibit some slight impedance changes. Ideally, a current source has infinite impedance, so that no matter the load voltage it drives, the current is exactly the same. For this reason, I suspect that the less the integrator cap voltage swings, the more accurate the circuit should be, as there's less occasion for impedance changes.
Here's the ADC clocking at 250MHz in GIO calibration mode with 1/8th the integrator capacitance. You can see that the feedback stream has been nicely de-clumped from the current 250MHz performance. This is due to 8x the voltage swing on the integrator cap, which is raising the bottom viable frequency by 8x (to maybe 8MHz):
Here are some simulations I just ran of the ADC in GIO-calibration mode.
If you probe the 4 x inverters, what do those nodes look like ?
Can you add layout-related series inductances in the supply leads of each inverter and some common mode inductance ?
Here are some simulations I just ran of the ADC in GIO-calibration mode.
If you probe the 4 x inverters, what do those nodes look like ?
Can you add layout-related series inductances in the supply leads of each inverter and some common mode inductance ?
They are laid out right in a row with common GIO and VIO rails. I don't think the inductance would be much there, but the power bus routing in could have some slight inductance.
The first inverters hardly change state, but by the 4th (there are six, it turns out, not four), there is enough change to flip the D input of the flop.
Here is a simulation of the ADC running clock-less, by bypassing the flipflop, in GIO calibration mode. The bottom trace is the integrator cap voltage. The next up is after the first inverter, then the second, the third, all the way up to the sixth inverter output which goes to the D input of the flop. Note that the D input captures the NOT of the actual state, so it's inverted.
Wow! What a good team of quantum-dwarfs had you brought to that screenplay!
Does the tools also allow you to preview the time elapsed at each stage, as each one "senses" the transitions at its input and forwards the result to its output, including the flip-flop input stage?
Wow! What a good team of quantum-dwarfs had you brought to that screenplay!
Does the tools also allow you to preview the time elapsed at each stage, as each one "senses" the transitions at its input and forwards the result to its output, including the flip-flop input stage?
Yes, you can zoom in on the horizontal and see the propagation delay. Here the last three inverter outputs are, interposed together. Timescale is 500ps per division:
Chip,
Is that really GIO-calibration? The capacitor charging rate seems inverted to me. I would have thought it would pull down toward GIO faster than up.
I have a question: Have you guys noticed any difference in the ADC's resolving power relative to clock frequency? In theory, there shouldn't be much difference, but I wonder. It seems to be flat, from what we've all observed, so far. The reality is that with more voltage swing, precision current sources should exhibit some slight impedance changes.
I wouldn't call it anything consistent but there was a lot more deviations in the VIO vs GIO scatter plots below 100 MHz. The plot lines tended to show more zigzag at 20-80 MHz end.
It is GIO calibration mode. It only goes 'up' once in a while.
No, I mean the regular slope. It charges faster than discharges. That seems opposite to what I imagined because two sources pulling in one direction should steepen the slope.
It is GIO calibration mode. It only goes 'up' once in a while.
No, I mean the regular slope. It charges faster than discharges. That seems opposite to what I imagined because two sources pulling in one direction should steepen the slope.
I think you are right, the input signal here must be Vcc, GIO will have a mirrored CAP voltage.
It is GIO calibration mode. It only goes 'up' once in a while.
No, I mean the regular slope. It charges faster than discharges. That seems opposite to what I imagined because two sources pulling in one direction should steepen the slope.
Ay, It's confusing to me, too. Okay, it seems the signal current and feedback current are inverted, so the integrator voltage looks upside-down. I didn't remember this. I don't even remember making it this way, but I did.
It's inverted because the continuous analog circuit that converts Vadc-VIO/2 into current is negative-feedback, internally, and I borrow its bias to generate the current that goes into the integrator. To make it work like one would assume it should work would require an addition inversion stage, which would just introduce more distortion.
Hmm, that means you've got some active analogue between the pin-pad and the dividers.
Yes, the pin is actually pulled to VIO/2, not an inverter's threshold. I explained it wrong a while back.
There is an analog input circuit, after the selection resistors, which converts 'Vadc-VIO/2' into +/- current. Having pure current allows the thing to run over a really wide clock frequency range, since the integrator can go up and down, spanning a few volts, without the voltage across a simple input resistor changing with the integrator, while the analog input remains the same, causing huge current errors. The current for both input and feedback are very high-impedance, so they don't change with integrator voltage.
Early on, I realized that a simple resistor going into an integrator limited performance to 7 bits, or so, given the practical size of a integrator cap totalling only a few pF and a 1M-ohm input resistor. Once I got things into current mode, things got way better.
Ay, It's confusing to me, too. Okay, it seems the signal current and feedback current are inverted, so the integrator voltage looks upside-down. I didn't remember this. I don't even remember making it this way, but I did.
It's inverted because the continuous analog circuit that converts Vadc-VIO/2 into current is negative-feedback, internally, and I borrow its bias to generate the current that goes into the integrator. To make it work like one would assume it should work would require an addition inversion stage, which would just introduce more distortion.
That means the circuit is not what was drawn above, but has more elements. (and likely more noise sources...)
Is there a full circuit somewhere ?
Comments
I can't remember if you've shown a diagram of the ADC or not. Does this describe it?
EDIT: Here's the KiCad files
I'd say that's close. Do you plan to simulate this on KiCad ? I've not pushed into that area yet, it would certainly be interesting.
I'd suggest using 74AUP1GU04 as the inverters, and you can save one inverter by using a 74AUP1G80.
-Phil
That's it, basically. Add one more cap at the RC Junction to VIO. Instead of two series'd inverters, there are four.
And: if the feedback voltage is derived from an DAC, the ADC can multiply two values.
Feedback is from the D-FF.Q and that is clocked.
The .Q acts as a 1-bit DAC, (I think Chip has mentioned a current switch, so it is a current-DAC) and the average of that matches the average input voltage, with all the noise sources contributing.
The CMOS inverters have very poor PSRR, (/2), meaning a noisy supply is merely halved onto the summing node.
If you use a low noise, precision reference supply to an external D-FF, and a true integrator opamp, some of those noise/thermal effect sources can be removed.
Chip,
What's value of C?
EDIT: More questions: When DAC level is being set by smartpin/cog/streamer, does this get clocked into the custom pin DAC register, or is the register bypassed? EDIT2: Or does that not exist in the pad ring?
In BIT_DAC mode, is OUT clocked to select DAC level?
Also in BIT_DAC mode, does IN have a job?
I personally believe, having a small cap, so the voltage oscillates +- the comparators threshold every clock should be best, but don't know, if such a cap can be manufactured, which stray effects occur or how all the tolerances come together.
The ADC side of the 440k input resistor is held precisely at VIO/2 via an unclocked analog feedback loop, causing a live difference current to continuously drive the integrator cap up or down in opposition to the fixed-current, clocked, negative feedback.
The clocked feedback provides a constant positive or negative correction current to keep the integrator voltage at the sense-amp inverter string's threshold.
Because the input and feedback are both in current form, the exact voltage of the integrator does not matter. The inverter string used as a sense amp decides if the integrator is '0' or '1' and that state is registered in a flop whose output is used to drive the negative feedback current. The threshold voltage of the inverter string varies slightly in each pin, but by calibrating for GIO and VIO, that offset error can be removed.
Here are plots of the integrator voltage and ADC output at both 250MHz and 1MHz. At 250MHz, the integrator voltage moves ~4mV per clock cycle most of the time, while at 1MHz, the voltage moves ~1.0V most of the time. At 250x the clock period there is 250x the voltage movement, as should be.
I don't think I really considered 1MHz ADC operation during design, but it's fortunate that due to the high linearity of the circuit, it actually works over such broad frequency range.
At 250MHz with 1/8th the integrator capacitance, the sample stream is less clumpy, since the inverter-chain sense-amp can resolve faster, with more voltage change.
I have a question: Have you guys noticed any difference in the ADC's resolving power relative to clock frequency? In theory, there shouldn't be much difference, but I wonder. It seems to be flat, from what we've all observed, so far. The reality is that with more voltage swing, precision current sources should exhibit some slight impedance changes. Ideally, a current source has infinite impedance, so that no matter the load voltage it drives, the current is exactly the same. For this reason, I suspect that the less the integrator cap voltage swings, the more accurate the circuit should be, as there's less occasion for impedance changes.
Here's the ADC clocking at 250MHz in GIO calibration mode with 1/8th the integrator capacitance. You can see that the feedback stream has been nicely de-clumped from the current 250MHz performance. This is due to 8x the voltage swing on the integrator cap, which is raising the bottom viable frequency by 8x (to maybe 8MHz):
I think 11 bit ADC is fine...
If there's something simple we could do to get a few more bits out of it, that would be great.
Yes. Use 1-bit WFBYTE mode to sample a pin on each clock and write it to hub every 8 clocks. That would let you get the bitstream, anyway.
Can you add layout-related series inductances in the supply leads of each inverter and some common mode inductance ?
They are laid out right in a row with common GIO and VIO rails. I don't think the inductance would be much there, but the power bus routing in could have some slight inductance.
The first inverters hardly change state, but by the 4th (there are six, it turns out, not four), there is enough change to flip the D input of the flop.
Here is a simulation of the ADC running clock-less, by bypassing the flipflop, in GIO calibration mode. The bottom trace is the integrator cap voltage. The next up is after the first inverter, then the second, the third, all the way up to the sixth inverter output which goes to the D input of the flop. Note that the D input captures the NOT of the actual state, so it's inverted.
Does the tools also allow you to preview the time elapsed at each stage, as each one "senses" the transitions at its input and forwards the result to its output, including the flip-flop input stage?
Yes, you can zoom in on the horizontal and see the propagation delay. Here the last three inverter outputs are, interposed together. Timescale is 500ps per division:
Is that really GIO-calibration? The capacitor charging rate seems inverted to me. I would have thought it would pull down toward GIO faster than up.
It is GIO calibration mode. It only goes 'up' once in a while.
I wouldn't call it anything consistent but there was a lot more deviations in the VIO vs GIO scatter plots below 100 MHz. The plot lines tended to show more zigzag at 20-80 MHz end.
No, I mean the regular slope. It charges faster than discharges. That seems opposite to what I imagined because two sources pulling in one direction should steepen the slope.
Ay, It's confusing to me, too. Okay, it seems the signal current and feedback current are inverted, so the integrator voltage looks upside-down. I didn't remember this. I don't even remember making it this way, but I did.
Yes, the pin is actually pulled to VIO/2, not an inverter's threshold. I explained it wrong a while back.
There is an analog input circuit, after the selection resistors, which converts 'Vadc-VIO/2' into +/- current. Having pure current allows the thing to run over a really wide clock frequency range, since the integrator can go up and down, spanning a few volts, without the voltage across a simple input resistor changing with the integrator, while the analog input remains the same, causing huge current errors. The current for both input and feedback are very high-impedance, so they don't change with integrator voltage.
Early on, I realized that a simple resistor going into an integrator limited performance to 7 bits, or so, given the practical size of a integrator cap totalling only a few pF and a 1M-ohm input resistor. Once I got things into current mode, things got way better.
That means the circuit is not what was drawn above, but has more elements. (and likely more noise sources...)
Is there a full circuit somewhere ?