I turned off some nearby equipment and led light and the voltage roughly halved. That indicates external factors at least partly to blame, so time to move on to other measurements. Sorry for the diversion
That means some DC restoration effects, on top of the leakage.
If we assume the new ~ 150mV is the average DC (no restore effects) that indicated appx 4.5nA of bias current.
I wonder whether what we're seeing is simply the proximity of pins to nearby positive rails, and absence of any GND pins. If thats the case we should see some pins heading for 1v8 and others heading for 3v3, right?
Yes.
You could check that, with a bridge ( AC fields reduced, of course ) where you have a simple pot or another power supply, and connect the 10G meter between P2 Pin and Vp, and vary until meter says 0, then check Vp.
I think our ADC limitations have everything to do with 1/f, or flicker, noise. It's low frequency and can't be filtered out. It's a part of reality that we can't be completely rid of. I'm trying to figure out how to handle it best.
There is more than one effect in play here .
Noise is very hard to chase down in Spice, but for the indicated thermal effects you should be able to simulate, if OnSemi's models include Tempco variances, and include ppm/'C/V effects too.
What ppm does On Semi predict, and what tracking in those ?
Some web data suggests ~200pm/'C for P+ poly ? (that's 1% over 50'C change)
Web info suggests R's track ~15 times better than absolute tolerance, maybe tempcos track 10x, 6x , 5x ? It would be nice to know the expected tempco tracking.
A bench test could check real P2 ppm, with a uA meter in series with Analog Pins, connected to GND or Vio, and the chip heated.
10 pins in parallel would given an average tempco, and one pin at a time would give some spread indication.
Doing this to both GND and VIO should show any voltage bias changes in tempco effects, which the scatter plots suggest are there.
This gives absolute tempco.
(maybe also choose some outliers on the scatter graphs, and some centroid ones, and see if meter tests can confirm their placement)
Measure of a floating-pin (ADC operating) using a bridge scheme (meter connects to external 1.65V or VIO/2), and again 10/20 pins in parallel would indicate average, and individual pins could show variance.
Static voltage error from the ideal, shows resistor value matching, and 'C variance shows the tempco matching of the internal VIO/2 resistor pair.
(another meter can use a +ve clamp diode to check Die temperature)
It's been over 10 years since I last sourced an A/D converter. But at that time, any A/D converter over 12 bits was actually just a 12 bit converter with a preamplifier.
So if you wanted 14 bits, you would program it for 4x gain, but then also have 1/4 the input range. Ultra lame. Is this still the case in 2018?
It's been over 10 years since I last sourced an A/D converter. But at that time, any A/D converter over 12 bits was actually just a 12 bit converter with a preamplifier.
So if you wanted 14 bits, you would program it for 4x gain, but then also have 1/4 the input range. Ultra lame. Is this still the case in 2018?
PGA's are a still common, but no, ADC's over 12 bits will give better than 12 bits of dynamic range.
When you chase better than 16 bits, the quality of your reference certainly matters. At 16 bits, 1 LSB is 15ppm, so any reference even as good as ±3ppm, could walk 1 LSB over just 5 degrees.
Of course price is inversely related to ppm and %
eg
MAX6070AAUT25+T 2.5V SOT23 10mA ±0.04% 6ppm/°C 4.8µVp-p 3µVrms 2.8 V ~ 5.5 V 300µA is $1.5557/3k
ADR4520BRZ-R7 2.048V 8SOIC 10mA ±0.02% 2ppm/°C is $4.6575/3k
LT6657AHMS8-3#PBF 3V 8MSOP 10mA ±0.1% 1.5ppm/°C 0.5ppmp-p 0.8ppmrms 3.5 V ~ 40 V is $6.528/3k
I started looking at the ADC mode potential as exposed with the TT=%11 bits. This only seems to work for even pins, and to be honest I'm not 100% confident the mode is set up. The setup word is
I started looking at the ADC mode potential as exposed with the TT=%11 bits. This only seems to work for even pins, and to be honest I'm not 100% confident the mode is set up. The setup word is
I think we might drop down to 20 MHz from now on to limit the self heating.
Which mode is this exactly ?
Is this the P1-emulate ? I think that shows as mode 011 in Chip's table, with a OUT and D-FF type feedback ?
Maybe that does have a pair-style limitation, because it is a 2-pin structure ?
or is this just ADC running, and reading the floating ADC in, which should give the MID point tracking. For this mode, it would be useful to know the exact 3.3V level ?
( 1.641*2 = 3.282 1.632*2 = 3.264 ) Error span appx 0.85%
This should not have any pair-limit ?
Least-error for that reading would be Gain = 100x, but with a G-Ohm meter the IP series R might not matter too much.
Today I spent a bit of time with the DACs. These are working really well, I was just curious what the worst code transition was. Turns out its from 15 to 16 and from 31 to 32, rather than the usual 127 to 128, but they are only marginally worse than the standard step case.
Here's the graph stepping through 4 DACs in turn, as well as a very zoomed-in picture of the step sizes obtained by adding 4 DAC values together.
I was going to start a new thread for DACs, but since there isn't much to complain about, I'll just post here.
Measurements were taken by adapting the P2 program to put out a 'initiate reading' pulse after each DAC step transition. The pin mode just steps from %10100_00000000 to %10111_11111111, which takes it through the 3v3 990 ohm DAC, 2v 600 ohm DAC, 3v3 123 ohm DAC, then 2v 75 ohm DAC. Measurements were in High-Z mode (not ideal), 10 PLC, board 2, room temperature ~ 20C, 80 MHz master clock.
...
Measurements were taken by adapting the P2 program to put out a 'initiate reading' pulse after each DAC step transition. The pin mode just steps from %10100_00000000 to %10111_11111111, which takes it through the 3v3 990 ohm DAC, 2v 600 ohm DAC, 3v3 123 ohm DAC, then 2v 75 ohm DAC. Measurements were in High-Z mode (not ideal), 10 PLC, board 2, room temperature ~ 20C, 80 MHz master clock.
What recorded the DAC voltage ? Was that a P2 ADC reading, or some external ADC ?
What was the expected (ideal) DAC step size - it looks to average slightly under 0.0415, whatever units those are ?
I also spent a bit of time having a preliminary look at the 1mA, 100uA, 10uA current sources that can be selected for high or low side pin driving.
It was only a preliminary look, but at room temperature, these are all reading a few percent (3~6%) "under".
Given these are not calibrated, that's remarkably close. Usually you would expect maybe 20% for uncalibrated / raw values.
What recorded the DAC voltage ? Was that a P2 ADC reading, or some external ADC ?
What was the expected (ideal) DAC step size - it looks to average slightly under 0.0415, whatever units those are ?
Recording done by the external multimeter in high-Z mode. It has a 10,000 reading buffer, in effect I let it run for 1024 samples with a DAC increment between each reading.
What recorded the DAC voltage ? Was that a P2 ADC reading, or some external ADC ?
What was the expected (ideal) DAC step size - it looks to average slightly under 0.0415, whatever units those are ?
Recording done by the external multimeter in high-Z mode. It has a 10,000 reading buffer, in effect I let it run for 1024 samples with a DAC increment between each reading.
Nice setup.
Is this the basis for the 2nd DAC plot ?
3.3/255+2/255+3.3/255+2/255 = 0.041568
- doing that may average some errors, so separate plots could be more useful, with a Vmax included to show the expected ideal step size.
With 3v3 990 ohm DAC, 2v 600 ohm DAC, 3v3 123 ohm DAC, then 2v 75 ohm DAC I'd expect the errors to vary by DAC, with perhaps the 990 ohm one best, and 2V 75 ohm worse.
The 2V will also be nominal.
Given these are not calibrated, that's remarkably close. Usually you would expect maybe 20% for uncalibrated / raw values.
I don't know what to expect, but just having the current sources there seems useful.
Yes, Chip did a nifty single-pin triangle oscillator using a cap and the internal current sources.
There should be an inductor equivalent oscillator, and this could even work on a LC oscillator too ?
Also, I'm pretty sure I was measuring a pseudo random stream, rather than midpoint voltages, before. Which explains why it only worked on even pins.
Do you mean the DAC was smart pin dithered as in "DAC 16-bit with pseudo-random dither" ?
I see this comment in the DOCs "If OUT is high, the ADC will be enabled and RDPIN/RQPIN can be used to retrieve the 16-bit ADC accumulation from the last sample period. This can be used to measure loading on the DAC pin."
If you have an external ADC and DAC sweep all nicely working here, can you add that mentioned P2-ADC capture, so the P2-ADC errors can be plotted across the whole ADC range ?
External meter collects the precise applied voltage (via the DAC), and the ADC reports the P2 value ?
- doing that may average some errors, so separate plots could be more useful, with a Vmax included to show the expected ideal step size.
You're right and I'll come back to this. I did measure vmax at 3.3059v at the start but of course it can wander a bit. I'm thinking it may be possible to interleave into the readings, in between each DAC step. Then it becomes a bit like the internal autocalibration, and just takes a bit more time.
With 3v3 990 ohm DAC, 2v 600 ohm DAC, 3v3 123 ohm DAC, then 2v 75 ohm DAC I'd expect the errors to vary by DAC, with perhaps the 990 ohm one best, and 2V 75 ohm worse.
The 2V will also be nominal.
Right, I'm curious how close the DACs get to the rails - that earlier test showed something like 6mv from GIO and 2mV from VIO, I think. That'll likely vary by DAC too
Yes, Chip did a nifty single-pin triangle oscillator using a cap and the internal current sources.
There should be an inductor equivalent oscillator, and this could even work on a LC oscillator too ?
Yeah that was really neat. We should be able to sweep in frequency too. Pin by pin bode plots
Do you mean the DAC was smart pin dithered as in "DAC 16-bit with pseudo-random dither" ?
I see this comment in the DOCs "If OUT is high, the ADC will be enabled and RDPIN/RQPIN can be used to retrieve the 16-bit ADC accumulation from the last sample period. This can be used to measure loading on the DAC pin."
I think it was the random noise source, only available to even pins. That would explain it
If you have an external ADC and DAC sweep all nicely working here, can you add that mentioned P2-ADC capture, so the P2-ADC errors can be plotted across the whole ADC range ?
External meter collects the precise applied voltage (via the DAC), and the ADC reports the P2 value ?
If we're going to do this properly, perhaps the following sequence should be followed
[code]
For each board 1 to 2
For each pin 0..61
For each DAC 990R to 75R
For each DAC code 0 through 255,
For each repeated measurement 1 to 3 (if required, for confidence)
"Fast" output GIO (~16 ohm resistance). Measure using both DMM and P2 ADC
Set DAC level and measure. Measure using both DMM and P2 ADC
"Fast" output VIO (~19 ohm resistance). Measure using both DMM and P2 ADC
[/quote]
The trouble is that the multimeter memory won't take enough readings. But, the above would give good coverage. I would probably want to get some more stability on temperature though, at least a fan or two
The variables not being looked at (at the moment) include VIO variation (eg running at 2v5 or 1v8), master clock frequency, and temperature.
If we're going to do this properly, perhaps the following sequence should be followed
For each board 1 to 2
For each pin 0..61
For each DAC 990R to 75R
For each DAC code 0 through 255,
For each repeated measurement 1 to 3 (if required, for confidence)
"Fast" output GIO (~16 ohm resistance). Measure using both DMM and P2 ADC
Set DAC level and measure. Measure using both DMM and P2 ADC
"Fast" output VIO (~19 ohm resistance). Measure using both DMM and P2 ADC
I like doing triangle sweeps, so the DAC is 0..255 then 255..0, that gives confidence and it saves 1 pass here.
If the memory is limited, you could do each DAC separately ?
Tubular, it would be good to measure the DACs separately. I'm looking at that stepping in the LSBs. I suspect the wild stepping is coming from the lower-impedance DAC, as its resistive elements self-heat and become more resistive.
Right, I'm curious how close the DACs get to the rails - that earlier test showed something like 6mv from GIO and 2mV from VIO, I think. That'll likely vary by DAC too
The 990R DAC gets within about 3.6mV of locally outputted GIO, VIO potentials
The 123R DAC gets within about 0.6mV of locally outputted GIO, VIO potentials
These are small compared to the nominal step size 12.94mV, but can't be completely written off
In addition, there's about 0.9mV of voltage rise between negative power input terminal and GIO. Estimating 1v8 current about 300mA flowing in that path (I see about .11A at 5v rail), thats an approx impedance of 0.003 ohms.
Here are some graphs looking at the 123R DAC, including error from line of best fit.
Some of these look dramatic, but are zoomed right in.
It took a while to get the measurement technique right. I had this odd transition going around code 92, turns out thats where the multimeter shifts range, and takes a moment to do so, throwing the integrating measurements out.
Edit: Where possible, I used blue markers for the increasing ramp (codes 0 to 255), and orange for the decreasing ramp (codes 255 downto 0)
Here are some graphs looking at the 123R DAC, including error from line of best fit.
Some of these look dramatic, but are zoomed right in.
It took a while to get the measurement technique right. I had this odd transition going around code 92, turns out thats where the multimeter shifts range, and takes a moment to do so, throwing the integrating measurements out.
Edit: Where possible, I used blue markers for the increasing ramp (codes 0 to 255), and orange for the decreasing ramp (codes 255 downto 0)
Nice plots !
The plot Board 2 Pin 0 DAC (123R) Voltage on upramp vs downramp, by code
might be showing us the Power supply noise. Are those Y units volts ? -> 150uV peak noise ? seems plausible.
The plot Board 2 Pin 0 DAC (123R) Error vs line of best fit
Is that one-up, one down, and the clusters are the sub-bit groupings.
ie looks like they are largely packets of 8, so 3 LSB's are one form, then a slight change occurs on next bits
The bottom 3, and top 5 are grouped in sets of 8, then middle ones disperse some more, > 150 they are 2 sets of 4.
Are they Y units Volts ? with the nominal step size 12.94mV 0..240 are within about 1.5mV, and > 240 spreads to 2.5mV
I think that's indicating ~11.1 bits for the < 240 area, and ~10.3 bits for the complete range.
For one on every pin, that's quite impressive. Dithering seems worth it, tho 16 bits may be optimistic.
I guess the random dither will 'join the dots' into more continual curves, but the non-linearity of the 'S' curve will remain.
Right, I'm curious how close the DACs get to the rails - that earlier test showed something like 6mv from GIO and 2mV from VIO, I think. That'll likely vary by DAC too
It took a while to get the measurement technique right. I had this odd transition going around code 92, turns out thats where the multimeter shifts range, and takes a moment to do so, throwing the integrating measurements out.
Does that range-change also change load ?
IIRC the bench meters here have a hi-Z mode, but only on the lowest range, when no divider is switched in. I think they have an auto-range-off option, to avoid steps.
I took the range change out and just operated on a fixed 10v range. Input impedance 10Megohm. This meter offers High Z on 100mv, 1V, 10V ranges, but not the 100V range.
Here's a 'bonus graph' - the supply current drawn on the 5V rail as the 123R DAC runs through the different codes, 0 to 255
It was easy to run this test while things are set up, just replace voltage with current measurement and repeat the cycle.
Master clock frequency is 80 MHz, and then addition of the current meter drops the voltage at the board terminals a bit, which causes the XCL220 switching regulator to draw about 5~10% more current.
Comments
I think the effort is just a basic reality check. Is there some optimization possible? If so, what does it take?
Once answered, it's answered.
10 bits is super useful. Software and willpower will get a couple more bits out of that.
Video digitization? Maybe we can make an upgraded one of these:
https://www.retrothing.com/2005/11/fisherprice_pxl.html
That means some DC restoration effects, on top of the leakage.
If we assume the new ~ 150mV is the average DC (no restore effects) that indicated appx 4.5nA of bias current.
Yes.
You could check that, with a bridge ( AC fields reduced, of course ) where you have a simple pot or another power supply, and connect the 10G meter between P2 Pin and Vp, and vary until meter says 0, then check Vp.
There is more than one effect in play here .
Noise is very hard to chase down in Spice, but for the indicated thermal effects you should be able to simulate, if OnSemi's models include Tempco variances, and include ppm/'C/V effects too.
What ppm does On Semi predict, and what tracking in those ?
Some web data suggests ~200pm/'C for P+ poly ? (that's 1% over 50'C change)
Web info suggests R's track ~15 times better than absolute tolerance, maybe tempcos track 10x, 6x , 5x ? It would be nice to know the expected tempco tracking.
A bench test could check real P2 ppm, with a uA meter in series with Analog Pins, connected to GND or Vio, and the chip heated.
10 pins in parallel would given an average tempco, and one pin at a time would give some spread indication.
Doing this to both GND and VIO should show any voltage bias changes in tempco effects, which the scatter plots suggest are there.
This gives absolute tempco.
(maybe also choose some outliers on the scatter graphs, and some centroid ones, and see if meter tests can confirm their placement)
Measure of a floating-pin (ADC operating) using a bridge scheme (meter connects to external 1.65V or VIO/2), and again 10/20 pins in parallel would indicate average, and individual pins could show variance.
Static voltage error from the ideal, shows resistor value matching, and 'C variance shows the tempco matching of the internal VIO/2 resistor pair.
(another meter can use a +ve clamp diode to check Die temperature)
So if you wanted 14 bits, you would program it for 4x gain, but then also have 1/4 the input range. Ultra lame. Is this still the case in 2018?
PGA's are a still common, but no, ADC's over 12 bits will give better than 12 bits of dynamic range.
When you chase better than 16 bits, the quality of your reference certainly matters. At 16 bits, 1 LSB is 15ppm, so any reference even as good as ±3ppm, could walk 1 LSB over just 5 degrees.
Of course price is inversely related to ppm and %
eg
MAX6070AAUT25+T 2.5V SOT23 10mA ±0.04% 6ppm/°C 4.8µVp-p 3µVrms 2.8 V ~ 5.5 V 300µA is $1.5557/3k
ADR4520BRZ-R7 2.048V 8SOIC 10mA ±0.02% 2ppm/°C is $4.6575/3k
LT6657AHMS8-3#PBF 3V 8MSOP 10mA ±0.1% 1.5ppm/°C 0.5ppmp-p 0.8ppmrms 3.5 V ~ 40 V is $6.528/3k
wrpin ##%100010_0000000_11_01111_0,#p 'ADC,AIO,1x,Fast,Fast
Running on
- Board 2
- 80 MHz clock,
- Room Temp ~17C, IC temp ~35C,
- Hi-Z input mode on the 461A multimeter
- Consuming about 110mA on 5V rail
Results
Pin P0 = 1.636V
Pin P2 = 1.632V
Pin P4 = 1.635V
Pin P6 = 1.646V
Pin P8 = 1.641V
Pin 10 = 1.641V
I think we might drop down to 20 MHz from now on to limit the self heating.
Which mode is this exactly ?
Is this the P1-emulate ? I think that shows as mode 011 in Chip's table, with a OUT and D-FF type feedback ?
Maybe that does have a pair-style limitation, because it is a 2-pin structure ?
or is this just ADC running, and reading the floating ADC in, which should give the MID point tracking. For this mode, it would be useful to know the exact 3.3V level ?
( 1.641*2 = 3.282 1.632*2 = 3.264 ) Error span appx 0.85%
This should not have any pair-limit ?
Least-error for that reading would be Gain = 100x, but with a G-Ohm meter the IP series R might not matter too much.
Here's the graph stepping through 4 DACs in turn, as well as a very zoomed-in picture of the step sizes obtained by adding 4 DAC values together.
I was going to start a new thread for DACs, but since there isn't much to complain about, I'll just post here.
Measurements were taken by adapting the P2 program to put out a 'initiate reading' pulse after each DAC step transition. The pin mode just steps from %10100_00000000 to %10111_11111111, which takes it through the 3v3 990 ohm DAC, 2v 600 ohm DAC, 3v3 123 ohm DAC, then 2v 75 ohm DAC. Measurements were in High-Z mode (not ideal), 10 PLC, board 2, room temperature ~ 20C, 80 MHz master clock.
It was only a preliminary look, but at room temperature, these are all reading a few percent (3~6%) "under".
They close the gap to ideal values when being cooled. ie the gap from ideal would widen at hotter temperatures.
I only looked at pins P0~P2 so far. I need to automate the code like was done for the DAC testing above.
What recorded the DAC voltage ? Was that a P2 ADC reading, or some external ADC ?
What was the expected (ideal) DAC step size - it looks to average slightly under 0.0415, whatever units those are ?
Given these are not calibrated, that's remarkably close. Usually you would expect maybe 20% for uncalibrated / raw values.
Recording done by the external multimeter in high-Z mode. It has a 10,000 reading buffer, in effect I let it run for 1024 samples with a DAC increment between each reading.
I don't know what to expect, but just having the current sources there seems useful. Going to look at the resistors next.
Also, I'm pretty sure I was measuring a pseudo random stream, rather than midpoint voltages, before. Which explains why it only worked on even pins.
Nice setup.
Is this the basis for the 2nd DAC plot ?
3.3/255+2/255+3.3/255+2/255 = 0.041568
- doing that may average some errors, so separate plots could be more useful, with a Vmax included to show the expected ideal step size.
With 3v3 990 ohm DAC, 2v 600 ohm DAC, 3v3 123 ohm DAC, then 2v 75 ohm DAC I'd expect the errors to vary by DAC, with perhaps the 990 ohm one best, and 2V 75 ohm worse.
The 2V will also be nominal.
Yes, Chip did a nifty single-pin triangle oscillator using a cap and the internal current sources.
There should be an inductor equivalent oscillator, and this could even work on a LC oscillator too ?
Do you mean the DAC was smart pin dithered as in "DAC 16-bit with pseudo-random dither" ?
I see this comment in the DOCs
"If OUT is high, the ADC will be enabled and RDPIN/RQPIN can be used to retrieve the 16-bit ADC accumulation from the last sample period. This can be used to measure loading on the DAC pin."
If you have an external ADC and DAC sweep all nicely working here, can you add that mentioned P2-ADC capture, so the P2-ADC errors can be plotted across the whole ADC range ?
External meter collects the precise applied voltage (via the DAC), and the ADC reports the P2 value ?
Correct, though the divisor could be somewhere between 255 and 256 due to IR drops once the DAC is running
You're right and I'll come back to this. I did measure vmax at 3.3059v at the start but of course it can wander a bit. I'm thinking it may be possible to interleave into the readings, in between each DAC step. Then it becomes a bit like the internal autocalibration, and just takes a bit more time.
Right, I'm curious how close the DACs get to the rails - that earlier test showed something like 6mv from GIO and 2mV from VIO, I think. That'll likely vary by DAC too
Yeah that was really neat. We should be able to sweep in frequency too. Pin by pin bode plots
I think it was the random noise source, only available to even pins. That would explain it
If we're going to do this properly, perhaps the following sequence should be followed
[code]
For each board 1 to 2
For each pin 0..61
For each DAC 990R to 75R
For each DAC code 0 through 255,
For each repeated measurement 1 to 3 (if required, for confidence)
"Fast" output GIO (~16 ohm resistance). Measure using both DMM and P2 ADC
Set DAC level and measure. Measure using both DMM and P2 ADC
"Fast" output VIO (~19 ohm resistance). Measure using both DMM and P2 ADC
[/quote]
The trouble is that the multimeter memory won't take enough readings. But, the above would give good coverage. I would probably want to get some more stability on temperature though, at least a fan or two
The variables not being looked at (at the moment) include VIO variation (eg running at 2v5 or 1v8), master clock frequency, and temperature.
If the memory is limited, you could do each DAC separately ?
I think those 6mV and 2mV are at the rails, it's just the internal rails, with the voltage drops getting into the device and to the IO cell.
On a DAC, is 00= 0V and 0xff=VIO (or DAC max) ?
What sets the 2.0V upper limit on the lower swing DACs ?
The 123R DAC gets within about 0.6mV of locally outputted GIO, VIO potentials
These are small compared to the nominal step size 12.94mV, but can't be completely written off
In addition, there's about 0.9mV of voltage rise between negative power input terminal and GIO. Estimating 1v8 current about 300mA flowing in that path (I see about .11A at 5v rail), thats an approx impedance of 0.003 ohms.
Some of these look dramatic, but are zoomed right in.
It took a while to get the measurement technique right. I had this odd transition going around code 92, turns out thats where the multimeter shifts range, and takes a moment to do so, throwing the integrating measurements out.
Edit: Where possible, I used blue markers for the increasing ramp (codes 0 to 255), and orange for the decreasing ramp (codes 255 downto 0)
Nice plots !
The plot
Board 2 Pin 0 DAC (123R) Voltage on upramp vs downramp, by code
might be showing us the Power supply noise. Are those Y units volts ? -> 150uV peak noise ? seems plausible.
The plot
Board 2 Pin 0 DAC (123R) Error vs line of best fit
Is that one-up, one down, and the clusters are the sub-bit groupings.
ie looks like they are largely packets of 8, so 3 LSB's are one form, then a slight change occurs on next bits
The bottom 3, and top 5 are grouped in sets of 8, then middle ones disperse some more, > 150 they are 2 sets of 4.
Are they Y units Volts ? with the nominal step size 12.94mV 0..240 are within about 1.5mV, and > 240 spreads to 2.5mV
I think that's indicating ~11.1 bits for the < 240 area, and ~10.3 bits for the complete range.
For one on every pin, that's quite impressive. Dithering seems worth it, tho 16 bits may be optimistic.
I guess the random dither will 'join the dots' into more continual curves, but the non-linearity of the 'S' curve will remain.
I wasn't remembering the bond wire impedance.
$00 = internal GIO (external GND)
$FF = internal VIO
The 2.0V modes are set by internal pull-down resistors.
Does that range-change also change load ?
IIRC the bench meters here have a hi-Z mode, but only on the lowest range, when no divider is switched in. I think they have an auto-range-off option, to avoid steps.
Yes, all the vertical scales are volts.
It was easy to run this test while things are set up, just replace voltage with current measurement and repeat the cycle.
Master clock frequency is 80 MHz, and then addition of the current meter drops the voltage at the board terminals a bit, which causes the XCL220 switching regulator to draw about 5~10% more current.