Thanks for adding those 20 MHz labels. I was reflecting on how odd this 'pull towards centroid' thing is - what other process does that with increasing perturbances (temperature) ?
Yeah, that just strange..
The variation between pins is also quite a surprise, as in the custom layout, I assume these cells are cut/paste copied, so should be very similar in all aspects.
If there any info around on how much P1 varies between pins, running ADCs ?
Remember that inside each ADC, the integrator sense amplifier is built of a string of near-minimum sized inverters. Those inverters' thresholds are going to vary in every instance. This results in gross differences between ADC's, but can be compensated for by calibration.
Remember that inside each ADC, the integrator sense amplifier is built of a string of near-minimum sized inverters. Those inverters' thresholds are going to vary in every instance. This results in gross differences between ADC's, but can be compensated for by calibration.
Of course, but these variations are rather larger than I'd expect from threshold miss-match alone.
The 'moving in different directions' aspect of this, will make compensation by calibration quite difficult.
eg the scatter plots above, show ~ +2.9 % on some pins and -2.36% on others, over MHz/Temp.
Knowing temperature alone, is not going to be much help there ? That's in the region of 5-6 bits of predictability.
Is a single compensation pulse able to overcome the comparators threshold?
Bringing this up again: if a single CompPulse does trigger the comparator, we would have one count up or down every clock cycle. If not, we would have to have a few clocks up and down, so we actually have a saw tooth. The readout would bring a varying number of clocks, depending on the phase of the sawtooth to the readout. That means, the adc should count every clock up/down when balanced
So that's about +/- 26mV threshold or 0.78% of 3v3
and some P1 general ADC comments harvested from other threads... Another note. Turning on the PLL and running with a 10MHz clock and 19Hz sample rate has 1.5-2x the noise of running without the PLL at 5MHz. This would indicate that using a fast crystal and no PLL is best for sigma delta precision.
"My goal is to get the best precision I can with a 10-30Hz sample rate. So far I can get about 13-14 stable bits. Super sampling followed by a CIC averaging filter hasn't shown a significant improvement. (though it likely rejects aliasing better)
"
Tho I did not see an error-vs-each value plot for that.
5MHz and 19Hz is roughly 18 bits of sample-time-quanta, so 13~14 bits is P1 noise.
@ErNa
Tubular and I were testing ADC and Goertzel stuff on the P2 silicon today.
Here's 8192 samples of the ADC noise for analysis if anyone is interested.
Could you please repeat the experiment reading the counter as fast as possible and store the counter values in an array? Only 8bit values are needed, anyway it will be faster to read and store 32 bit values.
pseudo code: loop: in cnt, store @x++ loop
No need to calculate the difference as this will slow down the loop. The adc input should be connected to a voltage divider with capacitor to have a low noise input voltage. Measurement should be done for different input levels.
This data should show, how the balancer works. If the balancer is not influenced by the readout (what should not be the case) the noise floor should go down when readout frequency goes down.
... But also if you want some particular tests run, just sing out
Back to Analog - I think Chip did some quick DAC tests, and any DAC level should be very low noise (Static, and low impedance operation).
A useful test would be to :
Connect a single DAC out, to 4-8 Analog IN pins, and sweep DAC & record all channels, ( No PLL, over a relatively long mains-rejecting time eg 1/60 or 1/50 s)
That should give scatter histograms for channel to channel variance, and error levels per step, when fed with exactly the same voltage.
I would avoid any DAC dither in the first tests, keep it as simple/pure as possible.
@ErNa
Tubular and I were testing ADC and Goertzel stuff on the P2 silicon today.
Here's 8192 samples of the ADC noise for analysis if anyone is interested.
Could you please repeat the experiment reading the counter as fast as possible and store the counter values in an array? Only 8bit values are needed, anyway it will be faster to read and store 32 bit values.
pseudo code: loop: in cnt, store @x++ loop
No need to calculate the difference as this will slow down the loop. The adc input should be connected to a voltage divider with capacitor to have a low noise input voltage. Measurement should be done for different input levels.
This data should show, how the balancer works. If the balancer is not influenced by the readout (what should not be the case) the noise floor should go down when readout frequency goes down.
What kind of source impedance would you like for the divider, Erna? Or should we just do as jmg has suggested with using a DAC to generate different levels?
Is a single compensation pulse able to overcome the comparators threshold?
Bringing this up again: if a single CompPulse does trigger the comparator, we would have one count up or down every clock cycle. If not, we would have to have a few clocks up and down, so we actually have a saw tooth. The readout would bring a varying number of clocks, depending on the phase of the sawtooth to the readout. That means, the adc should count every clock up/down when balanced
Chip could probably tell us the value (pF) of the integrating capacitor
Could you please repeat the experiment reading the counter as fast as possible and store the counter values in an array? Only 8bit values are needed, anyway it will be faster to read and store 32 bit values.
pseudo code: loop: in cnt, store @x++ loop
That will spawn a huge number of values, with little change in each value ?
Thanks.
Thinking some more, I've seen that some vendors suggest MCU IDLE during ADC measure, if you want the lowest possible noise (and they do that with a straight face..)
I wonder what the P2's lowest Digital noise mode is ?
A simple WAIT has to be quiet, surely ?
I guess that means coded as [ReadSn->Wait->ReadFn] then a separate serial send Fn-Sn captures analog with quietest digital during the analog reading.
What kind of source impedance would you like for the divider, Erna? Or should we just do as jmg has suggested with using a DAC to generate different levels?
Using the DAC seems ok, and a low pass filter 10K/(100nF+1nF) should do a good job, 1nF in parallel due to lower impedance.
Could you please repeat the experiment reading the counter as fast as possible and store the counter values in an array? Only 8bit values are needed, anyway it will be faster to read and store 32 bit values.
pseudo code: loop: in cnt, store @x++ loop
That will spawn a huge number of values, with little change in each value ?
Yes, that's right. But we see noise and if this noise comes from the balancing, the noise should be reduced at longer read out periods. So I expect the signal will be very noisy and then we can run some test with noise filtering and see, if we perform better than by straight integration.
What kind of source impedance would you like for the divider, Erna? Or should we just do as jmg has suggested with using a DAC to generate different levels?
Using the DAC seems ok, and a low pass filter 10K/(100nF+1nF) should do a good job, 1nF in parallel due to lower impedance.
In P2 the integrator cap is internal, but I wonder if splitting the decoupling to Vio/Gnd, as in P1, would make any difference to the analog results ? - probably not, but easy to check ?
I never checked, if splitting the cap made a difference, as I always connected one 1nF as close as possible to the pins and to ground layer. In the beginning I used 40pin Dip packages and only used the middle pins to have no long connections that influence the shape of the compensation pulses. Now, that the circuit is integrated, stray inductance and capacity should be minimal. even taking into account, that thin layers of dielectricum create high capacitance.
There's also a case for connecting a single cap to the 3v3 rail, which would be an ususual setup During calibration the 3v3 rail seems a little bit lower noise than the Gio. (I think stdev was something like 5.5 on Vio compared with 7.5 on Gio (16 bit samples)
I've hooked up temperature sensors to my P2D2 setup.
I can now log front and rear P2 chip temps with the ADC data.
Should have some more data on Monday.
Here's some data testing multiple (10) ADC inputs tied together. Building on / adapting OzPropDev's code
Pin P1 is the active DAC output (990 ohms I think), and it drives all of P2~P11. Its driving a fixed midrange level of %10000000 and this shows up as 1.66V on the multimeter. I've called this column AIO , so the sequence of measurement goes ground (GIO), analog pin input (AIO), then 3v3 (VIO).
The first capture file has no filter caps, the second has a single 100NF monoblock and 1NF polyester cap from the 'mass node' to ground. Only one ADC pin is being sampled at a time. Note this is not the same filter corner frequency Erna requested (resistance is 990 ohm dac rather than 10k series) . I guess I could add a 10kohm in series and repeat if important, but hopefully this data is enough
Frequency starts off at 80 MHz and steps in 40 MHz increments up to 320 MHz. Because of the reduced number of pins and bigger steps the self heating should be more limited. There is no cooling. The whole test takes about 90 seconds to run.
I don't have time today to graph / analyse this data, but will get to it later if others haven't
I realised it would be easy to test connecting the filter caps to different rails. He's the case where the 'mass node' is connected via 100NF and 1NF caps to the VIO (3v3) rail. I hypothesize that it may be slightly more stable than the gnd rail (the VIO readings come out more consistent than GIO during auto calibration)
And here's the 'Both' case for the 'mass node' connected via 100NF||1NF to VIO, as well as a second 100NF||1NF to GIO.
This is a similar filter arrangement to when we do sigma delta on the P1.
Since you have that circuit in place, would it make sense to also try (in addition to the noise reduction effort) some kind of multibit SW delta sigma on top of the HW one?
I mean, capture 10/12 bits with the HW ADC (say up to the current number of "good" bits plus one for quantizer dithering of sorts), invert the word and spit it back to the summing node via another DAC pin, then iterate this 64+ times to get additional precision (sorry for the pedantic explanation, I'm never sure if I'm being clear enough 🙄).
Requires two pins, but if it works could be a plan B for extended precision, maybe.
Repeated the 990 ohm DAC driving 10 ADC inputs test this morning, this time loading %00000000 (0 volts) and %11111111 (3v3) into the static DAC value, just to see what happens when compared with GIO and VIO autocalibration.
The 'noise' (VIOmax-VIOmin across 1000 samples) seemed a little lower for the AIO case than VIO case (both 3v3 inputs, but different paths). This wasn't really the same for the AIO vs GIO equivalent. I need a better calc based on drilled down raw detail to extract anything more meaningful.
For the ground measurement, AIOaverage was about 6mv higher than GIOaverage
For the 3v3 rail measurement, AIOaverage was about 2mv lower than VIOaverage
both of these are well within the 13mV DAC step size (3v3/255)
Nothing much to conclude here, just ran the test while convenient. I'll likely come back when we have the microsd running and can easy amass big data
Tubular, perhaps those millivolt differences are attributable to being driven by a 990 ohm DAC. Try the 123 ohm DAC and I think those numbers will tighten up a bit. The ADC has an input impedance of 440k ohm to ~VIO/2.
Comments
Remember that inside each ADC, the integrator sense amplifier is built of a string of near-minimum sized inverters. Those inverters' thresholds are going to vary in every instance. This results in gross differences between ADC's, but can be compensated for by calibration.
The 'moving in different directions' aspect of this, will make compensation by calibration quite difficult.
eg the scatter plots above, show ~ +2.9 % on some pins and -2.36% on others, over MHz/Temp.
Knowing temperature alone, is not going to be much help there ? That's in the region of 5-6 bits of predictability.
Bringing this up again: if a single CompPulse does trigger the comparator, we would have one count up or down every clock cycle. If not, we would have to have a few clocks up and down, so we actually have a saw tooth. The readout would bring a varying number of clocks, depending on the phase of the sawtooth to the readout. That means, the adc should count every clock up/down when balanced
I found this
"With Vdd measured at 3.297V, and nothing connected to any pin except the tx on P30
P0: 1.411 P8: 1.440 P16: 1.445 P24: 1.440
P1: 1.442 P9: 1.428 P17: 1.421 P25: 1.418
P2: 1.418 P10: 1.409 P18: 1.423 P26: 1.429
P3: 1.428 P11: 1.426 P19: 1.420 P27: 1.432
P4: 1.417 P12: 1.427 P20: 1.423 P28: 1.423
P5: 1.428 P13: 1.424 P21: 1.450 P29: 1.432
P6: 1.392 P14: 1.409 P22: 1.410 P30:
P7: 1.408 P15: 1.425 P23: 1.413 P31: 1.434"
So that's about +/- 26mV threshold or 0.78% of 3v3
and some P1 general ADC comments harvested from other threads...
Another note. Turning on the PLL and running with a 10MHz clock and 19Hz sample rate has 1.5-2x the noise of running without the PLL at 5MHz. This would indicate that using a fast crystal and no PLL is best for sigma delta precision.
"My goal is to get the best precision I can with a 10-30Hz sample rate. So far I can get about 13-14 stable bits. Super sampling followed by a CIC averaging filter hasn't shown a significant improvement. (though it likely rejects aliasing better)
"
Tho I did not see an error-vs-each value plot for that.
5MHz and 19Hz is roughly 18 bits of sample-time-quanta, so 13~14 bits is P1 noise.
pseudo code: loop: in cnt, store @x++ loop
No need to calculate the difference as this will slow down the loop. The adc input should be connected to a voltage divider with capacitor to have a low noise input voltage. Measurement should be done for different input levels.
This data should show, how the balancer works. If the balancer is not influenced by the readout (what should not be the case) the noise floor should go down when readout frequency goes down.
Back to Analog - I think Chip did some quick DAC tests, and any DAC level should be very low noise (Static, and low impedance operation).
A useful test would be to :
Connect a single DAC out, to 4-8 Analog IN pins, and sweep DAC & record all channels, ( No PLL, over a relatively long mains-rejecting time eg 1/60 or 1/50 s)
That should give scatter histograms for channel to channel variance, and error levels per step, when fed with exactly the same voltage.
I would avoid any DAC dither in the first tests, keep it as simple/pure as possible.
What kind of source impedance would you like for the divider, Erna? Or should we just do as jmg has suggested with using a DAC to generate different levels?
Chip could probably tell us the value (pF) of the integrating capacitor
By the way, analog devices have a nice little sigma delta interactive tutorial here:-
https://www.analog.com/en/design-center/interactive-design-tools/sigma-delta-adc-tutorial.html
Thanks.
Thinking some more, I've seen that some vendors suggest MCU IDLE during ADC measure, if you want the lowest possible noise (and they do that with a straight face..)
I wonder what the P2's lowest Digital noise mode is ?
A simple WAIT has to be quiet, surely ?
I guess that means coded as [ReadSn->Wait->ReadFn] then a separate serial send Fn-Sn captures analog with quietest digital during the analog reading.
In P2 the integrator cap is internal, but I wonder if splitting the decoupling to Vio/Gnd, as in P1, would make any difference to the analog results ? - probably not, but easy to check ?
There's also a case for connecting a single cap to the 3v3 rail, which would be an ususual setup During calibration the 3v3 rail seems a little bit lower noise than the Gio. (I think stdev was something like 5.5 on Vio compared with 7.5 on Gio (16 bit samples)
We can try these different things.
I can now log front and rear P2 chip temps with the ADC data.
Should have some more data on Monday.
Pin P1 is the active DAC output (990 ohms I think), and it drives all of P2~P11. Its driving a fixed midrange level of %10000000 and this shows up as 1.66V on the multimeter. I've called this column AIO , so the sequence of measurement goes ground (GIO), analog pin input (AIO), then 3v3 (VIO).
The first capture file has no filter caps, the second has a single 100NF monoblock and 1NF polyester cap from the 'mass node' to ground. Only one ADC pin is being sampled at a time. Note this is not the same filter corner frequency Erna requested (resistance is 990 ohm dac rather than 10k series) . I guess I could add a 10kohm in series and repeat if important, but hopefully this data is enough
Frequency starts off at 80 MHz and steps in 40 MHz increments up to 320 MHz. Because of the reduced number of pins and bigger steps the self heating should be more limited. There is no cooling. The whole test takes about 90 seconds to run.
I don't have time today to graph / analyse this data, but will get to it later if others haven't
This is a similar filter arrangement to when we do sigma delta on the P1.
Since you have that circuit in place, would it make sense to also try (in addition to the noise reduction effort) some kind of multibit SW delta sigma on top of the HW one?
I mean, capture 10/12 bits with the HW ADC (say up to the current number of "good" bits plus one for quantizer dithering of sorts), invert the word and spit it back to the summing node via another DAC pin, then iterate this 64+ times to get additional precision (sorry for the pedantic explanation, I'm never sure if I'm being clear enough 🙄).
Requires two pins, but if it works could be a plan B for extended precision, maybe.
At this stage I'm just trying to work out what if anything needs improvement, will get to strategies (also including filtering) later.
The 'noise' (VIOmax-VIOmin across 1000 samples) seemed a little lower for the AIO case than VIO case (both 3v3 inputs, but different paths). This wasn't really the same for the AIO vs GIO equivalent. I need a better calc based on drilled down raw detail to extract anything more meaningful.
For the ground measurement, AIOaverage was about 6mv higher than GIOaverage
For the 3v3 rail measurement, AIOaverage was about 2mv lower than VIOaverage
both of these are well within the 13mV DAC step size (3v3/255)
Nothing much to conclude here, just ran the test while convenient. I'll likely come back when we have the microsd running and can easy amass big data
I'll also try the local DAC/ADC combined mode on individual pin.
GND to 990ohms to 440kohms to 1.65v results in ~3.74uA and the 990-to-440k junction voltage would be 3.7mV.
When in combined DAC + ADC mode, is there a way to be isolated from the physical external pin? Or are they always connected to that external node?
It always connects to the physical pin.