ADC Noise - Page 3 — Parallax Forums

• Posts: 14,133
My theory about switching noise is probably wrong, because when we slow the chip down, the problem persists, exactly. It must have something to do with the design of the ADC that can stand some improvement.
• Posts: 14,033
If you do a running average of many measurements, does it eventually reach a fixed value?
Or, does it wander around on the timescale of seconds...
• Posts: 2,143
cgracey wrote: »
My theory about switching noise is probably wrong, because when we slow the chip down, the problem persists, exactly. It must have something to do with the design of the ADC that can stand some improvement.

So the noise frequency is independent of sysclock?

If sampling more than one pin, would it be better to use multiple cogs exactly in sync?
• Posts: 14,133
edited 2018-10-12 13:53
It's a wanderer. It goes round and round. I think that is the nature of true randomness, though. There is a noise floor which we just can't seem to get underneath, regardless of sample size.
• Posts: 14,133
TonyB_ wrote: »
cgracey wrote: »
My theory about switching noise is probably wrong, because when we slow the chip down, the problem persists, exactly. It must have something to do with the design of the ADC that can stand some improvement.

So the noise frequency is independent of sysclock?

If sampling more than one pin, would it be better to use multiple cogs exactly in sync?

It is independent of clock frequency. I think the phenomenon is wholly inside the converter. It is the same, regardless of power being consumed, frequency running, anything.
• Posts: 14,033
Maybe we can use for “real random” for p2
• Posts: 15,278
A little story of no help at all - Many wrapping machine moons ago I was using a high gain ADC to sample six thermocouples and they exhibited the same drifting over seconds and even minutes. Even though it was all differential wiring I still assumed it was common mode noise from the dangling thermocouples injecting into the differential circuit somehow. Each machine had varying excesses of drift - up to maybe 0.5 mV unamplified.

Besides filtering, both analogue and digital, and since there wasn't great need for precise or even accurate temperature readings, I made no further investigations into the actual cause. So am none the wiser really.

• Posts: 14,033
I still think 11 bits is actually pretty good...
Eight would probably be good enough for a lot of applications...

Would the P1 way of sigma-delta do any better? Probably not.
But, maybe a way to use DAC to improve it?
I'm sure there's something clever one could do...
• Posts: 14,033
For a better DC or low frequency voltage measurement, maybe this:
Measure 8-bits with ADC on pin 0.
Output this value on pin 1 using DAC.
Use external opamp to amplify difference between pin 0 and pin 1 and put on pin 2.
Measure difference on pin 2 and do some fancy math to get 16 bits.
Can that work?
• Posts: 1,743
cgracey wrote: »
No matter what mode I put the ADC in, for a 16-bit conversion, I get noise in the ~5 LSBs.

I output this noise onto a DAC, so I could look at it. It is not just hash, but a continuous noisy function. It wanders up and down. Not sure what causes it or if it can be remedied.

Here is a scope shot of it. I calculate that the peak-to-peak amplitude of this noise is ~1.6mV, or 3.3V / power(2, 16-5).
[/code]
could you please create a csv file of that measurment ( or a similar one) and post it?

• Posts: 14,033
Still thinking 11 bits is fine, better than others.

The ADC in the PIC16F676 (which I think I decided was being used in my servos) only has a 10 bit output, for example...
• Posts: 15,149
cgracey wrote: »
TonyB_ wrote: »
cgracey wrote: »
My theory about switching noise is probably wrong, because when we slow the chip down, the problem persists, exactly. It must have something to do with the design of the ADC that can stand some improvement.

So the noise frequency is independent of sysclock?

If sampling more than one pin, would it be better to use multiple cogs exactly in sync?

It is independent of clock frequency. I think the phenomenon is wholly inside the converter. It is the same, regardless of power being consumed, frequency running, anything.

here is one paper on Noise sources in MOSFETS & there are many..
https://www.nikhef.nl/~jds/vlsi/noise/sansen.pdf

You could also get an external DAC module, and test P2, vs the PAD test die to check they are the same & also check P1 using similar R,C elements as another litmus test.

Do you have the circuit of the ADC elements ?
• Posts: 15,149
Rayman wrote: »
For a better DC or low frequency voltage measurement, maybe this:
Measure 8-bits with ADC on pin 0.
Output this value on pin 1 using DAC.
Use external opamp to amplify difference between pin 0 and pin 1 and put on pin 2.
Measure difference on pin 2 and do some fancy math to get 16 bits.
Can that work?

Yes & no.
An offset opamp with gain certainly drops the noise floor, but the ADC & DAC limitations mean a step-follow is compromised.
Imagine you move closer to the next step, the ADC noise makes that decision uncertain, and if your DAC is not 16b perfect, that adds another error, add all that up, and you can be ‘better in some places, worse in others’.
• Posts: 14,033
edited 2018-10-12 19:19
Hey, I actually found a paper that discusses this technique (and others)

Apparently, it's called "subranging". See Fig.4 in the pdf link below.'...

https://www.mdpi.com/2079-9268/8/2/12/pdf

There's another trick called "Folding ADC" that looks interesting...
• Posts: 1,743
Just to be clear: the adc is of the same type as it is in the P1? So the compensation pulses to the integrating capacitor are counted? The feedback resistor (old) is now a current source (new) and the input resistor (old) is now what? As the sensitivity is selectable, is the input impedance switched? And the read out is done by a counter controlled (waitcnt) read of the phase counter? Would be usefull to have csv file of the scope signal.
• Posts: 312
Maybe averaging multiple 10/11bit samples should help somewhat, at least for low sampling rates?

Can't remember where I did read an explanation (I think it was a Microchip's application note) explaining that you can gain approx 1bit of dynamic range for every 4x oversampling factor applied, but I guess the pre-requisite is that the noise is really white-ish.

So it could be interesting to determine the spectral distibution of the noise.
• Posts: 14,033
edited 2018-10-12 20:54
Looks like Analog has used a pipelined version of subranging for a while:
http://www.analog.com/media/en/training-seminars/tutorials/MT-024.pdf

If one were to use about 8 (or maybe 10) P2 pins, I think you could digitize video with a bit of external hardware...

• Posts: 232
Does this affect the DAC too? Or just the ADC?

J
• Posts: 14,133
edited 2018-10-12 23:48
thej wrote: »
Does this affect the DAC too? Or just the ADC?

J

It's just the ADC. I'm kind of heartened, though, because the error seems to be independent of voltage, frequency, and digital switching noise. It makes me wonder if it is just caused by noise as current flows through the FETs in the analog circuitry. The noise seems very random and not tied to any frequency of electrical activity. So, I'm wondering, how do you minimize FET noise? Maybe upping the current within all the feedback networks? Or, does noise scale right up with current?

The DAC is working great. I did a test last night using the dithering modes and, sure enough, a single step in a 16-bit output causes a 50.3uV increase in output. At the critical steps where one set of resistors switches off and another switches on, the steps were within +-40uV of target, so it's still monotonic, at least, which is important - every increase in 16-bit output value causes an increase in output voltage.
• Posts: 14,033
I guess I'd put it in liquid nitrogen and see if the FET noise goes down...
• Posts: 15,149
edited 2018-10-13 01:18
cgracey wrote: »
It's just the ADC. I'm kind of heartened, though, because the error seems to be independent of voltage, frequency, and digital switching noise. It makes me wonder if it is just caused by noise as current flows through the FETs in the analog circuitry. The noise seems very random and not tied to any frequency of electrical activity. So, I'm wondering, how do you minimize FET noise? Maybe upping the current within all the feedback networks? Or, does noise scale right up with current?

The paper I linked above about Noise sources in MOSFETS lists many, it seems 1/f noise is known to be poor, and this noise looks like that.

Other checks would be to compare with P1, and with the PAD test chip to confirm you are in the same ballparks

cgracey wrote: »
The DAC is working great. I did a test last night using the dithering modes and, sure enough, a single step in a 16-bit output causes a 50.3uV increase in output. At the critical steps where one set of resistors switches off and another switches on, the steps were within +-40uV of target, so it's still monotonic, at least, which is important - every increase in 16-bit output value causes an increase in output voltage.

Which DAC modes did you test, and was that all steps typically within ±40µV - that's quite good. Wonder what the worst case is in ENOB ?
Looks like checking the DACs is going to need a good quality ADC

There are reasonable price high bit count ADCs like NAU7802SGI, 24b and goes to DC, 2 ch, but only 80sps.

Maybe using Audio parts is possible ? - you could generate a sine, from a table, and measure the table difference across the codes.
These use a standard i2s interface.
eg Taking AK5522VN - they do not pass DC, but have HPF of 3dB >1Hz, 0.1dB > 6.5Hz
At fs=192kHz they have upper corner of 83.7kHz

or, there are the expensive TI/AnalogDevices with faster sampling and DC capable.

addit : or, maybe a Codec is more useful, as you can loop-back to prove comparative quality - AK495x, AK4621 etc
• Posts: 14,133
Jmg, I tested the two smart pin 16-bit dither modes on the DAC.

One mode uses noise as the impetus to switch between two adjacent states on the 8-bit DAC, while the other uses PWM which cuts the transitions down to 2 per 256 clocks. The noise one can be updated at any time, while you should limit updates to the PWM one to every 256 clocks to respect the PWM frame.
• Posts: 6,548
"It makes me wonder if it is just caused by noise as current flows through the FETs in the analog circuitry. The noise seems very random and not tied to any frequency of electrical activity. So, I'm wondering, how do you minimize FET noise?" - Adequate guard rings around sensitive analog circuitry helps immensely to minimize noise. In some extreme cases you can apply active circuitry to HNWELL (High N Well ) which samples the substrate noise just below the HNWELL area so that any common mode noise cancels out.

The ADC's for the FOVEON image sensor from National Semiconductor implement active HNWELL noise cancellation to achieve extreme high resolution sample rates. ( I know because I did the layout for these ADC's ) What you are observing is probably thermal noise and more than likely feedback being injected into the substrate from the ADC circuitry itself. It wouldn't necessarily follow or synchronize with the system clock. This is actually common with Op-Amps ( or heck just a transistor amplifier used in an RF circuit ) and why you see a cap (usually a few pF) across the output pin and inverting input pin in high gain configurations. Although the cap does slow the response down slightly, at the same time it minimizes or eliminates unwanted oscillations. Other techniques where you need the speed would be to implement active noise cancellation.... hard to do with discrete components, so a capacitor is often used.
• Posts: 14,133
"It makes me wonder if it is just caused by noise as current flows through the FETs in the analog circuitry. The noise seems very random and not tied to any frequency of electrical activity. So, I'm wondering, how do you minimize FET noise?" - Adequate guard rings around sensitive analog circuitry helps immensely to minimize noise. In some extreme cases you can apply active circuitry to HNWELL (High N Well ) which samples the substrate noise just below the HNWELL area so that any common mode noise cancels out.

The ADC's for the FOVEON image sensor from National Semiconductor implement active HNWELL noise cancellation to achieve extreme high resolution sample rates. ( I know because I did the layout for these ADC's ) What you are observing is probably thermal noise and more than likely feedback being injected into the substrate from the ADC circuitry itself. It wouldn't necessarily follow or synchronize with the system clock. This is actually common with Op-Amps ( or heck just a transistor amplifier used in an RF circuit ) and why you see a cap (usually a few pF) across the output pin and inverting input pin in high gain configurations. Although the cap does slow the response down slightly, at the same time it minimizes or eliminates unwanted oscillations. Other techniques where you need the speed would be to implement active noise cancellation.... hard to do with discrete components, so a capacitor is often used.

Thanks, Beau! I think those are things I need to look into. I was really careful to cancel out charge injection into the integrator, even making a replica dummy load for the switches to connect to when not driving the integrator up or down. That part seems to work, but this noise issue is from something else. I got a can of freeze spray tonight that I will use to check low-temp noise. Kind of curious what it will do. Then, I need to do some experiments where I do three conversion quickly: GIO, pin, VIO, and then calculate a calibrated result. That might go a ways in improving one-off conversions, where more absolute accuracy is needed.
• Posts: 14,133
Tonight I got the ADC working with GIO and VIO calibration:

1) Sample GIO
2) Sample pin
3) Sample VIO
4) Final 32-bit measurement = (pin - GIO) << 32 / (VIO - GIO)

Doing calibration on each measurement is slower, but it gets rid of that low-frequency wandering noise, since the samples were all taken in close proximity. It also nulls out die-temperature effects and adds another bit of resolution!

Look at the lower byte of noise now. The scope's visible vertical range is 256 steps, so you can see this noise is confined to 1/2 a graticule, or 16 steps, which is only 4 bits. Without calibration, noise is at least twice that.

For AC signals, where you are concerned about spectral characteristics, there's no need to mess with this calibration stuff. Calibration is only needed when you want instrumentation-type readings.

Here's the code I wrote to do these calibrated measurements:
```' 16-bit analog to digital with GIO/VIO calibration

con	p =	5

dat	org

hubset	##%1_000001_0000011000_1111_10_00	'enable crystal+PLL, stay in 20MHz+ mode
waitx	##20_000_000/100			'wait ~10ms for crystal+PLL to stabilize
hubset	##%1_000001_0000011000_1111_10_11	'now switch to PLL running at 250MHz

dirh	#p^1

setse1	#%01<<6+p		'se1 triggers on ADC sample
'
'
' Sample gio, pin, vio
'
loop	callpa	adcmodg,#getsamp	'get gio sample
mov	gio,x

mov	pio,x

mov	vio,x
'
'
' Compute delta, scale sample
'
sub	vio,gio			'vio - gio

sub	pio,gio			'pio - gio

qfrac	pio,vio			'pio<<32 / vio
getqx	x
shr	x,#16			'make normalized 16-bit sample

'shr x,#8				'uncomment to see upper byte of sample

setbyte	dacmod,x,#1		'output lower byte of sample to DAC on P30
wrpin	dacmod,#30
dirh	#30

jmp	#loop			'loop
'
'
' Get sample
'
getsamp	wrpin	pa,#p			'set adc/counter mode
wypin	#0,#p			'inc on high
dirh	#p			'enable smart pin, starts acclimation
waitse1				'wait for acclimation done
akpin	#p			'ack pin
waitse1				'wait for sample done
rdpin	x,#p			'get sample
_ret_	dirl	#p			'disable smart pin
'
'
' Data
'

dacmod	long	%10100_10000000_00_00000_0	'DAC at mid-level (gets reused)

gio	res	1
pio	res	1
vio	res	1

x	res	1
```
• Posts: 15,278
edited 2018-10-13 09:35
cgracey wrote: »
... this noise is confined to 1/2 a graticule, or 16 steps, which is only 4 bits. Without calibration, noise is at least twice that.

And the slow wandering was more again, right?

• Posts: 1,743
Want to repeat this question, as understanding the adc for me is critical.
Just to be clear: the adc is of the same type as it is in the P1? So the compensation pulses to the integrating capacitor are counted? The feedback resistor (old) is now a current source (new) and the input resistor (old) is now what? As the sensitivity is selectable, is the input impedance switched? And the read out is done by a counter controlled (waitcnt) read of the phase counter?

And please, @cgracey : Would be usefull to have csv file of the scope signal.
• Posts: 14,133
evanh wrote: »
cgracey wrote: »
... this noise is confined to 1/2 a graticule, or 16 steps, which is only 4 bits. Without calibration, noise is at least twice that.

And the slow wandering was more again, right?

Calibration gets rid of the wandering problem, which was causing twice the error.
• Posts: 14,133
ErNa wrote: »
Want to repeat this question, as understanding the adc for me is critical.
Just to be clear: the adc is of the same type as it is in the P1? So the compensation pulses to the integrating capacitor are counted? The feedback resistor (old) is now a current source (new) and the input resistor (old) is now what? As the sensitivity is selectable, is the input impedance switched? And the read out is done by a counter controlled (waitcnt) read of the phase counter?

And please, @cgracey : Would be usefull to have csv file of the scope signal.

ErNa,

The input is now selectable by series resistors. The voltage coming through gets converted to current, as the resistor is held at ~VIO/2 by current source/sink. The feedback current to do this becomes the binary stream, as the up/down need is evaluated on each clock.

I don't have simple means to make a csv file, but I could write code to do that. That's a mini project, in itself. I may be able to get to it tomorrow night.