Here is a simulation of the ADC running clock-less, by bypassing the flipflop, in GIO calibration mode.
Thanks.
That's stable, because it becomes a PWM-Slice action around the bias point, but in being clockless, it can place edges anywhere.
Can you do the same plots, clocked ?
I'm interested in how the Tsu of the D-FF is margined, as the amount of overdrive here will vary as the sawtooth moves.
Here's a little piccy I just found at Analog.com when searching for controllable+current+circuit+bipolar. REF would be VIO/2 in the prop2, and the load would be the integrating capacitor:
I don't know how REF is applied though. That's not a typical op-amp. Goes looks ... okay, an instrumentation op-amp, sounds slow. Here's a functional circuit, with REF (attached to ground) on the right below VOUT.
There's been a bit of discussion about those VIOav vs GIOav 'trails' that Evanh plotted, and the general belief has been that the variation as frequency increased was probably primarily due to the chip getting hotter as the tests progressed.
Today I realized we could simply repeat the tests, so immediately after 320 MHz test was done with, drop straight back to 80Mhz and repeat with a now warmed die, and compare trails.
So for this test i went around the outer loop just over 2 times, following the sequence
My conclusion is that most of what we're seeing is thermally related. I deliberately picked a 'lower left quadrant pin', because from previous testing these tend to have a fairly straight and gentle slope (which should result in a trail that shifts mostly to the right and a little upwards), and sure enough, thats what we see.
We could make a much more rigorous version of this test. The test cycles ADC through pins 2 to 11 so there's a fair bit of time between 320MHz Pin 11 test, and subsequent Pin 11 @ 80 MHz test, due to testing pins 2~10 being tested with slowed down 80 MHz clock in between.
Far from perfect but I think it confirms what we've been thinking with regard to thermal effects.
My conclusion is most of what we're seeing is thermally related
Yes, looks to be a MHz contributor, and a temperature contributor.
The MHz effect is the 'follow the curves' and the temp effect is the 'follow the 80MHz dots'
For board2 data: Pin 11 is more bunched than some others. Pin 34 sits right next to Pin 11 on the graph but is twice as long. Pin 45 is probably the most stretched, and sits bottom left.
The top right is less pronounced, longest one there is Pin 50. Nice middle ground, short trail, on PIns from 25 to 32, favourite pick - Pin 28. Board2 outliers would be Pin 15 and Pin 40.
yeah there are better candidates, I just went with 11 because it was amongst the [pins 2..11] I had been testing with the 'mass node', so could compare data if needed.
I did tighten up the test so it only looked at pin 11, changed the interval to 20 MHz instead of 40 MHz and repeated 4 times on the back of each other. Here's the graph. As you can see the 3rd (grey) and fourth (yellow) passes start to get fairly close
Its like each pin has a 'signature' trail, that varies just a little from pass to pass, like a handwritten signature.
There is more thermal movement than I first thought, although not surprising.
Checking Pin 11 more closely on the earlier data from the full sweep of pins, it was about 50% wider than your blue line - Indicating it started colder but, given the notably flatter profile, I'm guessing it had a longer sampling time to spread things out more.
Here's a little bit more data supporting thermal noise theories. I went back to the tests we did with Dry Ice to see what else the data could tell us. At the time we were more interested in movement of GIO/VIO at different frequencies, and we only logged summary GIOmin, GIOmax, VIOmin, VIOmax at each pin, while staying fixed in frequency.
So without raw data to calculate STDEV on, a crude noise measure is simply GIOmax-GIOmin, though its obviously going to be sensitive to outliers.
The data seems to support lower noise at lower temperatures, as might be expected. For the test at 80 MHz (first attachment), the average across all pins was a 'crude noise value' averaging 66 (room temp) vs 56 (dry ice).
I've also included tests we did on board 1 and 2 at 250MHz, but these have a problem because the boards self-heat significantly. At 250 MHz, they're probably dissipating about 1.6 watts.
Because the pins are done in order, the first few pins provide the most reliable indicator - and the trend seems to support the thermal noise theory.
At some stage we'll revisit and test properly using raw data that we can calculate STDEV from, as well as limiting the self heating.
here's the graph at 80 MHz with not much self heating.
The blue curve is dry ice with an overall average (GIOmax-GIOmin) of 56
The red curve is room temp, average 66
horizontal axis is pin number, 0 to 58.
here are graphs of 2 different boards at 250MHz. There is self heating going on, which makes data at the left (completed first) more accurate than data at the right.
Also, at higher frequencies there is more proportional time spent switching, which causes more charge injection and noise. I would think that lower clock frequencies would produce more accurate readings, assuming higher swing on the integrator doesn't cause more non-linearity in the analog circuitry, which contributes to error.
Today I realized we could simply repeat the tests, so immediately after 320 MHz test was done with, drop straight back to 80Mhz and repeat with a now warmed die, and compare trails.
Can you add a 3rd test point, of Not GIO/VIO - ie the zero current drive resting point (pin not connected).
Should be nominally half way between, so maybe plot it as (GIO+VIO)/2 vs NC-Pin reading and this should show Zero drifts vs gain drifts.
In highest gain mode (lowest Rin), you should also be able to measure the mV offset between any two Analog-enabled pins, to gauge the offset voltage from pin to pin.
A high impedance meter could also measure the DC bias point of an Analog Enabled pin. (deviation from 50% ideal)
Internal heating is muddying the waters. I'd like to see all further temperature runs done at 20 MHz and using a temperature probe. Blowing hot and cold air on the bottom of the board should provide the changes needed.
Internal heating is muddying the waters. I'd like to see all further temperature runs done at 20 MHz and using a temperature probe. Blowing hot and cold air on the bottom of the board should provide the changes needed.
There's bound to be drift. That's what calibration modes are for. We need to figure out how to get better SNR.
If thermal is the biggest noise factor, and can be nulled, then smoothing will bring out more resolution.
Thermal seems to cause more drift than noise.
What are the sources of noise? What removes noise?
If the input voltage is adjusted that way, so every second feedback pulse is low, we should see no noise. If we could read out at clock frequency we should expect a zero and one count alternating. If we read out every second clock, we expect too see a one every time. Reading every third clock we expect one and three alternating. The lower the readout frequency is, the less noise we see.
So, reading at an appropriate rate to have some bits of resolution, we always average the noise of the virtual fast readout values and so we lose information about the character of this noise. Having such information about any systematical noise source would allow to taylor a filter.
That's about the reason why I asked for streaming a chunk of data from the adc at highest possible rate.
Certainly, the drift, linearity, offset and scaling is an issue, but when is comes to signal processing, we mostly are interested in changes of values and so static errors are cancelled out. It's very much like in a polling situation: you know, when the final readout is done, so you have to trigger noise in advance.
If thermal is the biggest noise factor, and can be nulled, then smoothing will bring out more resolution.
Thermal seems to cause more drift than noise.
That's about the reason why I asked for streaming a chunk of data from the adc at highest possible rate.
Chip mentioned just recently in this thread that we can record the 1-bit stream to hub using the streamer and 1-bit WFBYTE mode. That sounds great, because we can do moving average analysis which should be better than the current bucket approach.
Comments
That's stable, because it becomes a PWM-Slice action around the bias point, but in being clockless, it can place edges anywhere.
Can you do the same plots, clocked ?
I'm interested in how the Tsu of the D-FF is margined, as the amount of overdrive here will vary as the sawtooth moves.
It's a resistor divider. It's pretty much exactly VIO/2.
Here's a little piccy I just found at Analog.com when searching for controllable+current+circuit+bipolar. REF would be VIO/2 in the prop2, and the load would be the integrating capacitor:
Today I realized we could simply repeat the tests, so immediately after 320 MHz test was done with, drop straight back to 80Mhz and repeat with a now warmed die, and compare trails.
So for this test i went around the outer loop just over 2 times, following the sequence
80MHz (room temp, blue curve), 120MHz, 160, 200, 240, 280, 320, 80 (now warmed, orange curve), 120, 160, 200, 240, 280, 320, 80 (warmed, grey single point)
My conclusion is that most of what we're seeing is thermally related. I deliberately picked a 'lower left quadrant pin', because from previous testing these tend to have a fairly straight and gentle slope (which should result in a trail that shifts mostly to the right and a little upwards), and sure enough, thats what we see.
We could make a much more rigorous version of this test. The test cycles ADC through pins 2 to 11 so there's a fair bit of time between 320MHz Pin 11 test, and subsequent Pin 11 @ 80 MHz test, due to testing pins 2~10 being tested with slowed down 80 MHz clock in between.
Far from perfect but I think it confirms what we've been thinking with regard to thermal effects.
Yes, looks to be a MHz contributor, and a temperature contributor.
The MHz effect is the 'follow the curves' and the temp effect is the 'follow the 80MHz dots'
The top right is less pronounced, longest one there is Pin 50. Nice middle ground, short trail, on PIns from 25 to 32, favourite pick - Pin 28. Board2 outliers would be Pin 15 and Pin 40.
I did tighten up the test so it only looked at pin 11, changed the interval to 20 MHz instead of 40 MHz and repeated 4 times on the back of each other. Here's the graph. As you can see the 3rd (grey) and fourth (yellow) passes start to get fairly close
Its like each pin has a 'signature' trail, that varies just a little from pass to pass, like a handwritten signature.
Checking Pin 11 more closely on the earlier data from the full sweep of pins, it was about 50% wider than your blue line - Indicating it started colder but, given the notably flatter profile, I'm guessing it had a longer sampling time to spread things out more.
So without raw data to calculate STDEV on, a crude noise measure is simply GIOmax-GIOmin, though its obviously going to be sensitive to outliers.
The data seems to support lower noise at lower temperatures, as might be expected. For the test at 80 MHz (first attachment), the average across all pins was a 'crude noise value' averaging 66 (room temp) vs 56 (dry ice).
I've also included tests we did on board 1 and 2 at 250MHz, but these have a problem because the boards self-heat significantly. At 250 MHz, they're probably dissipating about 1.6 watts.
Because the pins are done in order, the first few pins provide the most reliable indicator - and the trend seems to support the thermal noise theory.
At some stage we'll revisit and test properly using raw data that we can calculate STDEV from, as well as limiting the self heating.
The blue curve is dry ice with an overall average (GIOmax-GIOmin) of 56
The red curve is room temp, average 66
horizontal axis is pin number, 0 to 58.
Can you add a 3rd test point, of Not GIO/VIO - ie the zero current drive resting point (pin not connected).
Should be nominally half way between, so maybe plot it as (GIO+VIO)/2 vs NC-Pin reading and this should show Zero drifts vs gain drifts.
In highest gain mode (lowest Rin), you should also be able to measure the mV offset between any two Analog-enabled pins, to gauge the offset voltage from pin to pin.
A high impedance meter could also measure the DC bias point of an Analog Enabled pin. (deviation from 50% ideal)
There's bound to be drift. That's what calibration modes are for. We need to figure out how to get better SNR.
Thermal seems to cause more drift than noise.
It's being finalized as we speak. The eval board, that is.
If the input voltage is adjusted that way, so every second feedback pulse is low, we should see no noise. If we could read out at clock frequency we should expect a zero and one count alternating. If we read out every second clock, we expect too see a one every time. Reading every third clock we expect one and three alternating. The lower the readout frequency is, the less noise we see.
So, reading at an appropriate rate to have some bits of resolution, we always average the noise of the virtual fast readout values and so we lose information about the character of this noise. Having such information about any systematical noise source would allow to taylor a filter.
That's about the reason why I asked for streaming a chunk of data from the adc at highest possible rate.
Certainly, the drift, linearity, offset and scaling is an issue, but when is comes to signal processing, we mostly are interested in changes of values and so static errors are cancelled out. It's very much like in a polling situation: you know, when the final readout is done, so you have to trigger noise in advance.
Chip mentioned just recently in this thread that we can record the 1-bit stream to hub using the streamer and 1-bit WFBYTE mode. That sounds great, because we can do moving average analysis which should be better than the current bucket approach.
However, the thermal noise is looking highly dynamic in nature. Any attempt to remove it by filtering I suspect will be doomed.
EDIT2: Well, that is for low frequencies at least. If only frequencies above about 100 Hz are needed then thermal behaviour won't interfere.
EDIT3: It might be interesting to feed the signal into an audio amplifier to listen for the highest component.