I have my name on PCB - Right up corner - that is good for me.
As I said to Ken - How Parallax distribute / market this board are Parallax that decide -- I'm happy for that to have one + some parts on my hands (Have talk with Ken on e-mail on that) and that You made Config file to it that use all resources
(but some question -- why You run on DE0-Nano only 60MHz -- It has Alteras Fastest FPGA ( C5 ) that probably can run 100MHz)
In some days I will post part list to most important parts -- All parts I used are Hand-solderable -- DAC resistors are 0805-footprint, Phono Jack are Yours part number.
all other parts are same Bill Henning use on his products.
I made this board that it can be used both as Propeller 2 emulator and as experimenters board to DE0-NANO board --
As Martin Hodgeon another thread said "Get a DE0 and explore the universe of FPGA's t'boot! It's a magical land! "
For me this PCB are simplest possible for DE0-Nano -- My own Experimenters board to DE0-Nano that I work on I can say are Advanced (Picture attached)
It have Nano + Propeller I + 7'' -TFT-LCD on other side
Thanks Chip. Wow 0.4mm is going to take some steady hands soldering! (think I said this before).
So far I've reflow soldered about 8 boards with a .4mm chip (28pin+EP), and have had 100% success. The main issues that I've come across so far is 1) high current traces (1 amp) have to narrow down to get close enough to the chip, and 2) the 3mil mylar stencils (from Pololu) don't work very well with the fine pitch: the solder doesn't go through that well, and it has to be manually applied.
SETINDA is used with two operands according to the Propeller 2 Detailed Preliminary Feature List v2.0:
Setup indirection register address A bottom range and top range where D is the top of the range and S is the bottom range. The indirection register will allow access to cog registers in this range.
However, when it has been used, as in David Betz's serial routines, it only has one operand:
SETINDA is used with two operands according to the Propeller 2 Detailed Preliminary Feature List v2.0:
Setup indirection register address A bottom range and top range where D is the top of the range and S is the bottom range. The indirection register will allow access to cog registers in this range.
However, when it has been used, as in David Betz's serial routines, it only has one operand:
setinda reserves
Has it changed?
Just to be clear, I didn't write the serial routines. They are taken from Chip's ROM monitor.
There are 6 instructions for the index registers now: SETINDA, SETINDB, SETINDS, FIXINDA, FIXINDB, and FIXINDS. So things are different from when that doc was written. I'm not sure about what they all do sorry. I just know the names of the instructions right now.
the 3mm mylar stencils (from Pololu) don't work very well with the fine pitch: the solder doesn't go through that well, and it has to be manually applied.
Have you tried laying out the pastemask for each row of leads as one big rectangle, instead of individual pads? I would expect surface tension to be your friend here. (You'd have to do the same with the soldermask, but you probably already do that, since board fabs don't like thin webs in the soldermask.) In order to keep the total amount of solder to the correct value, the pastemask rectangle can be made thinner than the pad height.
No, I haven't tried a long rectangle: I've only made one so far. Another issue that I see with that approach would be the exposed pad in the center. I'm not sure if having long rectangle cutouts for the pins along with a big cutout (or even several smaller cutouts) for the EP will make the mask too weak and flexible.
When I'm done with my current mask, I'll try using an exacto knife to cutout the rectangles and see what happens.
No, I haven't tried a long rectangle: I've only made one so far. Another issue that I see with that approach would be the exposed pad in the center. I'm not sure if having long rectangle cutouts for the pins along with a big cutout (or even several smaller cutouts) for the EP will make the mask too weak and flexible.
When I'm done with my current mask, I'll try using an exacto knife to cutout the rectangles and see what happens.
I think Sapieha misunderstood what I meant by a "big" rectangle. Obviously, you don't want solder under the chip itself. But a stripe of solder paste through each row of pads should work just fine. When I paste pads with a syringe, I will lay one thin bead through a row of closely-spaced pads. Assuming I don't deposit too much solder, the surface tension will suck it into the pad area as it melts in the toaster oven. If I do deposit too much solder, the resulting bridges are easily cleaned up with solder wick. But this should not be a problem with a correctly-sized mask aperture.
I think Sapieha misunderstood what I meant by a "big" rectangle. Obviously, you don't want solder under the chip itself. But a stripe of solder paste through each row of pads should work just fine. When I paste pads with a syringe, I will lay one thin bead through a row of closely-spaced pads. Assuming I don't deposit too much solder, the surface tension will suck it into the pad area as it melts in the toaster oven. If I do deposit too much solder, the resulting bridges are easily cleaned up with solder wick. But this should not be a problem with a correctly-sized mask aperture.
-Phil
That's the usual technique but those bridges can remain because solder may not reflow as well on power pads and other pads that have a larger thermal mass. If this technique is used then the trick is to design the pcb in the first place with some (or more) decoupling of the thermal mass from each pad and also to make sure that the oven reaches a high enough temperature for long enough to allow these pads to reflow. The other little trick is to give them a helping hand by dispensing flux alongside the solder as this aids in the reflow. In fact I have pcbs where the SD socket is the only component on the underside of the pcb and instead of another round in the oven I have found it better to apply flux to the pads and then hand solder the socket on. Anyway, it works for me.
I understood You ---- But if You look on link SRLM have in this post -- He talk on centre-pad of that IC
That need solder but not on entire pad. but that that I described.
I think Sapieha misunderstood what I meant by a "big" rectangle. Obviously, you don't want solder under the chip itself. But a stripe of solder paste through each row of pads should work just fine. When I paste pads with a syringe, I will lay one thin bead through a row of closely-spaced pads. Assuming I don't deposit too much solder, the surface tension will suck it into the pad area as it melts in the toaster oven. If I do deposit too much solder, the resulting bridges are easily cleaned up with solder wick. But this should not be a problem with a correctly-sized mask aperture.
I posted Design file's to Ken -- As I said DESIGN is Yours I only made some improvement and Layout -- and it is no way to break my integrity to give that to any other people.
Do RDBYTE, RDWORD, RDLONG implcitly perform a RDQUAD? If not, does that mean that the only way to ensure that the QUAD registers are fresh is to perform a RDQUAD (or the RDxxxxC calls that are outside the current QUAD read index)?
From Chip's docs on the RD/WRXXXXX instructions (first line):
All instructions use D as the data conduit, except WRQUAD/RDQUAD/RDQUADC, which uses the four QUAD registers.
My understanding of the docs:
The RDXXXXC instructions cause a RDQUAD to occur when needed, the RDBYTE/RDWORD/RDLONG instruction do not. The other way to write to the QUAD registers is to map them with SETQUAD and then write to the mapped locations.
Comments
I have my name on PCB - Right up corner - that is good for me.
As I said to Ken - How Parallax distribute / market this board are Parallax that decide -- I'm happy for that to have one + some parts on my hands (Have talk with Ken on e-mail on that) and that You made Config file to it that use all resources
(but some question -- why You run on DE0-Nano only 60MHz -- It has Alteras Fastest FPGA ( C5 ) that probably can run 100MHz)
In some days I will post part list to most important parts -- All parts I used are Hand-solderable -- DAC resistors are 0805-footprint, Phono Jack are Yours part number.
all other parts are same Bill Henning use on his products.
I made this board that it can be used both as Propeller 2 emulator and as experimenters board to DE0-NANO board --
As Martin Hodge on another thread said "Get a DE0 and explore the universe of FPGA's t'boot! It's a magical land! "
For me this PCB are simplest possible for DE0-Nano -- My own Experimenters board to DE0-Nano that I work on I can say are Advanced (Picture attached)
It have Nano + Propeller I + 7'' -TFT-LCD on other side
What is the P2 pin pitch please?
Is there a center ground pad? If so, must it be grounded?
The pin pitch is 0.4mm. There is no center pad.
No thanks Peter - it is easy enough to do - think I am going to extend a littler further than I normally do for this pitch.
So far I've reflow soldered about 8 boards with a .4mm chip (28pin+EP), and have had 100% success. The main issues that I've come across so far is 1) high current traces (1 amp) have to narrow down to get close enough to the chip, and 2) the 3mil mylar stencils (from Pololu) don't work very well with the fine pitch: the solder doesn't go through that well, and it has to be manually applied.
edit: changed 3mm to 3mil
Thanks
I'd just like to have some idea as part of deciding if going the FPGA route makes sense to get up to speed.
I'd hate to drop $600 dollars and then have the actual chips become available just a month or two later.
C.W.
SETINDA is used with two operands according to the Propeller 2 Detailed Preliminary Feature List v2.0:
Setup indirection register address A bottom range and top range where D is the top of the range and S is the bottom range. The indirection register will allow access to cog registers in this range.
However, when it has been used, as in David Betz's serial routines, it only has one operand:
setinda reserves
Has it changed?
-Phil
No, I haven't tried a long rectangle: I've only made one so far. Another issue that I see with that approach would be the exposed pad in the center. I'm not sure if having long rectangle cutouts for the pins along with a big cutout (or even several smaller cutouts) for the EP will make the mask too weak and flexible.
When I'm done with my current mask, I'll try using an exacto knife to cutout the rectangles and see what happens.
For reference, here is the 28+EP footprint: http://pdfserv.maximintegrated.com/package_dwgs/21-0139.PDF
Dont made one BIG rectangle --> that will give you problems.
Usually for that pads -- Uses 4 smaller rectangles in solder mask
Else IC will flow with re-flow
-Phil
I understood You ---- But if You look on link SRLM have in this post -- He talk on centre-pad of that IC
That need solder but not on entire pad. but that that I described.
http://forums.parallax.com/showthread.php?144199-Propeller-II-Emulation-of-the-P2-on-DE0-NANO-amp-DE2-115-FPGA-boards&p=1147090&viewfull=1#post1147090
I originally mentioned the problem there, but didn't get a response, so posted it here.
In attachment's I post 2 3D pictures that will help with mounting Propeller II Emulator PCB
And PDF with Schematics.
Will post Bill Of Materials as fast I'm clear with it ----> In same post
Link to clear PCB http://forums.parallax.com/showthread.php/145063-Sapeiha-s-Propeller-2-Base-Boards-DEO-Nano-Single-Cog-Emulator
Looks good. What layout program did you use to make that in?
I use Proteus - ISIS-sch, ARES-layout
I posted Design file's to Ken -- As I said DESIGN is Yours I only made some improvement and Layout -- and it is no way to break my integrity to give that to any other people.
Thanks for acceptance of my work.
Look on answer to Chip.
It is very simple to learn/use --- As You entirely work in wysi-wyg mode
This post is now updated with Bill of Material's PDF.
http://forums.parallax.com/showthread.php?125543-Propeller-II-update-BLOG&p=1147326&viewfull=1#post1147326
Chip, the referenced post is a suggestion I made for the HMAC/SHA-256 engine. I'm just going to leave the original post there to avoid duplication.
All instructions use D as the data conduit, except WRQUAD/RDQUAD/RDQUADC, which uses the four QUAD registers.
My understanding of the docs:
The RDXXXXC instructions cause a RDQUAD to occur when needed, the RDBYTE/RDWORD/RDLONG instruction do not. The other way to write to the QUAD registers is to map them with SETQUAD and then write to the mapped locations.
So if one cog writes to hub memory that matches the cached QUADs of another cog, does a RDxxxxC automatically detect this and reload the cache?