That FPGA could only support a 32KB main memory. It wouldn't do 64KB, anyway. Someone said it could do 48KB, but that's not a power of 2 and I'm too tired to think, anymore. I've been up all night and now I'm falling asleep in my chair and waking up with a sore neck, dry mouth, and drool.
Really nice work Chip - now go get some well deserved sleep...
But Chip...after you have had a well deserved rest...The DE0 Nano board has a 32MB SDRAM on it. Is it not possible to hook that up as HUB RAM?
Or is it so that this Prop implementation does not allow for such a wide address bus anway?
But Chip...after you have had a well deserved rest...The DE0 Nano board has a 32MB SDRAM on it. Is it not possible to hook that up as HUB RAM?
Or is it so that this Prop implementation does not allow for such a wide address bus anway?
Chip hopefully getting some well-deserved sleep, so I will jump in...
Assuming that the DE0-nano configuration is a cycle accurate emulation (but running at 60Mhz) it is unlikely that the DRAM could emulate hub memory without drastically slowing down the emulation.
The 16Mbit x 16 wide SDRAM would require 8 cycles to clock in (or out) the 128 bit hub width, and would also need RAS and CAS cycles, and while the emulation would have 8 prop cycles available, it would not be trivial to get all the SDRAM access accomplished in that time (hmm... maybe if the SDRAM was clocked at 120Mhz...)
What I would like to see is Chip "enabling" (once he had a lot of rest) the SDRAM on the nano as if it was hooked up to prop2 pins that cannot be brought outside.. after all, the SDRAM is connected to the FPGA pins, so it should be possible to map them in the same way they would be mapped in a real prop - thus allowing the SDRAM transfer instruction to work
But Chip...after you have had a well deserved rest...The DE0 Nano board has a 32MB SDRAM on it. Is it not possible to hook that up as HUB RAM?
Or is it so that this Prop implementation does not allow for such a wide address bus anway?
I intend to get the SDRAM pins mapped to the Prop2 pins, but that memory is not usable as hub space because it cannot be accessed randomly on a per-clock basis. It's like a freight train that takes umpteen clocks to get turned around. It can be accessed by a cog, though, that serves other cogs.
Chip posted the source for the Propeller II monitor somewhere in this thread but I can't find it. Can someone point me to the right post? That is the largest sample of Propeller II code that I know about and I'd like to use it to get an idea of how to program my new DE0-Nano Propeller II emulator.
Chip posted the source for the Propeller II monitor somewhere in this thread but I can't find it. Can someone point me to the right post? That is the largest sample of Propeller II code that I know about and I'd like to use it to get an idea of how to program my new DE0-Nano Propeller II emulator.
Dave, Sapieha, I managed to program my DE0 board, and remapped the Propplug to COM2 (checked with plain propeller) But I get no activity with a terminal program (9600 Baud) or Pnut.exe. Any suggestion what I could have overlooked?
Does this Prop II FPGA Emulation now warrant its very own forum section ?
It's definitely pulsing! Now I have to spend some time reading over Chip's ROM code to learn enough about the instruction set to write a simple program. I guess instruction set documentation will be coming soon which will make this much easier. I'm particularly interested in experimenting with the CLUT instructions.
My PII emulator is working both with a terminal program and using Pnut.exe. The Quartus 12.1 standalone programmer did the job o.k. That makes 3 succesfull implementations. Great and incredibly fast job, Chip, its only a few days ago that th DE0-nano came into the picture.
Ken: Do you think this is newsworthy? Perhaps Parallax Semi could generate some excellent free press - no other vendor offers this.
EE JOURNAL
HACKADAY
@Clusso - Releasing info about a new chip without everything done is not a good idea. There's an amazing amount of Prop Chip bashing people out there. Do not give them something to taste until the meal is complete.
If you want to inspect hub memory after your program has run, just put the following code at the end of your program:
coginit monitor_pgm,monitor_ptr 'relaunch cog0 with monitor
monitor_pgm long $70C 'monitor program address
monitor_ptr long 90<<9 + 91 'monitor parameter (conveys tx/rx pins)
This will launch the ROM Monitor and let you view what your program did to hub memory. The monitor only affects the hub memory when you give it a command to do so. So, when the monitor starts up, hub memory is just as your program left it, ready to be inspected.
Wow! It looks like you are anticipating using some taller female headers? You'll need clearance over your parts that are under the DE0-Nano board, or maybe you'll just remove the acrylic cover.
Well I am a bit disappointed as I got myself a DE2-115 but now the focus has shifted to the DE0 and I still don't have anything running, or have I missed something in the thread?
Well I am a bit disappointed as I got myself a DE2-115 but now the focus has shifted to the DE0 and I still don't have anything running, or have I missed something in the thread?
I think the DE2-115 board needs a PCB that Parallax is in the process of making.
Well I am a bit disappointed as I got myself a DE2-115 but now the focus has shifted to the DE0 and I still don't have anything running, or have I missed something in the thread?
The DE2-115 board needs an HSMC adapter board to get the signals out of it. The little DE0-Nano, just uses .100" headers, so it was easy to connect to.
Wait... there is a 40-pin header on the DE2-115 that we could plug a Prop Plug into. Do you have a Prop Plug? Let me see if I can make a special configuration for you.
Ken: Do you think this is newsworthy? Perhaps Parallax Semi could generate some excellent free press - no other vendor offers this.
EE JOURNAL
HACKADAY
ETC.
Yes, I do. I'm watching it closely for a bit and seeing what Chip decides board-wise. When we know where he's headed, then I'll round up the troops for some PR action and we'll start a thread for Propeller 2 core programming in board "X". When Chip was here at my place last week I extracted enough information from him to get behind this movement.
Comments
Really nice work Chip - now go get some well deserved sleep...
Yes!!!! I am able to run the monitor. I guess that means that my P2 is up and running. Thanks Chip!!!!!!!
NOT Yet.
Made some test board to show what happens on P0-P31.
BUT already programmed DE0-NANO
Thanks for trying that out. NOW I can go to bed.
BTW, to turn on the LEDs from the monitor, just start cogs (that don't exist):
>2+0
>3+0
>4+0
>7+0
>m
1 0 0 1 1 1 0 M
>2-
>3-
>4-
>7-
Thanks again and get some rest!
Chip
But Chip...after you have had a well deserved rest...The DE0 Nano board has a 32MB SDRAM on it. Is it not possible to hook that up as HUB RAM?
Or is it so that this Prop implementation does not allow for such a wide address bus anway?
Chip hopefully getting some well-deserved sleep, so I will jump in...
Assuming that the DE0-nano configuration is a cycle accurate emulation (but running at 60Mhz) it is unlikely that the DRAM could emulate hub memory without drastically slowing down the emulation.
The 16Mbit x 16 wide SDRAM would require 8 cycles to clock in (or out) the 128 bit hub width, and would also need RAS and CAS cycles, and while the emulation would have 8 prop cycles available, it would not be trivial to get all the SDRAM access accomplished in that time (hmm... maybe if the SDRAM was clocked at 120Mhz...)
What I would like to see is Chip "enabling" (once he had a lot of rest) the SDRAM on the nano as if it was hooked up to prop2 pins that cannot be brought outside.. after all, the SDRAM is connected to the FPGA pins, so it should be possible to map them in the same way they would be mapped in a real prop - thus allowing the SDRAM transfer instruction to work
I intend to get the SDRAM pins mapped to the Prop2 pins, but that memory is not usable as hub space because it cannot be accessed randomly on a per-clock basis. It's like a freight train that takes umpteen clocks to get turned around. It can be accessed by a cog, though, that serves other cogs.
Thanks,
David
OK, gotcha. But brilliant, so we can get some big XMM programs running somehow.
Post #1506
If You change You mind.
So tomorow You will have Gerbers to that PCB
Nico
Is this the milestone of a first off-site pulse ?
Does this Prop II FPGA Emulation now warrant its very own forum section ?
Regards
Nico Hatatink
btw beware there are two different deo boards - but only 1 DE0-nano.
definately time flor a new thread for deo-nano.
EE JOURNAL
HACKADAY
ETC.
Very cool,
@Clusso - Releasing info about a new chip without everything done is not a good idea. There's an amazing amount of Prop Chip bashing people out there. Do not give them something to taste until the meal is complete.
Thanks,
This will launch the ROM Monitor and let you view what your program did to hub memory. The monitor only affects the hub memory when you give it a command to do so. So, when the monitor starts up, hub memory is just as your program left it, ready to be inspected.
Wow! It looks like you are anticipating using some taller female headers? You'll need clearance over your parts that are under the DE0-Nano board, or maybe you'll just remove the acrylic cover.
The DE2-115 board needs an HSMC adapter board to get the signals out of it. The little DE0-Nano, just uses .100" headers, so it was easy to connect to.
Wait... there is a 40-pin header on the DE2-115 that we could plug a Prop Plug into. Do you have a Prop Plug? Let me see if I can make a special configuration for you.
Yes, I do. I'm watching it closely for a bit and seeing what Chip decides board-wise. When we know where he's headed, then I'll round up the troops for some PR action and we'll start a thread for Propeller 2 core programming in board "X". When Chip was here at my place last week I extracted enough information from him to get behind this movement.