Honestly I'd be happy with a 64 I/O P1B that can use the MUL and MULS instructions.
Just a bit more performance like that would be a sweet spot between the P1 and P2.
Although I've been ambivalent about the P2 for a long time, with the end in sight I'm starting to think about it again.
It'll be so cool to have those DACs.
I'm curious about the P1 applications that currently max out the pin usage. If a new version of P1 implemented some of the I/O capabilities from P2 (ADC, DAC, etc.), how many pins would that free up?
Incidentally, on the scaling it in VHDL thing at the last UPEW Chip teased us with the possibility of rescaling P2 to 45nm and creating chips that can run at 1 GHz. Of course they'd also require 100 watt power supplies because of the leakage...
Those chips that take 100 watts are usually on the order of 500 square mm. When we did the 40nm synthesis test with the P2 Verilog source, the silicon area was under 1 square mm. Add another 2 for SRAM and you've got 3. 100 watts * (3mm/500mm) = 600mW, likely.
Those chips that take 100 watts are usually on the order of 500 square mm. When we did the 40nm synthesis test with the P2 Verilog source, the silicon area was under 1 square mm. Add another 2 for SRAM and you've got 3. 100 watts * (3mm/500mm) = 600mW, likely.
So, just for fun, supposing that an active human brain requires about 80W (see http://wiki.answers.com/Q/How_many_watts_of_energy_does_your_brain_generate_while_awake), then this would be the equivalent of about 133 P2s. Figuring that the scaling isn't quite linear, lets go with just 100 P2s (for a total of 300 square mm, or 3 square cm). If you kept the peripherals the same, but just increased the cog count (maybe 100 sets of 8), just think of the power we could have in our hands!!! With clever use of the multi-tasking capability, you could emulate upwards of 3000+ neurons!
Hmm... okay.. So if you could just reduce power consumption by about 3x10^7...
Out of curiosity, what is the estimated power requirements (excluding I/O) of the P2 as it stands right now?
I'm curious about the P1 applications that currently max out the pin usage. If a new version of P1 implemented some of the I/O capabilities from P2 (ADC, DAC, etc.), how many pins would that free up?
I've used all the IOs in our project, and the addition of ADCs or DACs to a P1A would not help at all. I use an ADC in my project, but I get 8 input channels using only 3 IOs, so if I migrated that on to the P1A, I couldn't. But there are features that I would love to add to this project if I had more IOs, but we can't justify the price of adding a second Propeller. So if we got a P1B (with or with out ADCs) we could add all that stuff. If the P1B got ADCs/DACs as well, we could remove some of the external components and justify an increase in the price of the P1B over the P1A. We definitely would put a P1 with 64 IOs to great use. We want to use the P2, but we are using the P1 in a battery operated application, so the increase in power consumption my preclude its use in this project. But there are other projects on the horizon where the increased speed and functionality will be a necessity.
Out of curiosity, what is the estimated power requirements (excluding I/O) of the P2 as it stands right now?
I think it will be about 1.5 watts with all cogs going. When we laid out the power grid, we modeled power consumption very aggressively, so that at 3 watts consumption, the grid only sags about 50mV, worst-case.
One of my plans for P2 will use as many ADC/DACs as possible and very likely all COGs and on-board memory. I'll avoid using external memory if possible for that one since most of the product will have to do with IO features rather than business logic. We'll see.
OK !!
Back to the original question.....
When is the latest expectation of a Prop II release? Like for a purchase thereof?
My credit card is waiting.....
OK !!
Back to the original question.....
When is the latest expectation of a Prop II release? Like for a purchase thereof?
My credit card is waiting.....
Well, it turns out there wasn't a Feb 20 shuttle tapeout date for the TSMC C018LP process, after all. It's March 20, so we've got all the data out to the people handling the shuttle, but we are 4 weeks from fabrication beginning. We should have parts back late April. Hopefully, it works, so we can show it at the May 4 Propeller Expo.
Well, it turns out there wasn't a Feb 20 shuttle tapeout date for the TSMC C018LP process, after all. It's March 20, so we've got all the data out to the people handling the shuttle, but we are 4 weeks from fabrication beginning. We should have parts back late April. Hopefully, it works, so we can show it at the May 4 Propeller Expo.
That's too bad. At least you're ready for it when it comes though. In the meantime, we can have fun with our new FPGA add-on boards! :-)
That's too bad. At least you're ready for it when it comes though. In the meantime, we can have fun with our new FPGA add-on boards! :-)
That's right. Video work can be done, as well as CTR stuff. I'll probably make some FPGA configuration file that does delta-sigma over what are otherwise I/O pins. That way, the Goertzel transform can be explored, too. And then there's the texture mapping, too.
Just drop her off at Reno on the way with a boat load of entertainment cash.
Thanks for the suggestion but unfortunately neither of us are gamblers. On the other hand, she has expressed some interest in putting together a proposal for the MicroMedic contest so maybe she'll develop an interest in microcontrollers and actually want to attend OPC. :-)
I think it will be about 1.5 watts with all cogs going. When we laid out the power grid, we modeled power consumption very aggressively, so that at 3 watts consumption, the grid only sags about 50mV, worst-case.
Is that really what your simulations are saying about power consumption? Or is it just some worst case scenario?
800 mA is an awful lot of power for a micro, that is like 40x of most of them out there, and about 4x the worst I've seen on some really big 200 MHz multi-core ARMs with all their peripherals going.
Each cog takes roughly 1/8th of that with the hub logic taking a little bit more. That's roughly 200mW per cog when going full bore. Remember that the power consumption drops markedly when the cog is waiting for a future time or I/O pin state. Most cogs that provide I/O functions will spend most of their time waiting. Only the main cog (running the main program) and cogs doing high resolution video output are likely to be drawing this maximum current.
I was not sure how many gates would be toggling, typically, so we used a high number for the power estimation and a higher number for the power grid requirement. We tried to be conservative, but we don't know what the consumption will be, unfortunately.
... Only the main cog (running the main program) and cogs doing high resolution video output are likely to be drawing this maximum current.
As well as the usual mA/MHz slopes, there will be some base-currents around enabling things like the DACs.
An interesting number, would be Icc with all pin-dacs enabled ?
Too bad the OPC is all the way on the other side of the US... Now... if it were closer I'd prolly be able to convince the better half that this is something more then just a fun and expensive trip.
Comments
Just a bit more performance like that would be a sweet spot between the P1 and P2.
Although I've been ambivalent about the P2 for a long time, with the end in sight I'm starting to think about it again.
It'll be so cool to have those DACs.
Those chips that take 100 watts are usually on the order of 500 square mm. When we did the 40nm synthesis test with the P2 Verilog source, the silicon area was under 1 square mm. Add another 2 for SRAM and you've got 3. 100 watts * (3mm/500mm) = 600mW, likely.
So, just for fun, supposing that an active human brain requires about 80W (see http://wiki.answers.com/Q/How_many_watts_of_energy_does_your_brain_generate_while_awake), then this would be the equivalent of about 133 P2s. Figuring that the scaling isn't quite linear, lets go with just 100 P2s (for a total of 300 square mm, or 3 square cm). If you kept the peripherals the same, but just increased the cog count (maybe 100 sets of 8), just think of the power we could have in our hands!!! With clever use of the multi-tasking capability, you could emulate upwards of 3000+ neurons!
Hmm... okay.. So if you could just reduce power consumption by about 3x10^7...
Out of curiosity, what is the estimated power requirements (excluding I/O) of the P2 as it stands right now?
I've used all the IOs in our project, and the addition of ADCs or DACs to a P1A would not help at all. I use an ADC in my project, but I get 8 input channels using only 3 IOs, so if I migrated that on to the P1A, I couldn't. But there are features that I would love to add to this project if I had more IOs, but we can't justify the price of adding a second Propeller. So if we got a P1B (with or with out ADCs) we could add all that stuff. If the P1B got ADCs/DACs as well, we could remove some of the external components and justify an increase in the price of the P1B over the P1A. We definitely would put a P1 with 64 IOs to great use. We want to use the P2, but we are using the P1 in a battery operated application, so the increase in power consumption my preclude its use in this project. But there are other projects on the horizon where the increased speed and functionality will be a necessity.
I think it will be about 1.5 watts with all cogs going. When we laid out the power grid, we modeled power consumption very aggressively, so that at 3 watts consumption, the grid only sags about 50mV, worst-case.
Back to the original question.....
When is the latest expectation of a Prop II release? Like for a purchase thereof?
My credit card is waiting.....
Well, it turns out there wasn't a Feb 20 shuttle tapeout date for the TSMC C018LP process, after all. It's March 20, so we've got all the data out to the people handling the shuttle, but we are 4 weeks from fabrication beginning. We should have parts back late April. Hopefully, it works, so we can show it at the May 4 Propeller Expo.
That's too bad. At least you're ready for it when it comes though. In the meantime, we can have fun with our new FPGA add-on boards! :-)
That's right. Video work can be done, as well as CTR stuff. I'll probably make some FPGA configuration file that does delta-sigma over what are otherwise I/O pins. That way, the Goertzel transform can be explored, too. And then there's the texture mapping, too.
Just drop her off at Reno on the way with a boat load of entertainment cash.
Happy futuristic anniversary :-) , mine is May 14th.
Hope to see you there!!!
Huh. I wonder if I could convince my wife that this many years of marriage is the "microcontroller anniversary".
Is that really what your simulations are saying about power consumption? Or is it just some worst case scenario?
800 mA is an awful lot of power for a micro, that is like 40x of most of them out there, and about 4x the worst I've seen on some really big 200 MHz multi-core ARMs with all their peripherals going.
As well as the usual mA/MHz slopes, there will be some base-currents around enabling things like the DACs.
An interesting number, would be Icc with all pin-dacs enabled ?
"Did the Shuttle run complete?" - The shuttle run went out on March 20th, and is in production right now.
Right now it's "hurry up and wait" until we have the chips back to physically test.