Thanks.
I will send that info to You -- But You can even give them my e-mail if them have additional questions.
But I don't have Yours e-mail address.
My are -- christofferj2@gmail.com.
send me Yours to my e-mail so I will send all files to You as fats Chip approve SHC's
Have some time to be clear with them
Ps. all You send to me with PCB's --- Send as private post office BOX else it will be much charge to me WAT and that other payments.
Hey Sapieha, that'd be fine. I can order them whenever you send me the files. You can put them on forums, of course, but be sure to send me the zip by e-mail below. Be sure to specify all colors and anything they need to know because I won't be in the right position to answer to many questions from the PCB supplier (monkey in the control room).
And when I send these to you I can include anything else you may appreciate. Thanks for being part of the Propeller 2 early adopter team.
Thanks.
I will send that info to You -- But You can even give them my e-mail if them have additional questions.
But I don't have Yours e-mail address.
My are -- christofferj2@gmail.com.
send me Yours to my e-mail so I will send all files to You as fats Chip approve SHC's
Have some time to be clear with them
Ps. all You send to me with PCB's --- Send as private post office BOX else it will be much charge to me WAT and that other payments.
I'm kgracey@parallaxsemiconductor.com. If you (or anybody else) has a recommended PCB fabricator in the USA for this project let me know. Yes, and of course, we'll send these as a gift to avoid the VAT and associated crazy taxes in Sweden (?).
If You have time -- You can look on SCH's attached as PDF
Some of pages are A3 dimensions
Sapieha,
Looks generally good, but I noticed a few things:
1) You need to center the 13-pin ribbon header between the two main headers on the DE0-Nano. Move it left a little bit. Otherwise, the ribbon will be taking up the difference and looking skewed.
2) On the R-2R ladders, the R values should be 65 ohms, including the two series R's that make the GND leg of the circuit. The 2R values that are driven by the pins should be 110 ohms.
I didn't take the time to go over every detail yet, but I noticed that these things need addressing. The first one affects the PCB.
That schematic would get a lot simpler if you used labels for signal names and symbols for power and ground. Then, you don't have to drag wires everywhere. Think of it as wireless.
1) You need to center the 13-pin ribbon header between the two main headers on the DE0-Nano. Move it left a little bit. Otherwise, the ribbon will be taking up the difference and looking skewed.
2) On the R-2R ladders, the R values should be 65 ohms, including the two series R's that make the GND leg of the circuit. The 2R values that are driven by the pins should be 110 ohms.
I didn't take the time to go over every detail yet, but I noticed that these things need addressing. The first one affects the PCB.
That schematic would get a lot simpler if you used labels for signal names and symbols for power and ground. Then, you don't have to drag wires everywhere. Think of it as wireless.
I have a question about using the 4 tasks within 1 cog.
If one of the tasks hits a wait instruction (WAITPEQ for example), do the other tasks stop as well ? Or do they continue to execute while the task that has the WAITPEQ stops ?
I have a question about using the 4 tasks within 1 cog.
If one of the tasks hits a wait instruction (WAITPEQ for example), do the other tasks stop as well ? Or do they continue to execute while the task that has the WAITPEQ stops ?
My understanding is that this will stall all of the tasks. The instruction pipeline tracks which task an instruction belongs to, but the instructions are otherwise treated the same as if there were only one task.
I have a question about using the 4 tasks within 1 cog.
If one of the tasks hits a wait instruction (WAITPEQ for example), do the other tasks stop as well ? Or do they continue to execute while the task that has the WAITPEQ stops ?
Thanks,
Bean
I thought this had been answered previously in the 90 pages of this thread. There's bunches of info (too much) in here to be sifted through and verified.
If you use the normal version of WAITxxx instructions, all threads halt, however Chip added non-blocking versions that set the Carry flag, so you can poll them.
I have a question about using the 4 tasks within 1 cog.
If one of the tasks hits a wait instruction (WAITPEQ for example), do the other tasks stop as well ? Or do they continue to execute while the task that has the WAITPEQ stops ?
If you use the normal version of WAITxxx instructions, all threads halt, however Chip added non-blocking versions that set the Carry flag, so you can poll them.
I know that all of this information is going to be forthcoming, but I am wondering if you refer to the timeout mechanism Chip mentioned in post #1589:
WAITPEQ/WAITPNE now have timeouts. If the WC (write carry) bit is set, the last ALU result is used as a value to compare CNT to and upon exit of the instruction, C=1 if a timeout occurred, or C=0 if the WAITPxx condition was met.
If so, and assuming that latching a value of zero in the ALU would allow a WAITxxx instruction to complete immediately, would this avoid a pipeline stall?
Regardless, this would mean that polling would potentially require two instructions: one to set the ALU, one to WAITxxx. I wonder if it would have been easier to have the Carry flag simply mean "complete immediately with carry bit set", then use a tight loop to implement the timeout functionality. This might be preferable when multiple tasks are running, as it would avoid stalls.
I have a question about using the 4 tasks within 1 cog.
If one of the tasks hits a wait instruction (WAITPEQ for example), do the other tasks stop as well ? Or do they continue to execute while the task that has the WAITPEQ stops ?
My understanding is the tasks are time slices, and each slice has no idea, or need to know, what the others are doing.
I believe the only impact, is a lowered clock speed (naturally from the slice allocate proportion)
I think there is also a WAITPEQ variant, that is a little more flexible (but may not be as granular).
Yes, it goes without saying that boards will be ready from day 0 which will be at the PROPer time for it (would be good to have some early shuttle run "crumbs"). I have designs sitting around just waiting to be tweaked before I commit them to production. When chips are available then it's simply a matter of popping it on, load my pretested Tachyon software and me and P2 are talking.
Now, does anyone know what the equivalent of WAITPxx is on P2. I know it says it is the same but that does that mean it only works on PINA or does the pin numbering extend across the ports which I would assume it does, so therefore it is not really the same as P1.
Peter,
There is a SETPORT instruction that selects between the banks of 32 I/O pins. It determines what pins are going to be used with things like WAITPXX and such.
Peter,
There is a SETPORT instruction that selects between the banks of 32 I/O pins. It determines what pins are going to be used with things like WAITPXX and such.
Thanks Roy, I remember that instruction now. But perusing the ROM code I can see many instructions that have not been documented yet such as PASSCNT, CHKSPx etc. I await the documentation!
Comments
Thanks.
I will send that info to You -- But You can even give them my e-mail if them have additional questions.
But I don't have Yours e-mail address.
My are -- christofferj2@gmail.com.
send me Yours to my e-mail so I will send all files to You as fats Chip approve SHC's
Have some time to be clear with them
Ps. all You send to me with PCB's --- Send as private post office BOX else it will be much charge to me WAT and that other payments.
I'm kgracey@parallaxsemiconductor.com. If you (or anybody else) has a recommended PCB fabricator in the USA for this project let me know. Yes, and of course, we'll send these as a gift to avoid the VAT and associated crazy taxes in Sweden (?).
Try "sean@pcbnet.com" - I've gotten super nice PCB's from them. They are not cheap, but they are fast and very high quality.
What Sapieha ment is have a personal (non-company) "From" address, as if there is any company name on shipping labels he will get hit with a huge VAT.
Declared values <$100 are fine.
Bill
If You have time -- You can look on SCH's attached as PDF
Some of pages are A3 dimensions
Thanks Bill. That completes the picture for me nicely. I'll send the package USPS personally.
And we'll use PCBNet for Sapieha's PCBs.
If Chip approve SCH's --- PCB are clear.
Look on Pictures.
Thanks
Sapieha,
Looks generally good, but I noticed a few things:
1) You need to center the 13-pin ribbon header between the two main headers on the DE0-Nano. Move it left a little bit. Otherwise, the ribbon will be taking up the difference and looking skewed.
2) On the R-2R ladders, the R values should be 65 ohms, including the two series R's that make the GND leg of the circuit. The 2R values that are driven by the pins should be 110 ohms.
I didn't take the time to go over every detail yet, but I noticed that these things need addressing. The first one affects the PCB.
That schematic would get a lot simpler if you used labels for signal names and symbols for power and ground. Then, you don't have to drag wires everywhere. Think of it as wireless.
I see that problem on 2x13 header -- thanks
I don't had resistor values to R2R net so on SCH had default values Proteus-ISIS give me
I have with my bad eyes simpler to see traces -- BUT You are correct that with symbols SCH are simpler.
Thanks.
Have You look on page 2 about comment on Analogue IN ??
"I see that problem on 2x13 header" ----> Corrected
SCH's with correct Resistor values to R2R
And enabled colour printing from Proteus ---> Now You can see why my eyes have simpler to see that
If one of the tasks hits a wait instruction (WAITPEQ for example), do the other tasks stop as well ? Or do they continue to execute while the task that has the WAITPEQ stops ?
Thanks,
Bean
My understanding is that this will stall all of the tasks. The instruction pipeline tracks which task an instruction belongs to, but the instructions are otherwise treated the same as if there were only one task.
I thought this had been answered previously in the 90 pages of this thread. There's bunches of info (too much) in here to be sifted through and verified.
I know that all of this information is going to be forthcoming, but I am wondering if you refer to the timeout mechanism Chip mentioned in post #1589:
If so, and assuming that latching a value of zero in the ALU would allow a WAITxxx instruction to complete immediately, would this avoid a pipeline stall?
Regardless, this would mean that polling would potentially require two instructions: one to set the ALU, one to WAITxxx. I wonder if it would have been easier to have the Carry flag simply mean "complete immediately with carry bit set", then use a tight loop to implement the timeout functionality. This might be preferable when multiple tasks are running, as it would avoid stalls.
If You don't find any more dimensions else text errors -- PCB are clear.
Resistors for R2R are 0805 -- for possibility to hand solder.
Even all others components are simple to hand solder.
If You answer before Monday --- Ken will have files that day.
If so, with that info and the FPGA emulator, I think I could have a cool board ready on day 0...
My understanding is the tasks are time slices, and each slice has no idea, or need to know, what the others are doing.
I believe the only impact, is a lowered clock speed (naturally from the slice allocate proportion)
I think there is also a WAITPEQ variant, that is a little more flexible (but may not be as granular).
Ditto
(me 3)
May we live in interesting times!!
Now, does anyone know what the equivalent of WAITPxx is on P2. I know it says it is the same but that does that mean it only works on PINA or does the pin numbering extend across the ports which I would assume it does, so therefore it is not really the same as P1.
There is a SETPORT instruction that selects between the banks of 32 I/O pins. It determines what pins are going to be used with things like WAITPXX and such.
Pic show PCB that will be send to Ken for production.
Anyone that will have that
NEED talk to Ken
Sapieha,
We will probably sell your boards at cost to whoever wants one, and then give some away.
You should put your name on it, by the way, since you designed it.
It would probably good if you made a Digi-Key parts list so that people could easily order all the parts that they'll need for it.
Our little DE0-Nano board is much simpler and will be sold assembled. At least, that's how I see things shaping up.