I'm getting visions of spoiled christmas dinners all over the world, because daddies refuses to leave their study where they are frantically hacking PII code on their FPGA board's. I have one DE2-115 and two DE0-nano boards available, so count me in. Thinking: 6 Cogs on DE2 + 2 x 1 Cog on DE0 = 8 Cogs....Design the worlds first multi PII emulator system??
If you allow enough room around the 7805 for a R-78E5.0-0.5 switching module ($2.32 @100 off) then you can replace the 7805 easily and don't have to worry about supply current and voltage problems.
That is a neat idea. I could make an instruction that remaps bits from a byte or word into a 32-bit instruction, but it might be a little late for that now. If there were only one or two really useful remaps, they could be implemented pretty easily at RTL-design-time.
Chip,
If you're considering adding that sort of remap in hardware you might want to look at the CMM instruction set used by Propeller GCC. It would be great to get hardware assist to improve CMM performance. Eric Smith can give you more details.
Soft-cores of Parallax Prop2? Pretty amazing to see one of these! Bigger semicon/processor companies won't usually share the FPGA cores to the public. I haven't seen any 286 in soft-core form, seriously.
Soft-cores of Parallax Prop2? Pretty amazing to see one of these! Bigger semicon/processor companies won't usually share the FPGA cores to the public. I haven't seen any 286 in soft-core form, seriously.
How easy is it to reverse engineer the design from an FPGA configuration file? That may be why most companies won't let them out to the public.
How easy is it to reverse engineer the design from an FPGA configuration file? That may be why most companies won't let them out to the public.
So far, only the 8086/8088, the venerable 6502, and the AVR (alongside with some PIC16Fs) are now available in soft-core forms too. Even ARMs have soft-cores but I suspect a lot of money should be paid to obtain those.
I believe that the 286 is much complicated than the 8088 due to the extra stuff inside like "real mode" or "protected mode" thingy. That, and the supporting circuits inside too.
It will not be soft-core that You can add to Yours own system.
It will be Config-binary file that give You closed Propeller II system that You can't modify
Only use as emulator for Learn/testing Yours programming skills
So far, only the 8086/8088, the venerable 6502, and the AVR (alongside with some PIC16Fs) are now available in soft-core forms too. Even ARMs have soft-cores but I suspect a lot of money should be paid to obtain those.
I believe that the 286 is much complicated than the 8088 due to the extra stuff inside like "real mode" or "protected mode" thingy. That, and the supporting circuits inside too.
John, on http://opencores.org/projects under processors you will find dozens of examples of soft processors on source level. "Zet" is a limited (and slow) but working model of the Intel architecture. Altera is pushing their "NIOS" design, Xilinx their "microblaze". As Sapieha pointed out, the current idea is that Parallax could supply a ready to run configuration file that defines the millions of switches inside the FPGA. This allows users of that FPGA to run the model without being able to look into it or change it, but allows them create and run software for the PII. Reverse engineering this configuration file into a high level RTL model is impossible. Thank God, given the creative energy on this forum, only a handfull of forum members would be able to create dozens of application specific variations of the model without any version control in a matter of days.
As Sapieha pointed out, the current idea is that Parallax could supply a ready to run configuration file that defines the millions of switches inside the FPGA. This allows users of that FPGA to run the model without being able to look into it or change it, but allows them create and run software for the PII. Reverse engineering this configuration file into a high level RTL model is impossible.
It's good to hear that reverse enginneering the configuration file would be impossible. I suspected as much but just wanted to make sure so that Parallax didn't inadvertently give away their design. Of course, when you say "impossible" in this forum, you just may find someone who accepts the challenge is able to do it! :-)
This time impossible Have theirs meaning.
For reverse engineering
1. You need have MAP of all millions of configurations cells and what every cell i control do.
2 Even that give big problems to reverse engineering.
It's good to hear that reverse enginneering the configuration file would be impossible. I suspected as much but just wanted to make sure so that Parallax didn't inadvertently give away their design. Of course, when you say "impossible" in this forum, you just may find someone who accepts the challenge is able to do it! :-)
I understand you think 8-bit DACs would be fine, and the reality is that being R-2R implementations, they are not going to be that great, but to get rid of the LSB would mean that the dithering would seem very sporadic. In the actual silicon, there are 512 identical discrete resistors that sum together, making the DAC monotonic. On the FPGA we must account for the intrinsic pin impedance, making the R value less than 1/2 the 2R value.
It's good to hear that reverse enginneering the configuration file would be impossible. I suspected as much but just wanted to make sure so that Parallax didn't inadvertently give away their design.
This size of FPGA needed gives plenty of protection anyway. - and even at many hundreds of dollars, the emulation given is still only subset, of what should be a sub $20 part ? (even sub $10 in moderate volumes?)
That's even before Size and Power are considered.
It makes very good sense to seed software development, as that will strongly affect the sales ramp-up
I have looked on it little more.
AND.
With using 3 GPIO connector on NANO with short ribbon cable -- and some bigger PCB that have place on bottom of NANO for strapping connector between NANO and PCB it is possible to use most of available signals on NANO.
That can give 32 digital I/O's + 4x9 DAC's and signals needed for FLASH and other things You have on PCB.
Tomorrow I will post some PIC's what I mean.
have still some work on them
I understand you think 8-bit DACs would be fine, and the reality is that being R-2R implementations, they are not going to be that great, but to get rid of the LSB would mean that the dithering would seem very sporadic. In the actual silicon, there are 512 identical discrete resistors that sum together, making the DAC monotonic. On the FPGA we must account for the intrinsic pin impedance, making the R value less than 1/2 the 2R value.
I have looked on it little more.
AND.
With using 3 GPIO connector on NANO with short ribbon cable -- and some bigger PCB that have place on bottom of NANO for strapping connector between NANO and PCB it is possible to use most of available signals on NANO.
That can give 32 digital I/O's + 4x9 DAC's and signals needed for FLASH and other things You have on PCB.
Tomorrow I will post some PIC's what I mean.
have still some work on them
Adding a ribbon cable is getting messy, I think. Maybe the best way to handle the 2x13 header is just to map those GPIO pins into the 92-pin space that exists inside the Prop2. That way, you can hook to them if you want, but we don't need more clutter for what is only a 1-cog emulator.
Maybe
BUT more important -- IT give 32 Digital I/O pins for experiments (Real value of one Port Bank).
And 5-cm ribbon cable that not connect to outside world -- <only from NANO to Yours PCB -- will never be disturbing
Adding a ribbon cable is getting messy, I think. Maybe the best way to handle the 2x13 header is just to map those GPIO pins into the 92-pin space that exists inside the Prop2. That way, you can hook to them if you want, but we don't need more clutter for what is only a 1-cog emulator.
No, no! Wait! Get the updated instruction documentation out first! Then we can be updating Gear in parallel with the FPGA effort. (Yes, I may sound like a broken record on the documentation, but the FPGA option is a non-starter for me. I'd be bummed if I have to wait for the general release of P2 before I could start playing with it.)
Well, I just destroyed my DE2-115 board. $600+shipping gone.
That high-density Samtec HSMC connector has 12V(!!!) pins between every two signal pins along the PCB-edge side of the connector. I was probing it with a fine tipped probe through a magnifying glass, trying to discover the cause of an apparently inactive pin, when the switching supply started singing. The FPGA got too hot to touch through the back of the PCB and it is now dead. Here is the schematic with some helpful warnings I added:
I guess the takeaway is that our existing adapter board design was probably okay, after all, as I believe this same DE2-115 board had suffered something like this earlier, after Daniel first brought it up. Time to order another one.
Well, I just destroyed my DE2-115 board. $600+shipping gone.
That high-density Samtec HSMC connector has 12V(!!!) pins between every two signal pins along the PCB-edge side of the connector. I was probing it with a fine tipped probe through a magnifying glass, trying to discover the cause of an apparently inactive pin, when the switching supply started singing. The FPGA got too hot to touch through the back of the PCB and it is now dead. Here is the schematic with some helpful warnings I added:
I guess the takeaway is that our existing adapter board design was probably okay, after all, as I believe this same DE2-115 board had suffered something like this earlier, after Daniel first brought it up. Time to order another one.
Well, I just destroyed my DE2-115 board. $600+shipping gone.
That high-density Samtec HSMC connector has 12V(!!!) pins between every two signal pins along the PCB-edge side of the connector.
Yikes. Are those really 12v, or did they mean Vcc1.2v ?
It just seems weird to truck 12V onto high density connectors ?
Sorry to hear about your board... but why on earth would they do something that dumb?
I could see a lot of grounds, but 12V ????
Mixing 12V power and logic right next to each other is a recipe for success. Yes, you can sell many more replacement boards as the WHEN will be far more probably then the IF. Anyway, glad to know I'm not the only one who lets a fine tipped probe slip across pins to let the magic smoke out (but not $600 smoke).
I'm getting a DE0 or two for the more "dangerous" tests I think.
Mixing 12V power and logic right next to each other is a recipe for success. Yes, you can sell many more replacement boards as the WHEN will be far more probably then the IF. Anyway, glad to know I'm not the only one who lets a fine tipped probe slip across pins to let the magic smoke out (but not $600 smoke).
I'm getting a DE0 or two for the more "dangerous" tests I think.
Comments
Can that 7805 get accidently bent into the Power connector end-tab ?
7805 do come in TO220F (insulated packs), but better might be a D2PAK ?
You're right. Better turn it around or use SMT parts.
Regards
Nico Hattink
If you're considering adding that sort of remap in hardware you might want to look at the CMM instruction set used by Propeller GCC. It would be great to get hardware assist to improve CMM performance. Eric Smith can give you more details.
David
I have looked on Yours PDF.
And I think it not optimally use all GP_I/O's
Like simple that from bit positions in Long without additional information SEE what it is for PASM instruction
So far, only the 8086/8088, the venerable 6502, and the AVR (alongside with some PIC16Fs) are now available in soft-core forms too. Even ARMs have soft-cores but I suspect a lot of money should be paid to obtain those.
I believe that the 286 is much complicated than the 8088 due to the extra stuff inside like "real mode" or "protected mode" thingy. That, and the supporting circuits inside too.
It will not be soft-core that You can add to Yours own system.
It will be Config-binary file that give You closed Propeller II system that You can't modify
Only use as emulator for Learn/testing Yours programming skills
Nico Hattink
This time impossible Have theirs meaning.
For reverse engineering
1. You need have MAP of all millions of configurations cells and what every cell i control do.
2 Even that give big problems to reverse engineering.
What a Christmas Season!
The first dreams, just a glance ....
http://forums.parallax.com/showthread.php?144137-NASA-looking-into-Warp-Drive-development
Semms a little prophetic?
Now, Chip providing DEx Whormholes!
Paradise is here.
Thanks Tina!
Yanomani
What would you like to see?
I understand you think 8-bit DACs would be fine, and the reality is that being R-2R implementations, they are not going to be that great, but to get rid of the LSB would mean that the dithering would seem very sporadic. In the actual silicon, there are 512 identical discrete resistors that sum together, making the DAC monotonic. On the FPGA we must account for the intrinsic pin impedance, making the R value less than 1/2 the 2R value.
This size of FPGA needed gives plenty of protection anyway. - and even at many hundreds of dollars, the emulation given is still only subset, of what should be a sub $20 part ? (even sub $10 in moderate volumes?)
That's even before Size and Power are considered.
It makes very good sense to seed software development, as that will strongly affect the sales ramp-up
I have looked on it little more.
AND.
With using 3 GPIO connector on NANO with short ribbon cable -- and some bigger PCB that have place on bottom of NANO for strapping connector between NANO and PCB it is possible to use most of available signals on NANO.
That can give 32 digital I/O's + 4x9 DAC's and signals needed for FLASH and other things You have on PCB.
Tomorrow I will post some PIC's what I mean.
have still some work on them
Adding a ribbon cable is getting messy, I think. Maybe the best way to handle the 2x13 header is just to map those GPIO pins into the 92-pin space that exists inside the Prop2. That way, you can hook to them if you want, but we don't need more clutter for what is only a 1-cog emulator.
Maybe
BUT more important -- IT give 32 Digital I/O pins for experiments (Real value of one Port Bank).
And 5-cm ribbon cable that not connect to outside world -- <only from NANO to Yours PCB -- will never be disturbing
On pic's is my thinking on that PCB
That high-density Samtec HSMC connector has 12V(!!!) pins between every two signal pins along the PCB-edge side of the connector. I was probing it with a fine tipped probe through a magnifying glass, trying to discover the cause of an apparently inactive pin, when the switching supply started singing. The FPGA got too hot to touch through the back of the PCB and it is now dead. Here is the schematic with some helpful warnings I added:
I guess the takeaway is that our existing adapter board design was probably okay, after all, as I believe this same DE2-115 board had suffered something like this earlier, after Daniel first brought it up. Time to order another one.
I could see a lot of grounds, but 12V ????
Yikes. Are those really 12v, or did they mean Vcc1.2v ?
It just seems weird to truck 12V onto high density connectors ?
I'm getting a DE0 or two for the more "dangerous" tests I think.
Sheesh.
Next, someone will find a "warranty" chip (RTC) that blows the board after 12 months...