@evanh said:
Are TCXO not logic level outputs? I would've thought "CMOS" implied they are.
They can be.
The biggest market for TCXO is GPS etc, and those are usually 26MHz / 38.4MHz / 52Mhz / 19.2MHz etc with clipped sine out. Gives Lower Icc, and lower RFI.
Some part codes also offer CMOS as an option, but as you see below, that's not offered soonest in the newest, smallest packages. https://www5.epsondevice.com/en/products/tcxo/
I don't think that's a brick-wall issue, just that they chase the largest customers first.
Other examples are ECS-TXO-20CSMV, which is 2016 and only clipped sine / currently part codes for 26MHz only,
whilst the variant ECS-TXO-2016 is CMOS out and part codes for 10.000 12.000 16.000 20.000 25.000 32.000 40.000 50.000 MHz
Yes, those empty spots are for trimming caps, should there be a need. But also for configuring power to an oscillator. The pads are close indeed, but not incredibly close. The picture misleads a bit. There isn't a lot of space there anyway, to spread out freely
@knivd said:
Yes, those empty spots are for trimming caps, should there be a need. But also for configuring power to an oscillator. The pads are close indeed, but not incredibly close. The picture misleads a bit. There isn't a lot of space there anyway, to spread out freely
These new parts are not quite P2-ideal, as they assume one MCU Xtal pin can be set logic-high, but the sales-pitch is interesting.
Also unclear if a 2016 package part exists. Digikey has a code, SiTime does not ?
Sales: 'The XCalibur™ SiT1408 active resonator is a drop-in replacement for 4-pin SMD quartz crystal resonators'
Engineering : Oh, you need to have grounded pins 2,4 and add a Pin1 4n7 CAP with Pin 1 defined HIGH to power the part, with pin 3 as CLKOUT, but that's almost 'drop-in replacement', right ?
Most AVR etc MCUs could have PCBs designed to alternate-fit this part.
Yes, all that done by the book. Not the first one I am making...
Pin 1 on all (well, at least 99%) oscillators is driven low to force standby mode, but left floating the oscillator is enabled by default throung an internal pullup. This is how I have done it here. There is an optional 0R resistor from pin 1 to pin XO, which is installed in case of a crystal. The other one is pin 4, which can have either connection to +3.3V and capacitor to ground, or no connection to power and 0R to ground. Pins 2 and 3 are compatible on crystals and oscillators. The trimming caps are still there as well in case of a crystal being used, which is the default mode in my design.
@knivd said:
Here is how it looks inside without the polygons
Looks nifty.
I've seen some edge-terminated designs use two plated holes, instead of just 1, to give a little stress redundancy for top-bottom connections.
It looks like you have room for adding a medium sized via on those edge pads ?
@knivd said:
Hi All,
Here is something new, on which I have been working for a while. A chip-scale P2-STAMP module, which is only about 30x30mm in size, and fits into a standard PLCC-84 socket.
Which sockets have you allowed for, in the underside clearances ?
I see PLCC-84 sockets vary, some have 4 x peg- standoffs, some have 4 x arc stand offs, some SMD ones have no stand offs, and some SMD ones have 4 short standoffs.
The lcsc ones, (no stock, but good price ) show 4 squarer arcs.
I have never seen the need for adding a second hole inside the pad, but that won't be a problem. Will investigate further.
The module is on a 1.2mm PCB and has underneath only resistors adding no more than 0.5mm. Even with 1.6mm base will fit in all sockets, including those with arcs.
It looks like this is an attempt to get all of the high speeds stuff in a single package so that the average builder doesn't have to deal with the reliability of the long traces and surface mounting. To that end, I know it is tight, but have you thought about putting 4 PSRAM's on the back, or maybe even just 1? The 4bit interface seems to be fast enough at 340MHz for some emulation, like Ada's MegaYume.
@hinv said:
It looks like this is an attempt to get all of the high speeds stuff in a single package so that the average builder doesn't have to deal with the reliability of the long traces and surface mounting. To that end, I know it is tight, but have you thought about putting 4 PSRAM's on the back, or maybe even just 1? The 4bit interface seems to be fast enough at 340MHz for some emulation, like Ada's MegaYume.
There is already an 8-bit PSRAM in the module. Please check the first post in the thread
@knivd said:
There is already an 8-bit PSRAM in the module. Please check the first post in the thread
I think you may have meant 8-bit HyperRAM which is a specific type of PSRAM using a Hyperbus protocol vs the QSPI accessed PSRAM that @hinv refers to.
@hinv In theory an 8-bit HyperRAM can perform around the same or slightly faster per clock than the 16 bit QSPI PSRAM array because it has the ability to be clocked at twice the rate of PSRAM due to DDR. HyperRAM is faster whenever PSRAM needs to write single bytes/words which generate read-modify-write cycle overheads on 16 bit wide arrays. At the higher sysclk/1 streamer rate HyperRAM requires tight timing control though on the circuit board. My HyperRAM driver can support sysclk/1 streamer operation but I've found the input timing gets harder to meet across a larger range of clock frequencies. @evanh has done some work looking at this. In comparison the PSRAM timing is a lot simpler and we usually get a sampling interval closer to the the middle of a bit because there are always 2 P2 clock choices per data cycle we can use for sampling the data.
8bit HyperRAM @ sysclk/2 streamer rate is 1 HyperRAM clock cycle every 4 P2 clocks, and 2x 8-bit transfers per HyperRAM clock (DDR)
8bit HyperRAM @ sysclk/1 streamer rate is 1 HyperRAM clock cycle every 2 P2 clocks, and 2x 8-bit transfers per HyperRAM clock (DDR)
4x4bit PSRAMs @ sysclk/2 streamer rate is 1 PSRAM clock cycle every 2 P2 clocks, and 1x16 bit transfer per PSRAM clock (SDR)
The sorry state at the moment is there is only one setup with HyperRAM - The Eval Board accessory. Which is performance limited by the routing involved in it being a plug-in board. And further limited by the loading of the paralleled HyperFlash chip.
This module will be the first one that has a HyperRAM placed suitably to, potentially at least, unleash sysclock/1 throughput.
@MacTuxLin said:
Very nice. Where will this be sold, eventually?
The only stopping factor right now is the initial prototyping costs which I need to absorb at this stage. It is practically ready to go, so hopefully (very) soon
Update:
After a few months delay, the first prototypes are a fact, and a good one too.
I am currently designing a board for one of my current projects and will have a chance to test the Stamp in it in real life conditions soon, after which if the results are good, will start thinking how to make it available to a broader market. What puts me off is the terrifying logistics process associated with such activities. Any ideas about that?
Would you be willing to source the board, BOM and schematics? I would try building one for myself, be an interesting DIY build. If you are willing, list or PM a price for these.
@knivd said:
Update:
After a few months delay, the first prototypes are a fact, and a good one too.
I am currently designing a board for one of my current projects and will have a chance to test the Stamp in it in real life conditions soon, after which if the results are good, will start thinking how to make it available to a broader market. What puts me off is the terrifying logistics process associated with such activities. Any ideas about that?
Great to see your first board is back. You've made amazing use of the space available @knivd and it looks fabulous.
I hope the thermal performance is good with this and am wondering about heatsink options. If the heights of the components allow, perhaps a larger heatsink can cover multiple components including and surrounding the P2, increasing the heat dissipating area (the SD card reader looks like the tallest component which may limit the size of the heatsink if it won't sit flat, or any regulator caps that might short to a heatsink). Also maybe a fan can be mounted over the entire thing somehow and there are low cost 30x30mm or 40x40mm fans available which may help. A 40x40mm or larger could cover the entire PLCC socket carrying the P2 stamp.
In any final board that is soldered to the P2 stamp directly without the PLCC socket, is there an exposed pad path under your board for heat to travel down to the board it's soldered to, as that would be another way for heat to be removed. What does it look like on the reverse side of your board?
One other thing: How have you shared the IO pins with the RTC? Is it shared with the boot SPI flash or HyperRAM pins?
@"frank freedman" said:
Would you be willing to source the board, BOM and schematics? I would try building one for myself, be an interesting DIY build. If you are willing, list or PM a price for these.
I will certainly release all about the board, once I establish that it works as it is supposed to. Don't want to release designs which will later turn out non-functional. So, just a bit more patience with me on this, please.
This is the schematic here, which is loosely based on the Parallax's Edge module. Note again - this one first revision, not tested yet.
I hope the thermal performance is good with this and am wondering about heatsink options. If the heights of the components allow, perhaps a larger heatsink can cover multiple components including and surrounding the P2, increasing the heat dissipating area (the SD card reader looks like the tallest component which may limit the size of the heatsink if it won't sit flat, or any regulator caps that might short to a heatsink). Also maybe a fan can be mounted over the entire thing somehow and there are low cost 30x30mm or 40x40mm fans available which may help. A 40x40mm or larger could cover the entire PLCC socket carrying the P2 stamp.
In any final board that is soldered to the P2 stamp directly without the PLCC socket, is there an exposed pad path under your board for heat to travel down to the board it's soldered to, as that would be another way for heat to be removed. What does it look like on the reverse side of your board?
One other thing: How have you shared the IO pins with the RTC? Is it shared with the boot SPI flash or HyperRAM pins?
I have taken great care regarding the thermal challenges. There are a few layers in the PCB with that very purpose and lead the heat out to the carrier board through several ground pins.
The module can be soldered on a PCB, provided there is a 25x25mm cutout to accommodate the components on the bottom side. The overlay lines on the bottom are marking those limits. Or, as an idea - if the cutout is 28x28, it will be possible to fit the top side in it (obviously, flipping the footprint), thus making the entire design flatter and more secure. That way it may be simpler to install a fan too, if necessary.
This is how the bottom side looks like.
Note to self: expose the copper under P2 in the area surrounded by capacitors, for improved heat dissipation.
Comments
They can be.
The biggest market for TCXO is GPS etc, and those are usually 26MHz / 38.4MHz / 52Mhz / 19.2MHz etc with clipped sine out. Gives Lower Icc, and lower RFI.
Some part codes also offer CMOS as an option, but as you see below, that's not offered soonest in the newest, smallest packages.
https://www5.epsondevice.com/en/products/tcxo/
I don't think that's a brick-wall issue, just that they chase the largest customers first.
Other examples are ECS-TXO-20CSMV, which is 2016 and only clipped sine / currently part codes for 26MHz only,
whilst the variant ECS-TXO-2016 is CMOS out and part codes for 10.000 12.000 16.000 20.000 25.000 32.000 40.000 50.000 MHz
Oh I see, CMOS is not clipped-sine version.
This is how it looks now after the clock mods. Really tight on the top side...
Looks nice
Are you allowing for extra caps option on Xtal, to give you more buying choices, (matters these days) and allow some trim for offsets ?
Some of the edge (signal ?) pins look quite close to the Xtal pads, but not a lot you can do about that. Are most of those close pads GND ?
Yes, those empty spots are for trimming caps, should there be a need. But also for configuring power to an oscillator. The pads are close indeed, but not incredibly close. The picture misleads a bit. There isn't a lot of space there anyway, to spread out freely
These new parts are not quite P2-ideal, as they assume one MCU Xtal pin can be set logic-high, but the sales-pitch is interesting.
Also unclear if a 2016 package part exists. Digikey has a code, SiTime does not ?
https://www.sitime.com/products/resonators#cat4417
Sales: 'The XCalibur™ SiT1408 active resonator is a drop-in replacement for 4-pin SMD quartz crystal resonators'
Engineering : Oh, you need to have grounded pins 2,4 and add a Pin1 4n7 CAP with Pin 1 defined HIGH to power the part, with pin 3 as CLKOUT, but that's almost 'drop-in replacement', right ?
Most AVR etc MCUs could have PCBs designed to alternate-fit this part.
Yes, all that done by the book. Not the first one I am making...
Pin 1 on all (well, at least 99%) oscillators is driven low to force standby mode, but left floating the oscillator is enabled by default throung an internal pullup. This is how I have done it here. There is an optional 0R resistor from pin 1 to pin XO, which is installed in case of a crystal. The other one is pin 4, which can have either connection to +3.3V and capacitor to ground, or no connection to power and 0R to ground. Pins 2 and 3 are compatible on crystals and oscillators. The trimming caps are still there as well in case of a crystal being used, which is the default mode in my design.
Very nice, where is the "buy now" button? I want one :-)
Here is how it looks inside without the polygons
Looks nifty.
I've seen some edge-terminated designs use two plated holes, instead of just 1, to give a little stress redundancy for top-bottom connections.
It looks like you have room for adding a medium sized via on those edge pads ?
Which sockets have you allowed for, in the underside clearances ?
I see PLCC-84 sockets vary, some have 4 x peg- standoffs, some have 4 x arc stand offs, some SMD ones have no stand offs, and some SMD ones have 4 short standoffs.
The lcsc ones, (no stock, but good price ) show 4 squarer arcs.
I have never seen the need for adding a second hole inside the pad, but that won't be a problem. Will investigate further.
The module is on a 1.2mm PCB and has underneath only resistors adding no more than 0.5mm. Even with 1.6mm base will fit in all sockets, including those with arcs.
Excited to see this in the "flesh" 👍😎👍
It looks like this is an attempt to get all of the high speeds stuff in a single package so that the average builder doesn't have to deal with the reliability of the long traces and surface mounting. To that end, I know it is tight, but have you thought about putting 4 PSRAM's on the back, or maybe even just 1? The 4bit interface seems to be fast enough at 340MHz for some emulation, like Ada's MegaYume.
There is already an 8-bit PSRAM in the module. Please check the first post in the thread
I think you may have meant 8-bit HyperRAM which is a specific type of PSRAM using a Hyperbus protocol vs the QSPI accessed PSRAM that @hinv refers to.
@hinv In theory an 8-bit HyperRAM can perform around the same or slightly faster per clock than the 16 bit QSPI PSRAM array because it has the ability to be clocked at twice the rate of PSRAM due to DDR. HyperRAM is faster whenever PSRAM needs to write single bytes/words which generate read-modify-write cycle overheads on 16 bit wide arrays. At the higher sysclk/1 streamer rate HyperRAM requires tight timing control though on the circuit board. My HyperRAM driver can support sysclk/1 streamer operation but I've found the input timing gets harder to meet across a larger range of clock frequencies. @evanh has done some work looking at this. In comparison the PSRAM timing is a lot simpler and we usually get a sampling interval closer to the the middle of a bit because there are always 2 P2 clock choices per data cycle we can use for sampling the data.
The sorry state at the moment is there is only one setup with HyperRAM - The Eval Board accessory. Which is performance limited by the routing involved in it being a plug-in board. And further limited by the loading of the paralleled HyperFlash chip.
This module will be the first one that has a HyperRAM placed suitably to, potentially at least, unleash sysclock/1 throughput.
Very nice. Where will this be sold, eventually?
Looks neat 👌
The only stopping factor right now is the initial prototyping costs which I need to absorb at this stage. It is practically ready to go, so hopefully (very) soon
I’m joining the waiting list :-)
I’m joining the waiting list :-)
Update:
After a few months delay, the first prototypes are a fact, and a good one too.
I am currently designing a board for one of my current projects and will have a chance to test the Stamp in it in real life conditions soon, after which if the results are good, will start thinking how to make it available to a broader market. What puts me off is the terrifying logistics process associated with such activities. Any ideas about that?
Parallax might want to buy the design. It sure looks good. It'll totally fit their marketing too. The PropStamp
Yes, that could be ideal, if they are interested.
@knivd
, I have been waiting for a positive update 
This is great news
Craig
Would you be willing to source the board, BOM and schematics? I would try building one for myself, be an interesting DIY build. If you are willing, list or PM a price for these.
Great to see your first board is back. You've made amazing use of the space available @knivd and it looks fabulous.
I hope the thermal performance is good with this and am wondering about heatsink options. If the heights of the components allow, perhaps a larger heatsink can cover multiple components including and surrounding the P2, increasing the heat dissipating area (the SD card reader looks like the tallest component which may limit the size of the heatsink if it won't sit flat, or any regulator caps that might short to a heatsink). Also maybe a fan can be mounted over the entire thing somehow and there are low cost 30x30mm or 40x40mm fans available which may help. A 40x40mm or larger could cover the entire PLCC socket carrying the P2 stamp.
In any final board that is soldered to the P2 stamp directly without the PLCC socket, is there an exposed pad path under your board for heat to travel down to the board it's soldered to, as that would be another way for heat to be removed. What does it look like on the reverse side of your board?
One other thing: How have you shared the IO pins with the RTC? Is it shared with the boot SPI flash or HyperRAM pins?
That really is a work of art, Knivd. Well done
I will certainly release all about the board, once I establish that it works as it is supposed to. Don't want to release designs which will later turn out non-functional. So, just a bit more patience with me on this, please.
This is the schematic here, which is loosely based on the Parallax's Edge module. Note again - this one first revision, not tested yet.
I have taken great care regarding the thermal challenges. There are a few layers in the PCB with that very purpose and lead the heat out to the carrier board through several ground pins.
The module can be soldered on a PCB, provided there is a 25x25mm cutout to accommodate the components on the bottom side. The overlay lines on the bottom are marking those limits. Or, as an idea - if the cutout is 28x28, it will be possible to fit the top side in it (obviously, flipping the footprint), thus making the entire design flatter and more secure. That way it may be simpler to install a fan too, if necessary.
This is how the bottom side looks like.
Note to self: expose the copper under P2 in the area surrounded by capacitors, for improved heat dissipation.