... Continue recording while using heated air to produce a rising temperature. Stop when it levels out.
When doing any test, it can be useful to run a triangle sweep - ie both up and down in Voltage/Current/Temperature.
Here, you would record as it cooled as well.
That shows any hysteresis effects, and confirms the reading precision
A temperature probe will be useful to allow working back to derive a ppm/'C value, but it could be as simple as a diode range meter on a Pin-reverse diode.
As well as recording the Meter reading, the ADC on that diode pin could run, to track the temperature more automatically.
The meter values can then be used to 2 point calibrate the diode ADC channel.
Tracy, the resistors are 1kohm/sq P-plus polysilicon.
Did they state an intrinsic temperature coefficient? I've heard that it is possible to get near zero temperature at certain doping levels.
It will be a consideration if the input is a current source, such as a photodiode. You no longer have the ratio of the two polysilicon resistors, and the gain is directly affected by the character of the 300kΩ feedback resistor. Similarly if the input is driven by a non-zero output impedance of if you add an external resistive network.
Tracy, the resistors are 1kohm/sq P-plus polysilicon.
Did they state an intrinsic temperature coefficient? I've heard that it is possible to get near zero temperature at certain doping levels.
There is this general info
One source : Polysilicon Resistor
30-100 ohms/square (unshielded)
100-500 ohms/square (shielded)
Absolute accuracy = ±30%
Relative accuracy = 2% (5 µm)
Temperature coefficient = 500-1000 ppm/°C
Voltage coefficient ≈ 100ppm/V
another source
n+ polysilicon 100 ohm/sq -800ppm/°C 50ppm/V
P+ polysilicon 200 ohm/sq 200ppm/°C 50ppm/V
Likely, 1k/sq is going to be worse tempco than 200 ohm/sq.
That voltage coefficient seems to also affect the ppm/°C, as the VIO is better than GND, and the mid-point .
Matching of the tempco will also not be perfect, you might expect a ~10x matching improvement, but only when operated at the same voltage.
It will be a consideration if the input is a current source, such as a photodiode. You no longer have the ratio of the two polysilicon resistors, and the gain is directly affected by the character of the 300kΩ feedback resistor. Similarly if the input is driven by a non-zero output impedance of if you add an external resistive network.
Even the ratio will not match perfectly, and the difference will be less predictable.
You are right that Current feed like Photo-diodes will have worse tempco - users would have to choice of turning current into a voltage, or using a reference current on another ADC, to give some tracking.
Many photo diode apps use 2 or more, and you compare the results.
It will be a consideration if the input is a current source, such as a photodiode. You no longer have the ratio of the two polysilicon resistors, and the gain is directly affected by the character of the 300kΩ feedback resistor. Similarly if the input is driven by a non-zero output impedance of if you add an external resistive network.
That diagram is one I made up some days back. It's not exactly how the ADC is built. I don't think the 300kR exists at all now, it's a bunch of current amplifiers instead. Which is why Chip talked about the FETs likely being a bigger problem. Chip gave some insight a day before you turned up: https://forums.parallax.com/discussion/comment/1451855/#Comment_1451855
That diagram is one I made up some days back. It's not exactly how the ADC is built. I don't think the 300kR exists at all now, it's a bunch of current amplifiers instead. Which is why Chip talked about the FETs likely being a bigger problem. Chip gave some insight a day before you turned up: https://forums.parallax.com/discussion/comment/1451855/#Comment_1451855
What you have is still a valid model on the feedback side, because even for current sources, they are still generated from a biased resistor, so a resistor tempco is still in the mix.
I'm still curious to see the mid-point (pin open) added to the scatter plots, as that will show how good Zero tracking is, in bipolar systems.
It is possible to use a second pin, as a (some what HiZ) mid-rail reference generator, by enabling the ADC in highest gain mode, and decoupling the pin.
That does complicate things, it seems, in terms of components and interactions unseen. I'm wondering too how the magic is done. I see that the ~pF internal capacitors might demand a different approach, in order to avoid large value resistors (large in ohms and physical size). Instead, use smaller resistors to control µA level fet currents.
So, Vio/2 comes from an R/2R divider, and that determines both the feedback current and the input current proportional to Vadc - (Vio/2). Ratiometric to Vio, it would seem.
And six inverters for gain to the D latch input!
The beauty of the Prop 1 circuit with the Rs and Cs on the outside was that you could choose the parts with great flexibility even if it did mean a longer path to the silicon. Is that old posdet/negdet mode with feedback still available on the P2? The preliminary shortform data sheet mentions, "negative or positive local feedback, with or without clocking". Is that it? (Catching up!)
Is that old posdet/negdet mode with feedback still available on the P2? The preliminary shortform data sheet mentions, "negative or positive local feedback, with or without clocking". Is that it? (Catching up!)
I'm thinking doable on just the pin config for digital, %PPPPPPPPPPPPP = %0_VVV_CIO_HHHLLL (Digital mode) = %0_010_110_000000
%VVV = 010: IN = PinB logic, PinA output from IN
%C = clocked I/O (extra clock for IN and OUT)
%I = invert IN output, %O = invert OUT input
%HHH/LLL = digital out drive strength = %000: Fast
With external R-C circuit, this pin config should feed smartpin mode %01111 just the same as the internal ADC does.
PS: There is also current controlled drive options that would be worth trying out in place of the feedback resister.
PPS: %0_010_101_000000 might work too and should produce correct polarity bitstream. The alternative is invert the bitstream polarity at the smartpin input.
Then, bring your analog signal into the pin via a 200k resistor. The pin's IN signal will output the delta-sigma bit stream. You can use the smart pin circuit to tally up the ones.
Then, bring your analog signal into the pin via a 200k resistor. The pin's IN signal will output the delta-sigma bit stream. You can use the smart pin circuit to tally up the ones.
That still has the tempco and variance of the internal 150k, which is not great (but does give a single pin ADC).
I think you can get CMOS drive, sense from an adjacent pin, and use 2 external resistors ? (so now is the same as P1)
In this case, the clocked feedback is always at SysCLK only, right ?
An external D-FF allows any clock, but needs a pin for that clock (can be shared to other D-FF). The external D-FF allows total Analog supply isolation, and should give 20+ bits with an external opamp/integrator.
Then, bring your analog signal into the pin via a 200k resistor. The pin's IN signal will output the delta-sigma bit stream. You can use the smart pin circuit to tally up the ones.
That still has the tempco and variance of the internal 150k, which is not great (but does give a single pin ADC).
I think you can get CMOS drive, sense from an adjacent pin, and use 2 external resistors ? (so now is the same as P1)
In this case, the clocked feedback is always at SysCLK only, right ?
An external D-FF allows any clock, but needs a pin for that clock (can be shared to other D-FF). The external D-FF allows total Analog supply isolation, and should give 20+ bits with an external opamp/integrator.
Yes, you can use two pins - one to sense and one to output.
Is it such a simple thing to make an external 20-bit ADC? That's neat.
Is it such a simple thing to make an external 20-bit ADC? That's neat.
I've seen it done, yes, but I'm not sure I'd call it 'simple'...
You need a very good reference, and that powers the D-FF, and a low-noise opamp, plus some means to get 50.000% of Vcc, and then some good analog instrumentation amp ahead of all this...
It's certainly worth testing the P2 in this 2-pin analog mode, (using internal D-FF) to see how the Pin-buffer behaves.
Here's a quick test of voltage seen at floating pin P9 or P8 during that 60~75 sec startup window, before the chip goes to sleep.
There's no code loaded, the pin is floating and not used during the boot operations. I don't think it has a role in jtag but I may be wrong on this.
The potential moves around a bit because of the large impedance of the meter in High Z mode - datasheet says over 10 Gigohm.
As you can see the average is over 1.65v threshold. This is despite the meter being connected from pin to ground, so whatever the high input impedance of the meter is, it would be tugging the pin to ground if anything.
Here's a quick test of voltage seen at floating pin P9 or P8 during that 60~75 sec startup window, before the chip goes to sleep.
There's no code loaded, the pin is floating and not used during the boot operations. I don't think it has a role in jtag but I may be wrong on this.
The potential moves around a bit because of the large impedance of the meter in High Z mode - datasheet says over 10 Gigohm.
As you can see the average is over 1.65v threshold. This is despite the meter being connected from pin to ground, so whatever the high input impedance of the meter is, it would be tugging the pin to ground if anything.
So, it sounds, then, like something is leaking high, ever so slightly, causing the pin to be high when floating.
I just noticed something else interesting. The multimeter can only have 10Mohm or >10Gohm input resistance. In the >10Gohm mode that pin potential seems to float up to around 2v. The 10 MOhm pulls it towards ground fairly quickly.
So I tried combining the Hi-Z (10 Gigohm) meter with an external 33 Megohm to ground, the biggest resistor I had on hand, and in this case the pin hovers around +320mv. Which tends to indicate some diode or active component action, or perhaps something ionic on the pcb?
I wonder whether what we're seeing is simply the proximity of pins to nearby positive rails, and absence of any GND pins. If thats the case we should see some pins heading for 1v8 and others heading for 3v3, right?
I guess I could have a look at P0 which is next to the grounded test pin and see if it looks any different its next to 1v8
All FETs and diodes leak, somewhat. The bigger they are, the greater their leakage. The biggest FETs and diodes on the chip are in the I/O pins. All those devices leak a little. It sounds like that is what you are seeing. The current you are seeing looks to be 9.7nA, if it's 320mV with 33M to ground. It's likely that the main PFET output and/or clamp diode are leaking 9.7nA. That's ~1/100th of a microamp.
I turned off some nearby equipment and led light and the voltage roughly halved. That indicates external factors at least partly to blame, so time to move on to other measurements. Sorry for the diversion
doesn't seem to be a pattern with regard to neighbors
doesn't seem to be a pattern with which pins are used for jtag...
Every I/O has the same PFET and reversed diodes to VIO. There is a lot of opportunity for leakage in those structures. You might see something different on RESn, XI, and XO. They may even leak more, since their PFETs have many dummy fingers for ESD protection, whereas the I/O pins have diode clamps for ESD protection.
I just finished simulating the current ADC and a biased-up version which I figured might yield better resolution.
Results of the simulations were quite indeterminate. I ran each version for two stretches of 15,000 samples and compared the sample sets. In neither case was the error even one count between sets. So, no progress was made in determining what might improve the ADC performance.
I think our ADC limitations have everything to do with 1/f, or flicker, noise. It's low frequency and can't be filtered out. It's a part of reality that we can't be completely rid of. I'm trying to figure out how to handle it best.
I redid the simulations in "accurate" mode which added in some noise, I believe, but am not sure about.
So, the current design simulated with 182ppm difference between two consecutive 15,000-sample sets.
The biased-up version simulated with 131ppm difference. That's a little better, but such a change would drop the ADC input impedance from ~540k to ~135k. Not really worth it.
I think the ADC design that we already have is a decent balance of compromises. It might be good to tweak two FET dimensions to achieve 1/8th and 7/8th duty cycle at GND and VIO, instead of the current ~1/6th and ~5/6th, but I don't have any greater ideas for improving it. It's hard to get a handle on what's even limiting it.
Hello Chip, as I mentioned before: the propeller is not an ADC nor a DAC nor whatever. It is just a well balanced arrangement of brilliant ideas. So don't care to much.
The advantage of the propeller implementation of an sigma delta like adc is, that all strategies possible to reduce noise can be implemented using a cog. There is a huge field to do some search and even re-search, as we will find what others know or take for given. It will turn out: if the application requires state of the art ADC, a state of the art ADC should be attached. Such an ADC might be more expensive than the prop, and there is a reason.
Let's be real, if you want a high bit, low noise, instrumentation amplifier, you're going to use a purpose built unit. (I use amplifier, but it's basically the same thing). A low noise design will have special considerations given to power supply, heat, and routing.
Reading 10 bits accurately is still way ahead of anything that a MCU will really need. The current state of the art in video is 10bit HDR.
Yeah, 10 bits is still only 1024 steps, but that's still a lot for most things.
Reading a joystick doesn't need that.
Digitizing a video signal is probably just right at 10bit.
You've got 10-12bits of good ADC, sounds fine to me and not worth losing sleep over (I KNOW you are losing sleep over it!)
Comments
When doing any test, it can be useful to run a triangle sweep - ie both up and down in Voltage/Current/Temperature.
Here, you would record as it cooled as well.
That shows any hysteresis effects, and confirms the reading precision
A temperature probe will be useful to allow working back to derive a ppm/'C value, but it could be as simple as a diode range meter on a Pin-reverse diode.
As well as recording the Meter reading, the ADC on that diode pin could run, to track the temperature more automatically.
The meter values can then be used to 2 point calibrate the diode ADC channel.
Did they state an intrinsic temperature coefficient? I've heard that it is possible to get near zero temperature at certain doping levels.
It will be a consideration if the input is a current source, such as a photodiode. You no longer have the ratio of the two polysilicon resistors, and the gain is directly affected by the character of the 300kΩ feedback resistor. Similarly if the input is driven by a non-zero output impedance of if you add an external resistive network.
There is this general info
One source :
Polysilicon Resistor
30-100 ohms/square (unshielded)
100-500 ohms/square (shielded)
Absolute accuracy = ±30%
Relative accuracy = 2% (5 µm)
Temperature coefficient = 500-1000 ppm/°C
Voltage coefficient ≈ 100ppm/V
another source
n+ polysilicon 100 ohm/sq -800ppm/°C 50ppm/V
P+ polysilicon 200 ohm/sq 200ppm/°C 50ppm/V
Likely, 1k/sq is going to be worse tempco than 200 ohm/sq.
That voltage coefficient seems to also affect the ppm/°C, as the VIO is better than GND, and the mid-point .
Matching of the tempco will also not be perfect, you might expect a ~10x matching improvement, but only when operated at the same voltage.
Even the ratio will not match perfectly, and the difference will be less predictable.
You are right that Current feed like Photo-diodes will have worse tempco - users would have to choice of turning current into a voltage, or using a reference current on another ADC, to give some tracking.
Many photo diode apps use 2 or more, and you compare the results.
That diagram is one I made up some days back. It's not exactly how the ADC is built. I don't think the 300kR exists at all now, it's a bunch of current amplifiers instead. Which is why Chip talked about the FETs likely being a bigger problem. Chip gave some insight a day before you turned up: https://forums.parallax.com/discussion/comment/1451855/#Comment_1451855
I'm still curious to see the mid-point (pin open) added to the scatter plots, as that will show how good Zero tracking is, in bipolar systems.
It is possible to use a second pin, as a (some what HiZ) mid-rail reference generator, by enabling the ADC in highest gain mode, and decoupling the pin.
So, Vio/2 comes from an R/2R divider, and that determines both the feedback current and the input current proportional to Vadc - (Vio/2). Ratiometric to Vio, it would seem.
And six inverters for gain to the D latch input!
The beauty of the Prop 1 circuit with the Rs and Cs on the outside was that you could choose the parts with great flexibility even if it did mean a longer path to the silicon. Is that old posdet/negdet mode with feedback still available on the P2? The preliminary shortform data sheet mentions, "negative or positive local feedback, with or without clocking". Is that it? (Catching up!)
I'm thinking doable on just the pin config for digital, %PPPPPPPPPPPPP = %0_VVV_CIO_HHHLLL (Digital mode) = %0_010_110_000000
%VVV = 010: IN = PinB logic, PinA output from IN
%C = clocked I/O (extra clock for IN and OUT)
%I = invert IN output, %O = invert OUT input
%HHH/LLL = digital out drive strength = %000: Fast
With external R-C circuit, this pin config should feed smartpin mode %01111 just the same as the internal ADC does.
PS: There is also current controlled drive options that would be worth trying out in place of the feedback resister.
PPS: %0_010_101_000000 might work too and should produce correct polarity bitstream. The alternative is invert the bitstream polarity at the smartpin input.
Then, bring your analog signal into the pin via a 200k resistor. The pin's IN signal will output the delta-sigma bit stream. You can use the smart pin circuit to tally up the ones.
That still has the tempco and variance of the internal 150k, which is not great (but does give a single pin ADC).
I think you can get CMOS drive, sense from an adjacent pin, and use 2 external resistors ? (so now is the same as P1)
In this case, the clocked feedback is always at SysCLK only, right ?
An external D-FF allows any clock, but needs a pin for that clock (can be shared to other D-FF). The external D-FF allows total Analog supply isolation, and should give 20+ bits with an external opamp/integrator.
Yes, you can use two pins - one to sense and one to output.
Is it such a simple thing to make an external 20-bit ADC? That's neat.
I've seen it done, yes, but I'm not sure I'd call it 'simple'...
You need a very good reference, and that powers the D-FF, and a low-noise opamp, plus some means to get 50.000% of Vcc, and then some good analog instrumentation amp ahead of all this...
It's certainly worth testing the P2 in this 2-pin analog mode, (using internal D-FF) to see how the Pin-buffer behaves.
There's no code loaded, the pin is floating and not used during the boot operations. I don't think it has a role in jtag but I may be wrong on this.
The potential moves around a bit because of the large impedance of the meter in High Z mode - datasheet says over 10 Gigohm.
As you can see the average is over 1.65v threshold. This is despite the meter being connected from pin to ground, so whatever the high input impedance of the meter is, it would be tugging the pin to ground if anything.
So, it sounds, then, like something is leaking high, ever so slightly, causing the pin to be high when floating.
So I tried combining the Hi-Z (10 Gigohm) meter with an external 33 Megohm to ground, the biggest resistor I had on hand, and in this case the pin hovers around +320mv. Which tends to indicate some diode or active component action, or perhaps something ionic on the pcb?
I wonder whether what we're seeing is simply the proximity of pins to nearby positive rails, and absence of any GND pins. If thats the case we should see some pins heading for 1v8 and others heading for 3v3, right?
I guess I could have a look at P0 which is next to the grounded test pin and see if it looks any different its next to 1v8
P0 tends toward 344mV (neighbor: 1v8)
P1 tends toward 337mV (neighbor: 3v3)
P2 tends toward 329mV (neighbor: 3v3)
P3 tends toward 343mV (neighbor: 1v8)
P4 tends toward 368mV (neighbor: 1v8)
P5 tends toward 320mV (neighbor: 3v3)
P6 tends toward 350mV (neighbor: 3v3)
P7 tends toward 304mV (neighbor: 1v8)
P8 tends toward 308mV (neighbor: 1v8)
P9 tends toward 289mV (neighbor: 3v3)
doesn't seem to be a pattern with regard to neighbors
doesn't seem to be a pattern with which pins are used for jtag...
Every I/O has the same PFET and reversed diodes to VIO. There is a lot of opportunity for leakage in those structures. You might see something different on RESn, XI, and XO. They may even leak more, since their PFETs have many dummy fingers for ESD protection, whereas the I/O pins have diode clamps for ESD protection.
I believe the FPGA showed the same
This all probably doesn't matter. Also we have 150 k ohm pulldown option.
Results of the simulations were quite indeterminate. I ran each version for two stretches of 15,000 samples and compared the sample sets. In neither case was the error even one count between sets. So, no progress was made in determining what might improve the ADC performance.
I need to see about simulating with 1/f noise. Not clear on how to go about that.
So, the current design simulated with 182ppm difference between two consecutive 15,000-sample sets.
The biased-up version simulated with 131ppm difference. That's a little better, but such a change would drop the ADC input impedance from ~540k to ~135k. Not really worth it.
I think the ADC design that we already have is a decent balance of compromises. It might be good to tweak two FET dimensions to achieve 1/8th and 7/8th duty cycle at GND and VIO, instead of the current ~1/6th and ~5/6th, but I don't have any greater ideas for improving it. It's hard to get a handle on what's even limiting it.
https://www.maximintegrated.com/en/app-notes/index.mvp/id/5384
The digital filter sounds like something can do in the cog.
But, how do you add noise shaping?
Reading 10 bits accurately is still way ahead of anything that a MCU will really need. The current state of the art in video is 10bit HDR.
Yeah, 10 bits is still only 1024 steps, but that's still a lot for most things.
Reading a joystick doesn't need that.
Digitizing a video signal is probably just right at 10bit.
You've got 10-12bits of good ADC, sounds fine to me and not worth losing sleep over (I KNOW you are losing sleep over it!)