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Propeller II: Emulation of the P2 on FPGA boards (Prop123-A7/A9, DE0-NANO, DE2-115, etc)



  • Hi Chip

    With the advent of bga package culture, there seems to be some misconcern about what happens underneath chip packages.

    Also Cmos logic have been long ago mentally associated with low power levels, hence lower dissipation. The farther many could think, is providing some top-bonded heat sink, to help spread high power levels.

    But limits have been pushed and we need to understand the present reality, almost doing a rescue of technics that have been of common use, from decades, mainly in the bipolar realm.

    Bottom exposed pad qfns and qfps does present some chalenges that, when properly addressed, let us fully realize the benefits of simultaneous electrical and thermal conduction thru a single element.

    Working with P2 have been, and sure will be, an entire electronics classroom by itself.
  • Yes, Enrique, I agree. OnSemi was interested to know what our recommended PCB design will be like, in terms of exposed-pad vias, ground planes, and dimensions. They intend to do a thorough heat dissipation analysis to make sure the chip works as intended in the likely setting.
  • YanomaniYanomani Posts: 519
    edited October 2017 Vote Up0Vote Down
    Hi Chip

    Maybe one of their concerns is the fact that P2 die area will closely match the maximum space available in the chosen package, hence it's using almost all the available exposed pad area.
    This implies that any gain in heat dissipation will be totally dependent of the design of the landing area underneath the chip.
    The three references I've posted earlier show how heat flow develops laterally, from the land pattern soldering area and its thermal vias, to any connected metal plane inside the multilayer board sandwich.
    The next one I'm just posting here, has an impressive image (page 15) of a cutoff made into a multilayer board, showing why removing extra metal surfaces inside the sandwich can lead to changes in the final PCB thickness, affecting its flatness and hence leaving an almost unnoticed very poor solder/contact interface, just under the chip.
    Please note that the same will apply to the vicinity of the heavily populated metal area, represented by the whole tqfp land pattern, in the several stacked planes.
    IMHO, judicious design of the whole chip setup, including the nearest smt components, can and will greatly influence the final result.

    Hope it helps



    Another great resource from Ti, for the ones that simply love to do some math calculations. :lol:
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