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Propeller II: Emulation of the P2 on FPGA boards (Prop123-A7/A9, DE0-NANO, DE2-115, etc)

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  • Hi Chip

    With the advent of bga package culture, there seems to be some misconcern about what happens underneath chip packages.

    Also Cmos logic have been long ago mentally associated with low power levels, hence lower dissipation. The farther many could think, is providing some top-bonded heat sink, to help spread high power levels.

    But limits have been pushed and we need to understand the present reality, almost doing a rescue of technics that have been of common use, from decades, mainly in the bipolar realm.

    Bottom exposed pad qfns and qfps does present some chalenges that, when properly addressed, let us fully realize the benefits of simultaneous electrical and thermal conduction thru a single element.

    Working with P2 have been, and sure will be, an entire electronics classroom by itself.
  • Yes, Enrique, I agree. OnSemi was interested to know what our recommended PCB design will be like, in terms of exposed-pad vias, ground planes, and dimensions. They intend to do a thorough heat dissipation analysis to make sure the chip works as intended in the likely setting.
  • YanomaniYanomani Posts: 563
    edited October 2017 Vote Up0Vote Down
    Hi Chip

    Maybe one of their concerns is the fact that P2 die area will closely match the maximum space available in the chosen package, hence it's using almost all the available exposed pad area.
    This implies that any gain in heat dissipation will be totally dependent of the design of the landing area underneath the chip.
    The three references I've posted earlier show how heat flow develops laterally, from the land pattern soldering area and its thermal vias, to any connected metal plane inside the multilayer board sandwich.
    The next one I'm just posting here, has an impressive image (page 15) of a cutoff made into a multilayer board, showing why removing extra metal surfaces inside the sandwich can lead to changes in the final PCB thickness, affecting its flatness and hence leaving an almost unnoticed very poor solder/contact interface, just under the chip.
    Please note that the same will apply to the vicinity of the heavily populated metal area, represented by the whole tqfp land pattern, in the several stacked planes.
    IMHO, judicious design of the whole chip setup, including the nearest smt components, can and will greatly influence the final result.

    Hope it helps

    Henrique

    https://smta.org/chapters/files/Heartland_Heartland_May_2015_BTC_DaleLee.pdf

    P.S.

    Another great resource from Ti, for the ones that simply love to do some math calculations. :lol:

    ti.com/lit/an/snva419c/snva419c.pdf
  • Would it be possible to run the P2 on the new Arduino Vidor 4000? It has a Cyclone 10 LP 10CL016 (16000 LE)
  • evanhevanh Posts: 5,105
    The FPGA used for emulating an 8 Cog Prop2 is a Cyclone V -A9 which has 300,000 LE. And is substantially used.

    "Are we alone in the universe?"
    "Yes," said the Oracle.
    "So there's no other life out there?"
    "There is. They're alone too."
  • evanhevanh Posts: 5,105
    edited June 4 Vote Up0Vote Down
    Actually, it can hold 16 Cogs but doesn't fit every thing else then. One Cog is maybe 13000 LE.

    "Are we alone in the universe?"
    "Yes," said the Oracle.
    "So there's no other life out there?"
    "There is. They're alone too."
  • 1 cog would be enough to start learning P2 ASM and Taqoz. With Arduino reputation, I expect that there will be much more owner than the DE0 nano
  • jmgjmg Posts: 11,660
    FredBlais wrote: »
    1 cog would be enough to start learning P2 ASM and Taqoz. With Arduino reputation, I expect that there will be much more owner than the DE0 nano

    Do you mean until P2 silicon arrives ? P2 Eval Boards would expect to be lower cost than an Arduino Vidor 4000, with more cores & more MHz & more RAM & all the analog. (so that 's not a wide time window.)

    I could see interest in P1V's on that platform - not sure if anyone has the MHz figures for a compile to Cyclone 10 LP 10CL016 ?
  • In fact, porting to the Vidor 4000 could be used as a marketing strategy : As I understand it, the FPGA hardware peripherals will be hosted on Arduino Create (web hosted IDE) a bit like objects in the OBEX. If we showcase the single core P2 there, we could gather some more interest towards the upcoming chip. Especially when the Vidor will be released this month there shouldn’t be a lot of others IP core to try so there’s no better timing than doing it ASAP. At least it’s worth the try...
  • evanhevanh Posts: 5,105
    edited June 4 Vote Up0Vote Down
    It's somewhere around 1500-1800 LE per Smartpin, so at best, only room for one Cog plus two Smartpins. That's not enough Smartpins at all. :(

    EDIT: DE-Nano has about 22000 LE and can only manage 8 Smartpins. See https://forums.parallax.com/discussion/162298/prop2-fpga-files-updated-2-june-2018-final-version-32i

    Doing a rough calc of the Nano it wouldn't fit with my above sizes. So 11000 per Cog and 1400 per Smartpin fits better.

    That would allow 3 Smartpins in the Vidor 4000. Still unusable.

    "Are we alone in the universe?"
    "Yes," said the Oracle.
    "So there's no other life out there?"
    "There is. They're alone too."
  • jmgjmg Posts: 11,660
    evanh wrote: »
    It's somewhere around 1500-1800 LE per Smartpin, so at best, only room for one Cog plus two Smartpins. That's not enough Smartpins at all. :(

    Valid point, what about a P1V and more smart pins then ?

    There seems good progress on compilers/spin that can run on both P1 and P2, so the focus here could be examples of Smart Pin use, where the code can compile for either a real P2, or the 'Vidor 4000 P2-'

    The Smart pins are a key point of difference of P2 (aside from the Analog, which no FPGA can emulate anyway)

    An unknown question here is how quickly will Vidor 4000 ramp ? As 'not yet released', it could have some shake-out passes to go yet ?
  • FredBlais wrote: »
    In fact, porting to the Vidor 4000 could be used as a marketing strategy : As I understand it, the FPGA hardware peripherals will be hosted on Arduino Create (web hosted IDE) a bit like objects in the OBEX. If we showcase the single core P2 there, we could gather some more interest towards the upcoming chip. Especially when the Vidor will be released this month there shouldn’t be a lot of others IP core to try so there’s no better timing than doing it ASAP. At least it’s worth the try...

    As a marketing strategy, this might make some sense Fred. You'd need to convince Chip to compile for a different family, and Chip's probably thinking his compiling days are finally over... and 16k is a fair bit less than the 22k~25k for current small fpga targets (no cordic)

    My conclusion on the Cyclone 10 LP was it was 'underwhelming' - similar MHz figures on P1V to Max10, but no flash onboard, and an $18 external configuration prom. The lattice parts are much more attractive for their size as Ariba points out. See this thread for all the details

    https://forums.parallax.com/discussion/166073/cyclone-10-early-info/p1
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