Any news to the status of pfth for the P2. I would like to see the assembly words optimized for the P2, i.e using the cog hardware/multiply and the better branching instructions, etc ..
Can it still run on the DE0, or do I have to buy a bigger FPGA eval board ...
Also, the original post in this thread seems very dated, I have no idea what is current any more ...
So nothing to do but wait ........................................... again
Guess my playing with pfth on P2 on FPGA on some cheap hardware is not on yet then ... (DE0-NANO at the limit, can't aford the other one, like most ..)
Dang!
================================================================================ Info for the new P2 FPGA (Sept 2015 onwards) - after the P2-HOT follows.....
================================================================================
Cluso,
A bit of clarity on what topics are Prop2Hot and what are post-Prop2Hot: The Prop2Hot that went to shuttle run at On-Semi and failed badly I believe was 8 Cog, 128kB HubRAM design. It had the massive DAC bus that allowed every Cog fast analogue out on every pin.
The pimped up Prop2Hot ditched that massive bus and gained double the HubRAM (256kB) plus lots more instructions and of course that's when HubExec was introduced.
The 16 Cog, 512kB version has always been post-Prop2Hot, ie: The basis of the current version.
IIRC the P2-Hot came after the failed OnSemi silicon.
It was an 8 Cog, 128KB Hub, 1 clock instructions, multithreaded.
The post P2-Hot is the 16 Cog, 512KB Hub, 2 clock instructions.
Here's my opinion:
It's rated power was only tested for and identified at the very end - just before aborting it - but, and still just my opinion, it was always a hot design all along. That goes to the very heart of why Chip was so quick to start over.
I remember it took a while for quite a few of the people following to accept the significant and sudden course change. There was real bewilderment, and I think some here are still smarting from the expectations of delivery time being so drastically squashed.
Anyway, what I was intending to highlight was that a bunch of the post-Prop2Hot links and descriptions have been placed in with the Prop2Hot below the bright red P2-HOT banner in your OP.
Bewilderment... Oh yeah! I totally remember thinking, WTF? Seriously? No way!
Can't be happening.
The works!
Then there were all the discussions... It's still awesome at 4 COGS. Or, we can just run it slow. Somebody said they would just heat sink it and carry on too.
Well, here we are, and this one looks really good. Fingers crossed.
I thought someone posted a P2 pin mapping for the peripherals on the 1-2-3 A9 board, but nothing is showing up in the search. Does anyone know where it is?
As many have discovered it can be an exercise to get the latest Quartus Lite via their download page. So I've gathered up all the direct download links for Windoze and Linux:
PS: The Linux version is intended for RedHat but I've found it's perfectly fine on Ubuntu with one caveat (Probably applies to newer RedHat's as well) - It has an explicit version dependency on an old version of libpng.so, namely version 1.2. Ubuntu no longer supports such an old version of this library. It can be found as a package but, due to compatibility flags, you have to manually extract the specific library file yourself and it's best placed with Quartus's own library files. I've also built from source and done the same. It's not too hard with a ./configure followed by make then copy the resulting libpng12.so.0 soft-link and it's related binary into Quartus's libs directory - Which can be found at {Install Directory}/quartus/linux64/
Rayman, what happened in April 2014? It's been so long I've forgotten. Was that when the test chip was DOA, or was it when the power issue was discovered with P2-Hot?
I believe things are in much better shape now. The analog test chip was a success, and the new P2 design is almost done. I'm hoping the latest changes for the Spin interpreter are done, and the design can be frozen. It would be good to get some power estimates for the current design to ensure that the chip won't run into power issues this time.
I see it in much the same way Dave. These aren't pile on changes. Just more fully exploiting what is there.
This time around Chip did get safe design rules from OnSemi.
The core of SPIN is nearly complete too. I doubt many more tweaks are necessary.
That power budget... fingers crossed! To me, that's the big question mark. Should be OK though. Early on in this design, constraints were identified and used to avoid a hot chip.
The other fingers crossed item for me is the actual synthesis. I wonder if it's possible to run that somehow, even slow. Probably not. There are subtle potential errors and glitches possible.
.... It would be good to get some power estimates for the current design to ensure that the chip won't run into power issues this time.
and some RAM Size numbers....
That has been pretty much left till last on a 'RAM takes what is left' basis, but it may transpire that the Logic enhancements have reduced the amount of RAM that P2 can have ?
On the Topic of MCU RAM, there was this news....
Unlikely to run out of die space. Chip has kept an eye on that all along ... and even threw in dual-porting of LUTRAM because of his confidence in space left over. There was discussion on what to do with the excess beforehand. Smartpins got a rework as a result of that too I think.
It was statements like that that solidly put Billy in the dunce bin early on. It told me he didn't code and was just another mumbo jumbo marketer.
Functionally, even in the 1980's it was a no-brainer that, at least, megabytes was desirable. Also from an economics perspective back then, RAM was valuable for a reason - demand was insatiable!
Yes, it's too bad about Billy. If he would have only finished college he'd probably would have made something of himself. Look at how he ended up -- just sitting around the house all day trying to figure out what to do with his $86 billion.
Yes, it's too bad about Billy. If he would have only finished college he'd probably would have made something of himself. Look at how he ended up -- just sitting around the house all day trying to figure out what to do with his $86 billion.
Yes, I am delighted to not have that problem... not! Hehe
Comments
Please keep this thread to discussions about getting the FPGA code running (as per the first post).
Any news to the status of pfth for the P2. I would like to see the assembly words optimized for the P2, i.e using the cog hardware/multiply and the better branching instructions, etc ..
Can it still run on the DE0, or do I have to buy a bigger FPGA eval board ...
Also, the original post in this thread seems very dated, I have no idea what is current any more ...
Cheers,
Bernie
The P2's in this thread do run and are fun to play with but are nothing like the "real" P2.
Guess my playing with pfth on P2 on FPGA on some cheap hardware is not on yet then ... (DE0-NANO at the limit, can't aford the other one, like most ..)
Dang!
================================================================================
Info for the new P2 FPGA (Sept 2015 onwards) - after the P2-HOT follows.....
================================================================================
A bit of clarity on what topics are Prop2Hot and what are post-Prop2Hot: The Prop2Hot that went to shuttle run at On-Semi and failed badly I believe was 8 Cog, 128kB HubRAM design. It had the massive DAC bus that allowed every Cog fast analogue out on every pin.
The pimped up Prop2Hot ditched that massive bus and gained double the HubRAM (256kB) plus lots more instructions and of course that's when HubExec was introduced.
The 16 Cog, 512kB version has always been post-Prop2Hot, ie: The basis of the current version.
It was an 8 Cog, 128KB Hub, 1 clock instructions, multithreaded.
The post P2-Hot is the 16 Cog, 512KB Hub, 2 clock instructions.
It's rated power was only tested for and identified at the very end - just before aborting it - but, and still just my opinion, it was always a hot design all along. That goes to the very heart of why Chip was so quick to start over.
I remember it took a while for quite a few of the people following to accept the significant and sudden course change. There was real bewilderment, and I think some here are still smarting from the expectations of delivery time being so drastically squashed.
Can't be happening.
The works!
Then there were all the discussions... It's still awesome at 4 COGS. Or, we can just run it slow. Somebody said they would just heat sink it and carry on too.
Well, here we are, and this one looks really good. Fingers crossed.
'( 25Q80 8Mb SPI FLASH )
spi_cs = 61
spi_ck = 60
spi_di = 59
spi_do = 58
as these are the ones I found in ROM_Booter.spin
I'm actually interfacing to this now along with the SD card and my FAT32 filesystem.
Make sure USB-Blaster is selected in the Hardware Setup field!
Someone asked about P1V, I asked about a pin map and Chip posted it.
I haven't circled back since....we can blame my day job for that!
The original Nov 2006 question - http://forums.parallax.com/discussion/90019/what-would-you-want-more-of-cogs-or-ram/p1
Beau's fantastically long lived Sept 2010 Propeller II update - http://forums.parallax.com/discussion/125543/propeller-ii-update-blog/p1
The rather shocking April 2014 news - http://forums.parallax.com/discussion/155014/we-re-looking-at-5-watts-in-a-bga/p1
And it's rebirth - http://forums.parallax.com/discussion/155132/the-new-16-cog-512kb-64-analog-i-o-propeller-chip/p1 and http://forums.parallax.com/discussion/162069/the-new-16-cog-512kb-64-analog-i-o-propeller-chip-part-2/p1
For fresh Windoze install use this - http://download.altera.com/akdlm/software/acdsinst/16.1.2/203/ib_tar/Quartus-lite-16.1.2.203-windows.tar
To update an existing install use this - http://download.altera.com/akdlm/software/acdsinst/16.1.2/203/update/QuartusSetup-16.1.2.203-windows.exe
For fresh Linux install use this - http://download.altera.com/akdlm/software/acdsinst/16.1.2/203/ib_tar/Quartus-lite-16.1.2.203-linux.tar
To update an existing install use this - http://download.altera.com/akdlm/software/acdsinst/16.1.2/203/update/QuartusSetup-16.1.2.203-linux.run
The above is obviously the current release but it's pretty easy to derive and edit the URL appropriately for newer version numbers. For example a previous release was http://download.altera.com/akdlm/software/acdsinst/16.1.1/200/ib_tar/Quartus-lite-16.1.1.200-linux.tar
As you can see both sets of numbers in this URL have the differing version number but that's all the difference is.
PS: The Linux version is intended for RedHat but I've found it's perfectly fine on Ubuntu with one caveat (Probably applies to newer RedHat's as well) - It has an explicit version dependency on an old version of libpng.so, namely version 1.2. Ubuntu no longer supports such an old version of this library. It can be found as a package but, due to compatibility flags, you have to manually extract the specific library file yourself and it's best placed with Quartus's own library files. I've also built from source and done the same. It's not too hard with a ./configure followed by make then copy the resulting libpng12.so.0 soft-link and it's related binary into Quartus's libs directory - Which can be found at {Install Directory}/quartus/linux64/
PPS: libpng12 sources are here - https://sourceforge.net/projects/libpng/files/libpng12/
I thought we were much better off this time, but seems we keep piling on to the heap...
I believe things are in much better shape now. The analog test chip was a success, and the new P2 design is almost done. I'm hoping the latest changes for the Spin interpreter are done, and the design can be frozen. It would be good to get some power estimates for the current design to ensure that the chip won't run into power issues this time.
This time around Chip did get safe design rules from OnSemi.
The core of SPIN is nearly complete too. I doubt many more tweaks are necessary.
That power budget... fingers crossed! To me, that's the big question mark. Should be OK though. Early on in this design, constraints were identified and used to avoid a hot chip.
The other fingers crossed item for me is the actual synthesis. I wonder if it's possible to run that somehow, even slow. Probably not. There are subtle potential errors and glitches possible.
and some RAM Size numbers....
That has been pretty much left till last on a 'RAM takes what is left' basis, but it may transpire that the Logic enhancements have reduced the amount of RAM that P2 can have ?
On the Topic of MCU RAM, there was this news....
NXP K28,K27 series : 150MHz 2 MB Flash 1 MB SRAM SDRAM Controller QuadSPI XIP interface
HS USB,
http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/kinetis-cortex-m-mcus/k-series-performance-m4/k2x-usb/kinetis-k28-150-mhz-2x-usb-core-voltage-bypass-2mb-flash-1mb-sram-mcus-based-on-arm-cortex-m4:K28_150
and this, similar M4F core, 200MHz with 'SPI Flash controller with 32 KB cache memory, 100 MHz code execution'
https://www.embedded-world.de/en/ausstellerprodukte/embwld17/product-9863795/numicro-m480-series-microcontroller
Rayman, I will have an FPGA update out tomorrow. I hope we can turn that frown upside down.
You mean something like 640K ? More memory than we will ever need ;-)
Functionally, even in the 1980's it was a no-brainer that, at least, megabytes was desirable. Also from an economics perspective back then, RAM was valuable for a reason - demand was insatiable!