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Propeller II: Emulation of the P2 on FPGA boards (Prop123-A7/A9, DE0-NANO, DE2-115, etc) - Page 20 — Parallax Forums

Propeller II: Emulation of the P2 on FPGA boards (Prop123-A7/A9, DE0-NANO, DE2-115, etc)

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  • Cluso99Cluso99 Posts: 18,066
    edited 2013-10-01 16:43
    I have updated the first post with a link to the new code etc posted by Chip today
    http://forums.parallax.com/showthread.php/150588-Big-update-for-DE2-115-and-DE0-Nano-users-w-add-on-boards?p=1210517&viewfull=1#post1210517

    A number of new features and fixes. WTG Chip :)
  • Cluso99Cluso99 Posts: 18,066
    edited 2013-10-02 23:07
    Just a heads up for DE0 users...
    The new code only works on the DE0 with the Prop2 Emulator board fitted.
    DE0 requires a shunt/jumper fitted to JP3 pins 3 to 5.
    Remove the SPI Flash from the socket on the Prop2 Emulator board.
    PropPlug Ground is closest to the Prop Plug white overlay.
  • AribaAriba Posts: 2,682
    edited 2013-10-03 00:01
    Cluso

    You can also use the new code without the AddOn board if you connect the PropPlug to the right pins, just go back ~6 post in this thread.

    The jumper is only needed for Video/VGA.

    I have found you can replaced the Flash with an SPI RAM chip (128 kByte) in the same socket (it fits without any changes). The RAM is not detected as a boot memory device so the monitor starts. With the right code I can then access the SPI-RAM.

    Andy
  • David BetzDavid Betz Posts: 14,511
    edited 2013-10-03 04:08
    Cluso99 wrote: »
    Remove the SPI Flash from the socket on the Prop2 Emulator board.
    Why is it necessary to remove the flash chip? I don't seem to have any problems with it inserted. Also, if you use propeller-load you can write code to the flash that will boot on reset.
  • Cluso99Cluso99 Posts: 18,066
    edited 2013-10-03 04:35
    Ariba wrote: »
    Cluso

    You can also use the new code without the AddOn board if you connect the PropPlug to the right pins, just go back ~6 post in this thread.

    The jumper is only needed for Video/VGA.

    I have found you can replaced the Flash with an SPI RAM chip (128 kByte) in the same socket (it fits without any changes). The RAM is not detected as a boot memory device so the monitor starts. With the right code I can then access the SPI-RAM.

    Andy
    Andy: I could not get the DE0 to work standalone with the new fpga code. It works fine with the old fpga code and I reverted to ensure that this was the case.

    David: I had to remove the SPI Flash to make the new code work. I didn't try it with the old code. I just tried to get the monitor to run without loading anything. The new pnut.exe does not appear to output a hex file so I cannot use p2load atm.

    I have run out of time to try Invaders - off to bed now :(
  • ozpropdevozpropdev Posts: 2,791
    edited 2013-10-03 04:50
    David Betz wrote: »
    Why is it necessary to remove the flash chip? I don't seem to have any problems with it inserted. Also, if you use propeller-load you can write code to the flash that will boot on reset.

    Hi David,
    I had to remove the flash chip to get my DE0 to work even with the older software.
    Maybe the chip already has some code in it?
    I will have to have another look at "propeller-load" again, it's been a while.
    Cheers
    Brian
  • ozpropdevozpropdev Posts: 2,791
    edited 2013-10-03 05:04
    Hi David
    Is this the "propeller-load" you mentioned above?

    CON
    
      spi_cs = 89
      spi_ck = 88
      spi_di = 87
      spi_do = 86
    
    DAT
    		org
    
    		jmp	#begin
    
    		'program starting at $000
    data000		byte	$D9,$04,$FC,$0C,$D9,$04,$FC,$0C,$D9,$02,$FC,$0C,$00,$00,$7C,$1C
    
    		'signature starting at $7E0
    data7E0		byte	long $00000001[8]
    
    
    begin		getptrb	dataptr			'point dataptr to data000
    		add	dataptr,#4
    
    ' Erase 1st $1000 bytes
    
    		call	#spi_wrena		'write enable
    
    		mov	cmd,cmd_erase		'sector erase
    		call	#spi_cmd32
    		setp	#spi_cs
    
    		call	#spi_wait		'wait for completion
    
    ' Program 1st $800 bytes
    
    :program	call	#spi_wrena		'write enable
    
    		mov	cmd,cmd_program		'page program
    		or	cmd,addr
    		call	#spi_cmd32
    
    :byte		setptra	dataptr			'point to data
    		xor	addr,#%11		'(big-endian)
    		addptra	addr
    		xor	addr,#%11
    		mov	cmd,#0			'default data is $00
    		cmp	addr,#$010	wc
    	if_c	jmp	#:rdbyte
    		cmp	addr,h7E0	wc
    	if_c	jmp	#:got
    		subptra	h7D0
    :rdbyte		rdbyte	cmd,ptra
    :got
    		mov	x,#8			'send byte
    		shl	cmd,#24
    		call	#spi_out
    
    		add	addr,#1			'page done?
    		test	addr,#$FF	wz
    	if_nz	jmp	#:byte
    
    		setp	#spi_cs			'end page program
    
    		call	#spi_wait		'wait for completion
    
    		cmp	addr,h800	wz	'another page?
    	if_nz	jmp	#:program
    
    ' Read data back to $7000
    
    		mov	cmd,cmd_read		'read
    		call	#spi_cmd32
    
    		mov	y,h800			'read byte
    		setptra	h7000
    :read		call	#spi_in
    		wrbyte	cmd,ptra++
    		djnz	y,#:read
    
    		setp	#spi_cs			'end read
    
    ' Done, run monitor so data can be verified at $7000
    
    		jmp	#monitor
    '
    '
    ' SPI write enable
    '
    spi_wrena	mov	cmd,#$06		'write enable
    		call	#spi_cmd8
    		setp	#spi_cs
    
    spi_wrena_ret	ret
    '
    '
    ' SPI wait while busy
    '
    spi_wait	mov	cmd,#$05
    		call	#spi_cmd8
    
    :wait		call	#spi_in
    		test	cmd,#$01	wc
    	if_c	jmp	#:wait
    
    		setp	#spi_cs
    
    spi_wait_ret	ret
    '
    '
    ' SPI command
    '
    spi_cmd32	mov	x,#32
    		jmp	#spi_cmd
    
    spi_cmd8	mov	x,#8
    		shl	cmd,#24
    
    spi_cmd		setp	#spi_cs
    		clrp	#spi_ck
    		clrp	#spi_cs
    '
    '
    ' SPI byte out (x = bits, cmd = msbdata)
    '
    spi_out		shl	cmd,#1		wc
    		setpc	#spi_di
    		setp	#spi_ck
    		clrp	#spi_ck
    		djnz	x,#spi_out
    spi_cmd32_ret
    spi_cmd8_ret
    spi_out_ret		ret
    '
    '
    ' SPI byte in (cmd)
    '
    spi_in		mov	x,#8
    :loop		getp	#spi_do		wc
    		setp	#spi_ck
    		clrp	#spi_ck
    		rcl	cmd,#1
    		djnz	x,#:loop
    
    spi_in_ret	ret
    '
    '
    ' Run monitor
    '
    monitor		coginit	monitor_ptr,monitor_par
    monitor_ptr	long	$70C			'monitor address
    monitor_par	long	90 << 9 + 91		'monitor parameter (tx_pin=90, rx_pin=91)
    '
    '
    ' Data
    '
    cmd_erase	long	$20_00_00_00
    cmd_program	long	$02_00_00_00
    cmd_read	long	$03_00_00_00
    addr		long	$000
    
    h7D0		long	$7D0
    h7E0		long	$7E0
    h800		long	$800
    h7000		long	$7000
    '
    '
    ' Variables
    '
    dataptr		res	1
    cmd		res	1
    x		res	1
    y		res	1
    

    Cheers
    Brian
  • David BetzDavid Betz Posts: 14,511
    edited 2013-10-03 05:46
    Cluso99 wrote: »
    Andy: I could not get the DE0 to work standalone with the new fpga code. It works fine with the old fpga code and I reverted to ensure that this was the case.

    David: I had to remove the SPI Flash to make the new code work. I didn't try it with the old code. I just tried to get the monitor to run without loading anything. The new pnut.exe does not appear to output a hex file so I cannot use p2load atm.

    I have run out of time to try Invaders - off to bed now :(
    I don't think I ever added the ability to write to the flash to p2load. I think you have to use propeller-load. I can add it to p2load as well if there is a need.
  • Cluso99Cluso99 Posts: 18,066
    edited 2013-10-03 16:19
    Andy: Just re-read your post. Now I think I understand why I could not get the standalone board to work with the latest fgpa code.
    The Propplug pins have moved for this fpga version. You need to use the connections in Andy's post #568 above. I have not tried this.
    Thanks Andy.
  • SeairthSeairth Posts: 2,474
    edited 2013-12-25 07:34
    My DE0-Nano is finally ordered! Now, where do I get the beakout board?
  • ctwardellctwardell Posts: 1,716
    edited 2013-12-25 08:11
    Seairth wrote: »
    My DE0-Nano is finally ordered! Now, where do I get the beakout board?

    Send Chip a PM, make sure you specify it is for the Nano.

    C.W.
  • TorTor Posts: 2,010
    edited 2013-12-25 10:26
    I'm considering breaking down and buy a DE0-Nano myself, but I thought there was just that batch of breakout boards initially and that was it? Can we use the Nano for anything P2 as-is? There's been so much written that I'm now uncertain about what's needed.

    -Tor
  • ozpropdevozpropdev Posts: 2,791
    edited 2013-12-25 17:31
    The DE0-Nano and DE2-115 boards can be used without the breakout boards but you won't have Video support.
    Nano will support 1 Cog + 32k Hub Ram. Lots can be learned on how the instructions work using the ROM monitor.
    Take a look a t Cluso's LMM debugger too. :)

    Edit: Without the breakout board you may have to use an earlier version of the P2 FPGA core/code. I believe the
    later versions only support comms through the breakout boards. Maybe Chip can build 2 versions for
    with/without breakout boards...or Parallax does another run of breakout boards.
  • David BetzDavid Betz Posts: 14,511
    edited 2013-12-25 18:04
    ozpropdev wrote: »
    The DE0-Nano and DE2-115 boards can be used without the breakout boards but you won't have Video support.
    Nano will support 1 Cog + 32k Hub Ram. Lots can be learned on how the instructions work using the ROM monitor.
    Take a look a t Cluso's LMM debugger too. :)

    Edit: Without the breakout board you may have to use an earlier version of the P2 FPGA core/code. I believe the
    later versions only support comms through the breakout boards. Maybe Chip can build 2 versions for
    with/without breakout boards...or Parallax does another run of breakout boards.
    Do we know yet whether the next version of the P2 will fit in the DE0-Nano? Will the cache logic fit?
  • ozpropdevozpropdev Posts: 2,791
    edited 2013-12-25 18:32
    David Betz wrote: »
    Do we know yet whether the next version of the P2 will fit in the DE0-Nano? Will the cache logic fit?

    Good point David, We'll have to see what Chip finds when he tries to compile the latest version.
    Maybe chopping a couple of K of the top of HUB will squeeze it in?
  • ctwardellctwardell Posts: 1,716
    edited 2013-12-26 10:53
    I think Chip mentioned leaving out one of the counters makes it fit.

    C.W.
  • SeairthSeairth Posts: 2,474
    edited 2013-12-26 12:15
    Yeah, but that comment was made before these latest round of changes were made. He could also leave out Port D and the inter-prop exchange stuff. Crossing fingers...
  • StefanL38StefanL38 Posts: 2,292
    edited 2014-01-03 16:56
    Hi,

    I'm just curious if there are any estimated times of year (spring,summer etc. when the P2 will be purchasable?

    best regards
    Stefan
  • msrobotsmsrobots Posts: 3,701
    edited 2014-01-03 17:30
    End of summer probably. Not sure what year... hopefully the actual one ...

    Enjoy!

    Mike
  • mindrobotsmindrobots Posts: 6,506
    edited 2014-01-12 08:38
    Yay! My Nano is back among the living in the modern P2 world. I just reloaded (thrilled I remembered the process) with the 2013_11_27 P2 image. It's all nestled happily in it's expansion carrier waiting for my commands. I haven't tested any of the video programs yet - I don't have a jumper or a monitor handy.

    I feel like I have a lot of catching up to do - I lost a year someplace along the line in 2013. Now, we just need the latest and greatest emulation to let the fun begin!!!

    (*I'm still going to have to work my Nano into a robot implementation so I don't break my New Year's resolution)
  • __red____red__ Posts: 470
    edited 2014-01-12 18:39
    So, on the subject of FPGA boards, Ken expressed a want to get to 1000 FPGA boards in the wild before P2 silicon was set.

    I know at one point there was talk of a customer FPGA board and of looking at boards other than the nano... If I wish to jump aboard, should I stay in a holding pattern and wait for some announcement or grab a nano and attempt to work through some of the older images?

    Thanks,



    Red
  • jmgjmg Posts: 15,140
    edited 2014-01-12 19:15
    I would pause at least until Chip completes the latest round.
    There has been talk of the newest built not fitting into a Nano, so I would not rush that.
    It may be a build targeting size over speed could still fit - need to wait an see.

    There is also a BEMICRO CV board, showing back in stock at Verical 920 pcs for $43.70, and that is a slightly larger and newer Cyclone V FPGA.

    Current builds are for Cyclone IV, but Cyclone V will come sometime, as Parallax are looking at their own Cyclone V version.
    Whatever Parallax do, will match up SDRAM and Cyclone V, so it is likely to be the best testing combination.

    I'd consider a BEMICRO CV cheap enough, that you could depreciate it $10/month and use one until parallax are ready.
  • Cluso99Cluso99 Posts: 18,066
    edited 2014-01-12 20:15
    There is no fpga code for the Bemicro CV board and since it is basically no better than the DE0 which has already hit its limit, there seems no point IMHO in making code for the Bemicro cv board.
  • jmgjmg Posts: 15,140
    edited 2014-01-12 20:53
    Cluso99 wrote: »
    There is no fpga code for the Bemicro CV board and since it is basically no better than the DE0 which has already hit its limit, there seems no point IMHO in making code for the Bemicro cv board.

    Wow, tell Altera the Cyclone V is ' basically no better ' than the Cyclone IV - why did they even bother ??

    Parallax are going to have to do a Cyclone V build at some stage, as they plan to release a Cyclone V Board.
    The Bemicro CV Board is in stock, now.

    The details matter : Present Cyclone IV device lists 22320 LE and the Cyclone V is 25000
    - that 12% gain can be quite significant, on a design that is just on the limit of 22320

    There are plenty of users with smaller budgets who want to trial P2 code, so it makes sense to have a low end board.

    If the present build fails to fit in the Nano (even with SIZE chosen), the Bemicro CV could become very important indeed.
  • Dave HeinDave Hein Posts: 6,347
    edited 2014-02-02 09:13
    I ported pfth 1.03 to run on the FPGA. I ran into a couple of problems that took me a while to figure out. The first one had to do with a trick that I used under P1 when returning from within the body of a routine instead of at the end. On P1 I would do "jmp name_ret" instead of "jmp #name_ret" to save one instruction time. Of course, the P1 trick doesn't work on P2, so I had to add # to all of the place where I did this. I could have replace the "jmp name_ret" with a "ret" instruction, but the "jmp #name_ret" form works on both P1 and P2.

    The other problem I had is that image doesn't seem to build correctly if it's larger than 32K. I removed some comments from chess.fth to get the image less than 32K in size, and it seems to work OK.

    Use F11 to compile and load pfth. After it starts up you can type "words" to see all the words that are defined. pfth is ANS Forth interpreter that includes some common non-standard words. Those familiar with the "Starting Forth" book should be able to run most of the examples in it without any changes. You can run the chess program by entering the "chess" word. Moves must be entered in upper case, such as "DZ2-D4". You can quit out of the chess program by typing "Q" when prompted for a move.

    You can load some of the other Forth files at compile time by commenting out the file "chess.fth" line, and uncommenting the line for the file you want to include.

    If you are using the Prop Serial Terminal you should disable linefeeds to eliminate double-spacing. Or you can edit the definition for the CR word in init.fth to only emit 0d without emitting 0a also.
  • mindrobotsmindrobots Posts: 6,506
    edited 2014-02-02 09:31
    Very cool, Dave! Does it run on both or just the DE2?

    Those of us with little ones still want to play when we can! :0)
  • Dave HeinDave Hein Posts: 6,347
    edited 2014-02-02 10:11
    I've only tested it on the DE2, but I think it should run on the DE0-NANO as well. It uses one cog, and can only address 64K of memory. BTW, I should mention that David Betz ported an earlier version of pfth about a year ago. I used that to help me with pfth 1.03. Thanks to David for his earlier work.

    I haven't looked at the Prop-specific words in propwords.fth. I'll look at that next.
  • Cluso99Cluso99 Posts: 18,066
    edited 2014-02-02 16:10
    Congratulations Dave - fantastic news!
    Is this the first proper high level language to run on the P2? I don't think Spin2 is running properly to claim this title and neither is GCC - is this true guys?

    BTW I will update the first post - let me know if it runs on DE0 (no time to test yet). I will also update the latest fpga code link too.
  • potatoheadpotatohead Posts: 10,253
    edited 2014-02-02 16:15
    GCC ran on the earlier version. Several of us wrote and successfully compiled code. A second effort will start when the instruction set settles.

    That said, this is very cool! I don't want to take anything away from Forth now on the P2. :)
  • Cluso99Cluso99 Posts: 18,066
    edited 2014-02-02 16:22
    Dave,
    I think P2FTH needs its own thread ;)
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