Lately at Parallax, Daniel Harris discovered Terasic DE2-115 FPGA boards that we've all been using to emulate the Prop II. These boards are $599 (or $299 "student" price) and can emulate 6 of the 8 cogs. They are based on Altera Cyclone IV chips, and not as quick as the Stratix III that I've been using, but they are 1/8th the cost. We could publish a config file that would turn that board into a Prop II (minus the analog I/O pins), if anyone was interested. We should probably make a simple I/O board that plugs into it and gives a Prop Plug connection and a few 9-bit DACs for video. Oh, and an 8-pin Flash chip for program storage. These Cyclone IV chips can run cogs at up to 80MHz. The Stratix III can go 200MHz!
Chip, I would be extremely exited by the opportunity to play with a PII emulator. And I have a DE2-115 board laying on my desk here. In the past I have written a limited Verilog model of a PI Cog, see this original thread http://forums.parallax.com/showthread.php?107829 . I got the model working with up to 3 Cogs running at 120 MHz == 40 MIPS on DE1, DE2-70 and DE2-115 boards eventually, then lost interest. Please..
CMPR means compare-reverse, where D and S are swapped going into the comparator so that S-D is computed, instead of the usual (CMP) D-S.
WAITPEQ/WAITPNE now have timeouts. If the WC (write carry) bit is set, the last ALU result is used as a value to compare CNT to and upon exit of the instruction, C=1 if a timeout occurred, or C=0 if the WAITPxx condition was met. The port to watch is set using SETPORT D/#n (D or immediate).
The ROM is all done and installed into the memories. All we are waiting for now is the synthesized block to be re-routed to accommodate a new keep-out region which will make the signals between it and our pad frame (w/memories) more correct-by-design so that we are more confident about those 7,000+ connections. After that, it's ready to go to the foundry. The next foundry shuttle is in December and we plan to be on it.
What I am going to start next is a detailed description of all the assembly instructions, grouped by function. Then, I'll document the ROM and the three programs inside it. At that point, anyone who wants to start making their own tools will have sufficient data.
Lately at Parallax, Daniel Harris discovered Terasic DE2-115 FPGA boards that we've all been using to emulate the Prop II. These boards are $599 (or $299 "student" price) and can emulate 6 of the 8 cogs. They are based on Altera Cyclone IV chips, and not as quick as the Stratix III that I've been using, but they are 1/8th the cost. We could publish a config file that would turn that board into a Prop II (minus the analog I/O pins), if anyone was interested. We should probably make a simple I/O board that plugs into it and gives a Prop Plug connection and a few 9-bit DACs for video. Oh, and an 8-pin Flash chip for program storage. These Cyclone IV chips can run cogs at up to 80MHz. The Stratix III can go 200MHz!
Wow! This all sounds fabulous!! I'm certainly interested in an FPGA board with 6-8 COGs. I'm also very interested in the detailed instruction set documentation. This is all very good! Thanks Chip!!
Let me know if you need any help with any of this.
We could publish a config file that would turn that board into a Prop II (minus the analog I/O pins), if anyone was interested.
That would be nice (I'd think two cogs would be enough to "play" with it), but updated instruction documentation would be better. Besides, you'd need it to use the FPGA also.
I see this FPGA on Digikey, is that the one to get? I'll order one this week as I would really like to become familiar with the P2 beforehand if possible. Now if only I could get that "student" price!
Leon and Sapieha wondered if you could fit at least one cog into a DE0-Nano... that would also be of great interest to me, as I happen to have a Nano in my lab...
Now if two would happen to fit, that would be even better
[It would be useful even if there was only a tiny amount of hub memory, and only a single cog without analog io]
Update:
DE2-115: 114,480 LE's, up to 3.9Mbits of RAM, 266 multiploers
DE0-nano: 22,320 LE's, 594Kbits ram, 66 multipliers
114,800 / 6 = 19080 I think that one cog would fit!
[worst case: some instructions can be dropped for the nano test configuration - ie CORDIC]
A cog needs roughly 16Kbit of ram, i think three-ported, which would be 48Kbits
That would leave 546Kbits for hub etc, which is 68.25KB
Even if my estimate is wrong, it sounds like 32KB of hub ram would be possible (maybe up to 64KB)
CMPR means compare-reverse, where D and S are swapped going into the comparator so that S-D is computed, instead of the usual (CMP) D-S.
WAITPEQ/WAITPNE now have timeouts. If the WC (write carry) bit is set, the last ALU result is used as a value to compare CNT to and upon exit of the instruction, C=1 if a timeout occurred, or C=0 if the WAITPxx condition was met. The port to watch is set using SETPORT D/#n (D or immediate).
The ROM is all done and installed into the memories. All we are waiting for now is the synthesized block to be re-routed to accommodate a new keep-out region which will make the signals between it and our pad frame (w/memories) more correct-by-design so that we are more confident about those 7,000+ connections. After that, it's ready to go to the foundry. The next foundry shuttle is in December and we plan to be on it.
What I am going to start next is a detailed description of all the assembly instructions, grouped by function. Then, I'll document the ROM and the three programs inside it. At that point, anyone who wants to start making their own tools will have sufficient data.
Lately at Parallax, Daniel Harris discovered Terasic DE2-115 FPGA boards that we've all been using to emulate the Prop II. These boards are $599 (or $299 "student" price) and can emulate 6 of the 8 cogs. They are based on Altera Cyclone IV chips, and not as quick as the Stratix III that I've been using, but they are 1/8th the cost. We could publish a config file that would turn that board into a Prop II (minus the analog I/O pins), if anyone was interested. We should probably make a simple I/O board that plugs into it and gives a Prop Plug connection and a few 9-bit DACs for video. Oh, and an 8-pin Flash chip for program storage. These Cyclone IV chips can run cogs at up to 80MHz. The Stratix III can go 200MHz!
The DE0-nano has only 22K LE's (DE2-115 has 115K LE's), 66KByte of fast dualport memory (DE2-115 has more than 400KByte) and no SRAM, so could only support 1 COG' with 48KByte of hub memory. If Parallax is already using DE2-115 boards for internal (software) development, as Chip suggests, a limited edition of that for enthusiast early users would be very nice. Asking too much, as adaptations for other boards, would slow down PII development and that is the last thing we want.
Although: I agree with Sapieha that the magic of soft-processors is that you can interface them on chip to all the hardware resources of the board (LED's, VGA, SDRAM etc). An FPGA configuration file that allows only one fixed configuration is nice, but limited. Is there an in between possible, many of the designs bundled with Terasic boards contain "encrypted" IP, modules that you can use as in a higher level dessign, but cannot change as you have no access to the source
If the Monitor was Top-level single mask stuff, then that would allow some choice, (and cheaper bug fixes) but it sounds like it is compile-time ROM, which is really cast-in-stone stuff. You have to be very sure there are no bugs, and no drop-dead's.
From a security standpoint you will need to be SURE (need additional blink tag) that any prop reset will clear all hub and cog memory. Relying on losing power is NOT sufficient as you can cause memory cells to retain data by freezing the chip.
Conceivably, an attacker could break the boot mechanism then use the built-in monitor to dump memory and attack the "protected" code / data.
Red
PS: Does anyone have a link to the up-to-date PropII security documentation?
For me, using the proposed config file with the board specified would be great.
Count me in!
I'm ready to put the board Leon linked on order, as a student and I are working on Prop chips now anyway, which makes that one very attractive on price.
There is one other upside I can think of, and that is evaluation / engineering P2 chips will be in high demand. Having this option available will let people author stuff, leaving evaluation chips for those building hardware. Seems to me a nice gain in that we can get more stuff ready sooner, avoiding a lot of the lag that will happen otherwise.
When the P2 is out, and we all have real hardware, we transition to that, leaving this nice FPGA board to learn on, and I for one would see a lot of value out of taking this path.
__red__ and others: Do keep in mind that the Prop II is not intended to provide high level security. As Beau and others have discussed many times before, it is possible to break nearly any chip security system. The task of the chip designer / implementer is to make it difficult and expensive enough to do so that others will not bother, particularly when your rate of innovation is such that you'll have a newer and better device long before someone successfully copies your "old tech" device.
On the other hand, you don't want to make it too easy to copy ...
If Parallax is already using DE2-115 boards for internal (software) development, as Chip suggests, a limited edition of that for enthusiast early users would be very nice.
Nico Hattink
I will be ordering four (4) of these for our GCC team today. We gave some thought to stocking these boards for a wider group of developers but Chip and I haven't talked to much about it. He's at my home for the next couple of days so I will be sure to talk this over with him in detail. He's agreeable to everything, of course, but we would need to place the boards in a way that productively benefits Parallax, moving us quickly towards a release. It's really great to have freedom in engineering, but we'll need to identify the overlap of our interests with those holding FPGA boards to make it productive. There's nothing I'd love more than a much wider development team than we have, but we're extremely limited in bandwidth for a while to effectively manage our external team. You all know the business model: long-term R&D efforts (that we hope to shorten), a goal of commercial use, and lots of education/hobby applications during the meantime.
It's true that the Terasic DE0-Nano board could support ONE cog, but there is another problem: It takes TWO cogs to boot the chip, since the SHA-256/HMAC authenticator runs in its own cog, albeit briefly. I could make a ROM version that skips authentication. As someone else pointed out, the memory might only be 48k, instead of 128k. The monitor could run, anyway.
I'll order a DE0-Nano and see if I can get it working. It would require a tiny interface board for the host connection. We could get probably 24 I/O pins out, in addition to one fast 9-bit DAC for composite video.
And regarding memory clearing on reset for security, I believe we've got all the holes plugged. I will be documenting that soon.
I would have thought Parallax would be close to it's first shuttle run by now and a possible public release by the 1st half of next year. Makes me wonder if that is too optimistic.
I would have thought Parallax would be close to it's first shuttle run by now and a possible public release by the 1st half of next year. Makes me wonder if that is too optimistic.
I think the FPGA boards are mostly to get a jump on tools creation before the actual silicon arrives. I think P2 chips are still expected fairly soon.
A DE0-Nano is $86.25 at Digikey.com, with $8 for overnight shipping (or free shipping with a $200 order) ... and it would let a lot of people get an early start on software for the P2 :-)
For working with more complex code, more I/O and external memory, the DE2-115 is a MUCH better fit.
It's true that the Terasic DE0-Nano board could support ONE cog, but there is another problem: It takes TWO cogs to boot the chip, since the SHA-256/HMAC authenticator runs in its own cog, albeit briefly. I could make a ROM version that skips authentication. As someone else pointed out, the memory might only be 48k, instead of 128k. The monitor could run, anyway.
I'll order a DE0-Nano and see if I can get it working. It would require a tiny interface board for the host connection. We could get probably 24 I/O pins out, in addition to one fast 9-bit DAC for composite video.
And regarding memory clearing on reset for security, I believe we've got all the holes plugged. I will be documenting that soon.
How many year(s) away is the propeller 2...looking at boards that cost $600 and $90 (one cog)..That is crazy...
Certainly not so crazy if you already have the FPGA sitting on your desk waiting to do something interesting.
Also, I trust you read Chip's post where he indicated they intend to make the December shuttle run.
It's true that the Terasic DE0-Nano board could support ONE cog, but there is another problem: It takes TWO cogs to boot the chip, since the SHA-256/HMAC authenticator runs in its own cog, albeit briefly. I could make a ROM version that skips authentication. As someone else pointed out, the memory might only be 48k, instead of 128k. The monitor could run, anyway.
I wouldn't simplify the loader/authentication because I'd think one of the first uses of the FPGA would be to develop second-stage loaders.
If the DE2-115 code is made available (pls advise final decision once you've discussed with Chip, Ken), we could find a way to make an Australasian "rover" - a preloaded DE2 board plus accessories that could spend a week with each of us serious about Prop2 dev.
If the DE2-115 code is made available (pls advise final decision once you've discussed with Chip, Ken), we could find a way to make an Australasian "rover" - a preloaded DE2 board plus accessories that could spend a week with each of us serious about Prop2 dev.
That could really help
Are you kidding! I'm hanging on to mine! I'm serious about Prop2 dev!
Are you kidding! I'm hanging on to mine! I'm serious about Prop2 dev!
Know what you mean. My point is I suspect we'd benefit from the extra cogs and ram (DE2 over DE0), and sharing might be one way to make this happen quickly. (It doesn't preclude the case where we might all end up getting our own DE2s once we're hooked)
If the DE2-115 code is made available (pls advise final decision once you've discussed with Chip, Ken), we could find a way to make an Australasian "rover" - a preloaded DE2 board plus accessories that could spend a week with each of us serious about Prop2 dev.
Comments
Is it possible You can made that for that Board with ONE else 2 COG's ?
For testing PASM programming for Propeller II.
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593
Regards
Nico Hattink, Son, The Netherlands
Wow! This all sounds fabulous!! I'm certainly interested in an FPGA board with 6-8 COGs. I'm also very interested in the detailed instruction set documentation. This is all very good! Thanks Chip!!
Let me know if you need any help with any of this.
That would be nice (I'd think two cogs would be enough to "play" with it), but updated instruction documentation would be better. Besides, you'd need it to use the FPGA also.
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=502
Thanks for the update!
Leon and Sapieha wondered if you could fit at least one cog into a DE0-Nano... that would also be of great interest to me, as I happen to have a Nano in my lab...
Now if two would happen to fit, that would be even better
[It would be useful even if there was only a tiny amount of hub memory, and only a single cog without analog io]
Update:
DE2-115: 114,480 LE's, up to 3.9Mbits of RAM, 266 multiploers
DE0-nano: 22,320 LE's, 594Kbits ram, 66 multipliers
114,800 / 6 = 19080 I think that one cog would fit!
[worst case: some instructions can be dropped for the nano test configuration - ie CORDIC]
A cog needs roughly 16Kbit of ram, i think three-ported, which would be 48Kbits
That would leave 546Kbits for hub etc, which is 68.25KB
Even if my estimate is wrong, it sounds like 32KB of hub ram would be possible (maybe up to 64KB)
Although: I agree with Sapieha that the magic of soft-processors is that you can interface them on chip to all the hardware resources of the board (LED's, VGA, SDRAM etc). An FPGA configuration file that allows only one fixed configuration is nice, but limited. Is there an in between possible, many of the designs bundled with Terasic boards contain "encrypted" IP, modules that you can use as in a higher level dessign, but cannot change as you have no access to the source
Regards
Nico Hattink
From a security standpoint you will need to be SURE (need additional blink tag) that any prop reset will clear all hub and cog memory. Relying on losing power is NOT sufficient as you can cause memory cells to retain data by freezing the chip.
Conceivably, an attacker could break the boot mechanism then use the built-in monitor to dump memory and attack the "protected" code / data.
Red
PS: Does anyone have a link to the up-to-date PropII security documentation?
Count me in!
I'm ready to put the board Leon linked on order, as a student and I are working on Prop chips now anyway, which makes that one very attractive on price.
There is one other upside I can think of, and that is evaluation / engineering P2 chips will be in high demand. Having this option available will let people author stuff, leaving evaluation chips for those building hardware. Seems to me a nice gain in that we can get more stuff ready sooner, avoiding a lot of the lag that will happen otherwise.
When the P2 is out, and we all have real hardware, we transition to that, leaving this nice FPGA board to learn on, and I for one would see a lot of value out of taking this path.
On the other hand, you don't want to make it too easy to copy ...
I will be ordering four (4) of these for our GCC team today. We gave some thought to stocking these boards for a wider group of developers but Chip and I haven't talked to much about it. He's at my home for the next couple of days so I will be sure to talk this over with him in detail. He's agreeable to everything, of course, but we would need to place the boards in a way that productively benefits Parallax, moving us quickly towards a release. It's really great to have freedom in engineering, but we'll need to identify the overlap of our interests with those holding FPGA boards to make it productive. There's nothing I'd love more than a much wider development team than we have, but we're extremely limited in bandwidth for a while to effectively manage our external team. You all know the business model: long-term R&D efforts (that we hope to shorten), a goal of commercial use, and lots of education/hobby applications during the meantime.
I'll order a DE0-Nano and see if I can get it working. It would require a tiny interface board for the host connection. We could get probably 24 I/O pins out, in addition to one fast 9-bit DAC for composite video.
And regarding memory clearing on reset for security, I believe we've got all the holes plugged. I will be documenting that soon.
A DE0-Nano is $86.25 at Digikey.com, with $8 for overnight shipping (or free shipping with a $200 order) ... and it would let a lot of people get an early start on software for the P2 :-)
For working with more complex code, more I/O and external memory, the DE2-115 is a MUCH better fit.
What I tend to do is wait until I accumulate $200 worth of stuff I need to order from them, and get free shipping.
To wifey's chagrin, I usually don't have to wait very long to get a large enough order for free shipping
Also, I trust you read Chip's post where he indicated they intend to make the December shuttle run.
I wouldn't simplify the loader/authentication because I'd think one of the first uses of the FPGA would be to develop second-stage loaders.
That could really help
Know what you mean. My point is I suspect we'd benefit from the extra cogs and ram (DE2 over DE0), and sharing might be one way to make this happen quickly. (It doesn't preclude the case where we might all end up getting our own DE2s once we're hooked)
It is not code ---- Only compiled BINARY file for programing that will be available