It is not code ---- Only compiled BINARY file for programing that will be available
Yes I understand that - an fpga binary that includes a kind of 6 cog Prop2 soft core, which we can then test prop2 code on.
I guess what I meant by "made available" is "confirm a broader DE2 release for the rest of us, rather than just the core software team". It just sounded like that aspect hadn't been discussed thoroughly yet.
Yes I understand that - an fpga binary that includes a kind of 6 cog Prop2 soft core, which we can then test prop2 code on.
I guess what I meant by "made available" is "confirm a broader DE2 release for the rest of us, rather than just the core software team". It just sounded like that aspect hadn't been discussed thoroughly yet.
regards
tubular
Hey Lachlan -
Yes, I believe we will be able to release the design to general developers, beyond the core P2 software team for compilers, IDEs, etc. It hasn't been discussed in detail yet, but will be before the weekend gets underway. Chip is coming to my home for a couple of days so I'll have him cornered to discuss this issue, documentation about the ROM loader and documentation about instruction set. We would be happy to get some people started with development. I just need to understand (from Chip) any risks, limitations of releasing the binary design and we can make it happen.
Yes, I believe we will be able to release the design to general developers, beyond the core P2 software team for compilers, IDEs, etc. It hasn't been discussed in detail yet, but will be before the weekend gets underway. Chip is coming to my home for a couple of days so I'll have him cornered to discuss this issue, documentation about the ROM loader and documentation about instruction set. We would be happy to get some people started with development. I just need to understand (from Chip) any risks, limitations of releasing the binary design and we can make it happen.
Yes, I believe we will be able to release the design to general developers, beyond the core P2 software team for compilers, IDEs, etc. It hasn't been discussed in detail yet, but will be before the weekend gets underway. Chip is coming to my home for a couple of days so I'll have him cornered to discuss this issue, documentation about the ROM loader and documentation about instruction set. We would be happy to get some people started with development. I just need to understand (from Chip) any risks, limitations of releasing the binary design and we can make it happen.
Thanks Ken. It would be wonderful to start early and hit the ground running once silicon is released, that would have a big impact on time to market.
As I don't have money to buy DE1 -- But have DE0 for me that version are very interesting.
And I think that it is many of people that are in same situation that me
Hello Sapieha, yes, I understand your situation. Chip ordered a few of the low-cost FPGA boards today to see what they can do. I'll track his progress closely and report back. I'd be happy if our C team could also get by with the low cost boards, but I'm not certain they can. We shall see.
Now that we are very near to ordering the P2 I plan on switching gears 100% towards P2 preparations inside Parallax, including early support of developers like yourself.
What would be really useful for the DE2-115 FPGA developers version is to have something similar to an ICE where we can at least single-step and examine registers etc. I'm sure we will be banging our heads against the wall anyway, at least we will be able to cut down on the damage done.
IMHO the DE0 would be too limiting for LMM / gcc development work - just a couple of examples:
- needing serial I/O for GDB and debugging
- needing TV/VGA/etc for trying drivers plus app driving them.
Perhaps you could get the $299 educational price since you are getting 4+ units ... never hurts to ask them!
I think they would be inclined to give the discount due to the increased exposure for the DE2-115 on the forums.
DE0 would be great for making the new instruction set available to a much wider audience ahead of time, allowing software for P2 to be developed before test shuttle or production chips.
Hello Sapieha, yes, I understand your situation. Chip ordered a few of the low-cost FPGA boards today to see what they can do. I'll track his progress closely and report back. I'd be happy if our C team could also get by with the low cost boards, but I'm not certain they can. We shall see.
Now that we are very near to ordering the P2 I plan on switching gears 100% towards P2 preparations inside Parallax, including early support of developers like yourself.
What would be really useful for the DE2-115 FPGA developers version is to have something similar to an ICE where we can at least single-step and examine registers etc. I'm sure we will be banging our heads against the wall anyway, at least we will be able to cut down on the damage done.
Single step should be easy with some clock control, and there is (still?) a high speed chip-chip link.
Above that it would be nice to be able to read the PC (Opcode ptr), and even compare that, for break control, and have some R/W to register memory.
Even if just the PC could be linked to, read only, (which should be trivial to include) and you could map that to a 512W memory, to allow coverage HW and a single sticky-bit-column would allow you to view currently active pathways (so it would work on threads, in real time )
Of course, you also need to avoid morphing the FPGA too far from a real chip, and the best effort will be to find a debug that works in a real device too... using what the Prop II has.
Chip is a smart guy... i bet he could add something like: (to the FPGA code)
COGHALT n- halts COG n from another cog, dumps state to a 2KB area in the fpga's "hub" space
COGRESUME n - resumes a previously halted cog from the previously dumped 2KB area in the fpga's "hub" space
maybe even a
COGSNAPSHOT n - dumps cog without halting to a 2KB area in the fpga's "hub" space
Snapshots should also save/restore the internal PC of the cog along with W & Z ... basically the whole state, maybe even the LUT
Ken, don't shoot! This is FPGA work only, not new features for Prop 2. They can wait for Prop3 :-)
The above would be a REALLY nice addition to the FPGA logic, and would make debugging MUCH easier - including LMM kernel work and GCC work.
What would be really useful for the DE2-115 FPGA developers version is to have something similar to an ICE where we can at least single-step and examine registers etc. I'm sure we will be banging our heads against the wall anyway, at least we will be able to cut down on the damage done.
COGSNAPSHOT n - dumps cog without halting to a 2KB area in the fpga's "hub" space
That's unlikely to fit, as it needs another port, and already that is many-port memory. ie too invasive.
You can however, figure out where a COG is fetching real time, at low cost, via looking at the PC, and if you map that via a small content memory as I mentioned in #1630, you can tag subroutines and threads.
It would need relatively little HW to read that small memory, and rasterize onto a VGA screen to get a live picture of where your threads all were.
Some variable persistence could even be added.
What would be really useful for the DE2-115 FPGA developers version is to have something similar to an ICE where we can at least single-step and examine registers etc. I'm sure we will be banging our heads against the wall anyway, at least we will be able to cut down on the damage done.
Once a detailed description of the P2 instruction set is available, Dave Hein will probably update his simulator to handle the P2 instruction set. He's already started that and gotten as far as he can with the limited documentation that is currently available. The simulator should allow many more people to work with the P2 instruction set and can provide much better debug support.
however I think it COGSNAPSHOT could fit in the FPGA if instead of adding another memory port it simply halted the cog while the snapshot was saved.
It may reduce the cog count to five, but it may be worth it.
For debugging things like LMM kernels, COGHALT / COGRESUME would allow hardware single stepping of the non-LMM native instructions (which is my interest in it)
That's unlikely to fit, as it needs another port, and already that is many-port memory. ie too invasive.
You can however, figure out where a COG is fetching real time, at low cost, via looking at the PC, and if you map that via a small content memory as I mentioned in #1630, you can tag subroutines and threads.
It would need relatively little HW to read that small memory, and rasterize onto a VGA screen to get a live picture of where your threads all were.
Some variable persistence could even be added.
Yes, SpinSim does have a P2 mode, and it supports the instructions that I could decipher from the current specification. I'll update it once a new P2 spec is published.
however I think it COGSNAPSHOT could fit in the FPGA if instead of adding another memory port it simply halted the cog while the snapshot was saved.
Yes, if you remove your original feature of "without halting", then it gets much simpler.
You might even be able to patch-in a simple opcode-force that, just feeds fetches 512 of SNDSER (or RCVSER), with an incrementing field (supplied by the patch-counter) and then self-removes. The PC is back where it was. Cost is a MUX and a Small counter.
The rest of the FPGA swallows/supplies the data at full SNDSER (or RCVSER) speed. ie it looks like another Prop
Might be worth seeing about a group order, I imagine with all of us chomping at the bit we would have a pretty decent order.
C.W.
Well if you ask them, then ask them soon, because I will order mine this week either way. There's always the problem of co-ordinating this too as someone has to order and pay for it, collect payments, arrange shipments etc.
Well if you ask them, then ask them soon, because I will order mine this week either way. There's always the problem of co-ordinating this too as someone has to order and pay for it, collect payments, arrange shipments etc.
I've already made contact with Terasync about discounts, reselling, etc. and I was only able to get a 10% discount for 10 boards. I tried all the tricks I know, and usually at least one of them works but not this time.
I've already made contact with Terasync about discounts, reselling, etc. and I was only able to get a 10% discount for 10 boards. I tried all the tricks I know, and usually at least one of them works but not this time.
Ain't worth the trouble then but thanks for giving it a good go. Hope you still have some tricks left to use on Chip
I've already made contact with Terasync about discounts, reselling, etc. and I was only able to get a 10% discount for 10 boards. I tried all the tricks I know, and usually at least one of them works but not this time.
You tried with chocolate cookies? Usually this trick works with women at least.
I've already made contact with Terasync about discounts, reselling, etc. and I was only able to get a 10% discount for 10 boards. I tried all the tricks I know, and usually at least one of them works but not this time.
Perhaps you could form a school charter and as your 'students' we could all get academic discounts.
The progress of this Prop2 is very good, from the last few posts.
However, I'm still wondering is a CORDIC mechanism takes a constant amount of cycles in this Prop2. Manually, on pencil and paper, it takes 2-5 iterations for a cos(x) which x can be any radians. I tried that for a few values, each value has a different number of iterations. If for a sine-wave oscillator, each sample that comes out to the DAC must be fixed, like 5 cycles per sample for example.
Or, the CORDIC inside has a compensation mechanism inside which takes care of all these.
Will it has another DAC for sound generation purposes also?
Also - does it have a saturate instruction inside Prop2?
The DE2-115 is actually good value at $599, the EP4CE115 it uses costs over $400. I was wondering if putting one on a low-cost board was feasible.
Well whatever you do don't point out the students there's a $400 chip on a board they can purchase for $299, or they'll be desoldering like crazy.
I think the DE2 is good value for what you get, the $235 multitouch 7" screen seems good value too (though you can just use a VGA monitor without). We've considered the Altium Nanoboard, about the same price, but it has a smaller cyclone III and not as good expansion (HSMC accessories). The $390, twin 14bit ADC/DAC @ 150/250 Msps looks interesting.
- Both Terasic AD/DA boards have 50 ohm transformer coupled inputs/outputs with a 500 KHz low frequency limit: great for SDR (Software Defined Radio) but unusable for DSO type applications
- I feel a 1 COG - 48KB hub PII emulator is nice to experiment with the PII instructionset (the enthusiast users) but not for for the developers on this forum that want to explore PII based products.
Parallax take your pick, who do you want to support. Both??
As Leon pointed out, the FPGA on the DE2-115 costs about $400, alone. If it was much cheaper, we could make a one-size-fits-all board. For now, I think we will support both the DE0 and DE2 boards. The DE0 is very cheap to make add-on boards for, since it uses .100" connectors, while the DE2 uses a special Samsung HSMC part that is expensive. The DE0 board would be great for writing single-cog apps in assembly, but not much else. The DE2 board would be better for developing tool systems on which need something closer to the whole chip.
I don't know too much about fpga (because I went the Propeller route).
But, I'm interested in this early in...
I'm mostly interested in things that don't need the special pin I/O function of Prop2 (such as LCDs and SDRAM).
If I get the DE0 or DE2, how many digital I/O pins do I get?
DE2 -172 pin mezzanine port and 40 pin port for I/O.
The DE2 from the looks of it, is really a powerful system, that you'll get a lot of use after the early development of the P2 is taken care of. That is if you are into FPGA's and VHDL. Otherwise at $600 it's a expensive way to become a alpha tester for a few months.
As Leon pointed out, the FPGA on the DE2-115 costs about $400, alone. If it was much cheaper, we could make a one-size-fits-all board. For now, I think we will support both the DE0 and DE2 boards. The DE0 is very cheap to make add-on boards for, since it uses .100" connectors, while the DE2 uses a special Samsung HSMC part that is expensive. The DE0 board would be great for writing single-cog apps in assembly, but not much else. The DE2 board would be better for developing tool systems on which need something closer to the whole chip.
Otherwise at $600 it's a expensive way to become a alpha tester for a few months.
That's why I'm hoping an updated instruction reference gets published first. Then we can use it to update Gear and play with the P2 in software. Useful both now *and* when the chip is released.
Comments
Yes I understand that - an fpga binary that includes a kind of 6 cog Prop2 soft core, which we can then test prop2 code on.
I guess what I meant by "made available" is "confirm a broader DE2 release for the rest of us, rather than just the core software team". It just sounded like that aspect hadn't been discussed thoroughly yet.
regards
tubular
Hey Lachlan -
Yes, I believe we will be able to release the design to general developers, beyond the core P2 software team for compilers, IDEs, etc. It hasn't been discussed in detail yet, but will be before the weekend gets underway. Chip is coming to my home for a couple of days so I'll have him cornered to discuss this issue, documentation about the ROM loader and documentation about instruction set. We would be happy to get some people started with development. I just need to understand (from Chip) any risks, limitations of releasing the binary design and we can make it happen.
Ken Gracey
As I don't have money to buy DE1 -- But have DE0 for me that version are very interesting.
And I think that it is many of people that are in same situation that me
A cheap DE0-nano for simple verification and a more expensive DE2-115 for more complex verification.
I await the results of discussions between Ken & Chip with enthusiasm.
Seems like my time freeing up has just occurred at the right time
Thanks Ken. It would be wonderful to start early and hit the ground running once silicon is released, that would have a big impact on time to market.
Enjoy your festive weekend, don't work too hard.
Hello Sapieha, yes, I understand your situation. Chip ordered a few of the low-cost FPGA boards today to see what they can do. I'll track his progress closely and report back. I'd be happy if our C team could also get by with the low cost boards, but I'm not certain they can. We shall see.
Now that we are very near to ordering the P2 I plan on switching gears 100% towards P2 preparations inside Parallax, including early support of developers like yourself.
Thanks, Ken
IMHO the DE0 would be too limiting for LMM / gcc development work - just a couple of examples:
- needing serial I/O for GDB and debugging
- needing TV/VGA/etc for trying drivers plus app driving them.
Perhaps you could get the $299 educational price since you are getting 4+ units ... never hurts to ask them!
I think they would be inclined to give the discount due to the increased exposure for the DE2-115 on the forums.
DE0 would be great for making the new instruction set available to a much wider audience ahead of time, allowing software for P2 to be developed before test shuttle or production chips.
Regards,
Bill
Single step should be easy with some clock control, and there is (still?) a high speed chip-chip link.
Above that it would be nice to be able to read the PC (Opcode ptr), and even compare that, for break control, and have some R/W to register memory.
Even if just the PC could be linked to, read only, (which should be trivial to include) and you could map that to a 512W memory, to allow coverage HW and a single sticky-bit-column would allow you to view currently active pathways (so it would work on threads, in real time )
Of course, you also need to avoid morphing the FPGA too far from a real chip, and the best effort will be to find a debug that works in a real device too... using what the Prop II has.
COGHALT n- halts COG n from another cog, dumps state to a 2KB area in the fpga's "hub" space
COGRESUME n - resumes a previously halted cog from the previously dumped 2KB area in the fpga's "hub" space
maybe even a
COGSNAPSHOT n - dumps cog without halting to a 2KB area in the fpga's "hub" space
Snapshots should also save/restore the internal PC of the cog along with W & Z ... basically the whole state, maybe even the LUT
Ken, don't shoot! This is FPGA work only, not new features for Prop 2. They can wait for Prop3 :-)
The above would be a REALLY nice addition to the FPGA logic, and would make debugging MUCH easier - including LMM kernel work and GCC work.
That's unlikely to fit, as it needs another port, and already that is many-port memory. ie too invasive.
You can however, figure out where a COG is fetching real time, at low cost, via looking at the PC, and if you map that via a small content memory as I mentioned in #1630, you can tag subroutines and threads.
It would need relatively little HW to read that small memory, and rasterize onto a VGA screen to get a live picture of where your threads all were.
Some variable persistence could even be added.
however I think it COGSNAPSHOT could fit in the FPGA if instead of adding another memory port it simply halted the cog while the snapshot was saved.
It may reduce the cog count to five, but it may be worth it.
For debugging things like LMM kernels, COGHALT / COGRESUME would allow hardware single stepping of the non-LMM native instructions (which is my interest in it)
Might be worth seeing about a group order, I imagine with all of us chomping at the bit we would have a pretty decent order.
C.W.
Yes, if you remove your original feature of "without halting", then it gets much simpler.
You might even be able to patch-in a simple opcode-force that, just feeds fetches 512 of SNDSER (or RCVSER), with an incrementing field (supplied by the patch-counter) and then self-removes. The PC is back where it was. Cost is a MUX and a Small counter.
The rest of the FPGA swallows/supplies the data at full SNDSER (or RCVSER) speed. ie it looks like another Prop
I've already made contact with Terasync about discounts, reselling, etc. and I was only able to get a 10% discount for 10 boards. I tried all the tricks I know, and usually at least one of them works but not this time.
However, I'm still wondering is a CORDIC mechanism takes a constant amount of cycles in this Prop2. Manually, on pencil and paper, it takes 2-5 iterations for a cos(x) which x can be any radians. I tried that for a few values, each value has a different number of iterations. If for a sine-wave oscillator, each sample that comes out to the DAC must be fixed, like 5 cycles per sample for example.
Or, the CORDIC inside has a compensation mechanism inside which takes care of all these.
Will it has another DAC for sound generation purposes also?
Also - does it have a saturate instruction inside Prop2?
Well whatever you do don't point out the students there's a $400 chip on a board they can purchase for $299, or they'll be desoldering like crazy.
I think the DE2 is good value for what you get, the $235 multitouch 7" screen seems good value too (though you can just use a VGA monitor without). We've considered the Altium Nanoboard, about the same price, but it has a smaller cyclone III and not as good expansion (HSMC accessories). The $390, twin 14bit ADC/DAC @ 150/250 Msps looks interesting.
http://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/
- Both Terasic AD/DA boards have 50 ohm transformer coupled inputs/outputs with a 500 KHz low frequency limit: great for SDR (Software Defined Radio) but unusable for DSO type applications
- I feel a 1 COG - 48KB hub PII emulator is nice to experiment with the PII instructionset (the enthusiast users) but not for for the developers on this forum that want to explore PII based products.
Parallax take your pick, who do you want to support. Both??
Nico Hattink
But, I'm interested in this early in...
I'm mostly interested in things that don't need the special pin I/O function of Prop2 (such as LCDs and SDRAM).
If I get the DE0 or DE2, how many digital I/O pins do I get?
And, will they work just like the real thing?
DE2 -172 pin mezzanine port and 40 pin port for I/O.
The DE2 from the looks of it, is really a powerful system, that you'll get a lot of use after the early development of the P2 is taken care of. That is if you are into FPGA's and VHDL. Otherwise at $600 it's a expensive way to become a alpha tester for a few months.
In time You made Configure file for DE0-NANO can You use
JP1 on it as digital IO's.
JP2, JP3 to other things.
Thanks
That's why I'm hoping an updated instruction reference gets published first. Then we can use it to update Gear and play with the P2 in software. Useful both now *and* when the chip is released.