It does! Configure ctra for DUTY mode with frqa = 1 and output on a pin. Configure ctrb to be positive edge triggered with frqb = 1 and input from the same pin. There's your 64-bit counter: phsb:phsa !
It does! Configure ctra for DUTY mode with frqa = 1 and output on a pin. Configure ctrb to be positive edge triggered with frqb = 1 and input from the same pin. There's your 64-bit counter: phsb:phsa !
Don't! Use a normal NCO and edge detection for the upper 32bit. DUTY is all but reliable at 80MHz.
I am just disappointed that the lack of a simple controllable gate and line to input to the counters/video seems to be missing. This is such a simple thing and would permit these complex counters/video to be used in all kinds of ways in reverse (as in clocking the data in rather than out). Perhaps I am oversimplifying, but IMHO this would have far more use in any P2 design (for use as serial in modes) than any of the complex functions of these counters/video provide. Enough said.
Certainly a Counter should feature :
* External Gate ability
* External capture, Narrow pulse capable (and yes, both features available at the same time)
* capture of multiple counters from one pin. ( The pin-map nature of Prop should do this bit easily.)
* Precaler, ( also to > CoreCLK speed - A binary ripple counter and MUX is ok here, so Silicon cost is tiny)
* As well as the Adder-mode it has now, a more conventional divide by N too, for stable CLK generation.
( this will likely be there, if they have a fixed PWM ability )
* External triggered preset.
If that have Quadrature, they likely have at least this :
Up/Down ability, external Clock, and External Preset from the Index Pulse encoders deliver.
* & some tiny-config-logic, like PICs have of XOR + D/T FF on the pins.
'Can't speak to "consensus", but I think kuroneko and I are on the same page, at least. Be sure to use this procedure for reading all 64 bits:
1. Read the high counter.
2. Read the low counter.
3. Read the high counter again. Did it change since reading 1?
3a. Yes: Read the low counter again, and use this and reading 3.
3b. No: Use readings 1 and 2.
For the best accuracy, you will want to adjust the result for the delay between readings 2 and 3a. But this is a diversion from the topic of this thread. Any further comments should have their own thread.
The half bridge drivers I have seen already have a 500ns deadband to prevent cross conduction. Since you won't likely be driving MOSFETs directly from a propeller port pin, just let the driver chip handle it.
Most of the hits are for a missile defense system. There's a few hits for some form of software. There's an online electronics store in India. Various peices of elecronic hardware.
Most of the hits are for a missile defense system. There's a few hits for some form of software. There's an online electronics store in India. Various peices of elecronic hardware.
The Propeller II is LVS/DRC clean (LVS - Layout Versus Schematic ; DRC = Design(process) Rule Checking) at the top level with the exception of the 'core' which is currently being auto routed and will be LVSd/DRCd independently. Of the main RAM, there is a section of it that will be hard coded as ROM. This is just a bit-level bit-cell replacement of the existing bit RAM cell within the memory block. (<- a simple process that shouldn't take long.) We are expecting Propeller II chips in hand by mid to end May.
I can't WAIT for the Prop2. The one thing I'm curious about is what the release price will be *estimate* I need to save up money so I can get my hands on one ASAP.
Comments
-Phil
Certainly a Counter should feature :
* External Gate ability
* External capture, Narrow pulse capable (and yes, both features available at the same time)
* capture of multiple counters from one pin. ( The pin-map nature of Prop should do this bit easily.)
* Precaler, ( also to > CoreCLK speed - A binary ripple counter and MUX is ok here, so Silicon cost is tiny)
* As well as the Adder-mode it has now, a more conventional divide by N too, for stable CLK generation.
( this will likely be there, if they have a fixed PWM ability )
* External triggered preset.
If that have Quadrature, they likely have at least this :
Up/Down ability, external Clock, and External Preset from the Index Pulse encoders deliver.
* & some tiny-config-logic, like PICs have of XOR + D/T FF on the pins.
BTW, for those who want to do this with NCO, use negative edge triggering in the second counter.
-Phil
2. Read the low counter.
3. Read the high counter again. Did it change since reading 1?
3b. No: Use readings 1 and 2.
For the best accuracy, you will want to adjust the result for the delay between readings 2 and 3a. But this is a diversion from the topic of this thread. Any further comments should have their own thread.
-Phil
BTW: I was hoping we'd see actual Prop2 chips at the West Coast Expo this year... Guess that's not going to happen...
'Beat ya!
-Phil
Yes, the Prop II spec says that; but we were talking about the Prop I.
-Phil
"Parallax Phalanx" or maybe "Parallax Propeller Phalanx" ?
After all, having 96 identical, super-powered, I/O pins not to mention 8 cores, is probably the biggest distinguishing features, right?
Also, it's a "P...x" word. Probably not too many of those...
The Propeller II is LVS/DRC clean (LVS - Layout Versus Schematic ; DRC = Design(process) Rule Checking) at the top level with the exception of the 'core' which is currently being auto routed and will be LVSd/DRCd independently. Of the main RAM, there is a section of it that will be hard coded as ROM. This is just a bit-level bit-cell replacement of the existing bit RAM cell within the memory block. (<- a simple process that shouldn't take long.) We are expecting Propeller II chips in hand by mid to end May.
Thanks Beau for that bit of new.
(just trying to help!)
- Thoroughly test functionality.
- Characterize for voltage, current consumption, speed, etc., over temperature.
- Assuming first silicon checks out, schedule a production run.
- Produce a complete datasheet.
- Produce and document dev tools.
- Design and manufacture EVM kits.
- Write example software and educational materials for the EVMs.
- Design a marketing program and produce sales materials.
- It's show time! (Sometime in mid 2013?)
I'm sure I've left out some steps.-Phil