2) I have implemented some minor layout changes to the IO's that will increase functionality ... This is the result of a brainstorm between Chip and Roy Eltham :-)
4) Chip is making some small changes to the inner core (glue logic) which will not affect the layout that I am doing.
Do any of these changes, give the counters the ability to flip to shift registers ?
"Do any of these changes, give the counters the ability to flip to shift registers" - That I'm not sure about ... For changes that I'm doing, the answer would be no, however that could be another story with the core changes Chip is making.
I think you are incorrect in this case. It separately mentions "given D or n" as the mask. Maybe another way to ask the question is "what is the function of the mask?"
Oh, I see, I was still reading the SETMAP encoding. Yeah, port D should prolly be portD to help clarify that it's not talking about register direct addressing.
As for your original question, dunno. The logical ports A-D vs the physical ports 0-3 are a nicety. Using ports that have bonded pins is not infeasible so portD is probably a better choice than port 3.
... I wrote a script in the layout tool that allows me to do this. Looking at the video, next time I'll apply a reverse log rather than just a linear advancement so that the time spent on each magnified view will be equally distributed over the entire video length.
Looking at the video, next time I'll apply a reverse log rather than just a linear advancement so that the time spent on each magnified view will be equally distributed over the entire video length.
Seems there may be some confusion about what is inside the core and outside...
From previous posts, I have presumed that...
Inside the core:
Cog processor logic and counter logic
Outside the core:
Hub memory
Cog memory and fifos
pins and associated logic and routing around the outside of the die
..there is still some zoom granularity towards the very end, but this is because the layout tool itself has a snap-zoom at low viewing levels. It's still better than the first video. I would love to provide the RAW mpeg video, but it's 162Megs.
Enjoy!
BTW) I love the guesses ... please send them the the E-mail address I have created, so that it's easier to keep track of them.
The 'outer core' consists of all of the I/O's, all of the memories, all of the PLL's, as well as all of the fuses.
The 'inner core' is completely digital glue-logic ... AND's, OR's, XOR's, NOT's, NOR's, NANDs, Flip-Flop's, MUX's, etc.
This inner core constitutes the processing and communication of all of the COGs... if you look at the video, and some of the stills, you can see just by the wiring where the 8-cogs naturally break down into.... As Chip and I have said, it sort of looks like a square pizza. There was no special rendering other than the placement of the logic from the tool to create this pattern, this image emerged based on the symmetry and interconnection/communication of the cogs themselves.
I love the fact that the symmetry is emergent, and isn't the true symmetry of something laid out perfectly and then rotated and stamped eight times but that's obviously slightly different in each slice, the way animals are symmetrical except for a few details like hearts and handedness. The P1 die was iconic and instantly recognizable and the P2 die is going to be iconic and instantly recognizable for completely different reasons.
I am just curious, what software is parallax using for designing the prop 2? More specifically, it looks like you are designing all the gates and whatnot by hand which leads me to ask, are you possibly using an opensource asic design program like Magic or Electric?
Comments
Do any of these changes, give the counters the ability to flip to shift registers ?
Oh, I see, I was still reading the SETMAP encoding. Yeah, port D should prolly be portD to help clarify that it's not talking about register direct addressing.
As for your original question, dunno. The logical ports A-D vs the physical ports 0-3 are a nicety. Using ports that have bonded pins is not infeasible so portD is probably a better choice than port 3.
No idea about the masking question.
7500um to 14um in 26 seconds:
http://www.youtube.com/watch?v=LNVxGSpeYD0&feature=youtu.be
... I wrote a script in the layout tool that allows me to do this. Looking at the video, next time I'll apply a reverse log rather than just a linear advancement so that the time spent on each magnified view will be equally distributed over the entire video length.
Enjoy!!
Have you been talking to Arthur Dent again?
C.W.
Edit to add: That is total transistors.
Yes please :P
From previous posts, I have presumed that...
Inside the core:
Cog processor logic and counter logic
Outside the core:
Hub memory
Cog memory and fifos
pins and associated logic and routing around the outside of the die
http://www.youtube.com/watch?v=ghMWI71bGB0
..there is still some zoom granularity towards the very end, but this is because the layout tool itself has a snap-zoom at low viewing levels. It's still better than the first video. I would love to provide the RAW mpeg video, but it's 162Megs.
Enjoy!
BTW) I love the guesses ... please send them the the E-mail address I have created, so that it's easier to keep track of them.
The 'outer core' consists of all of the I/O's, all of the memories, all of the PLL's, as well as all of the fuses.
The 'inner core' is completely digital glue-logic ... AND's, OR's, XOR's, NOT's, NOR's, NANDs, Flip-Flop's, MUX's, etc.
This inner core constitutes the processing and communication of all of the COGs... if you look at the video, and some of the stills, you can see just by the wiring where the 8-cogs naturally break down into.... As Chip and I have said, it sort of looks like a square pizza. There was no special rendering other than the placement of the logic from the tool to create this pattern, this image emerged based on the symmetry and interconnection/communication of the cogs themselves.
Three million.
-Phil
Side note: soon I think it's time to start a new serious Prop2 update thread.
Well, it's a nice round number!
I think I've read that Chip is using a Stratix - http://www.altera.com/devices/fpga/stratix-fpgas/stratix/stratix/stx-index.jsp - for functional testing.
not sure what else ...