anyone know max current draw of max II core? I can't seem to find max. typical is about 80mA for the 570.
i want to know if LP3990TL-1.8/NOPB is to small. 150mA
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mctrivia said...
Could you not boot from the 5mhz xin attached to prop pin? Having an eeprom not to big of inconvience.
Many times cames to the forum the need to have more program storage, many users have asked if it is possible to boot from above the 32k boundary of a larger eeprom or sd card. Now everyone that have some hardware/microcontroller skills (and have read it the prop datasheet the boot procedure) knows that this is not possible. So many alternative bootstrap code was written to allow this. The general way is to boot a new booter from eeprom and it will load alternate code on desire. Now IMO this involves longer boot times and highe component count so for such applications (like our) I have thought on what I can do.
The solution is (because the cpld is already there) to replace the eeprom with a much larger spi (but the same can be done on a larger i2c eeprom, of course not connected to the prop but to the cpld)
The prop after the reset, when the internal rc clock stabilizes,·makes the first boot attempt on serial port (P30/31), if nothing foung it try from the eeprom (P28/29) and if still nothing it shutdown till the next reset/power cycle.
Now the prop do not need the clock to boot, but if you do not boot you can not provide the clock to the cpld, and if you do not provide the clock to the cpld you can not boot. I need this clock because also the cpld have its start-up (booting) time. When the cpld is started it prepares itself for spi access (setup the commands for the quad continous read mode) and when ready takes the prop out of reset so it not loose the prop eeprom-boot time-window. The external cpld clock clocks the state machine and the spi flash. Now this is working from the spi firsts 32k but it is easy to add a register to boot from the second, third ... 32k block on next reset (using the ufm also on next power-up) This opens the possibilty of really secure field/remote firmware upgrade.
Theoretically with·EPM family the prop boot from the spi flash could be possible even without external clocks because if the UFM internal oscillator (3.3<>5.5MHz), but it suffers the same problems as the prop one: stability. So you have two asynchronous (unstable) blocks that must in synchronous way communicate between them. Practically some trials with different devices must be done (actually I am developing on coolrunner - I haven't EPM hardware). Usually I not rely on theory without practical tests on such things. Simulators exists but I am not skilled enough to rely on them when cames to tight synchronization timings.
mctrivia said...
can i do this to save pins?
i see chip select is used in the timing but do not see write protect and hold with the M25P64-VME6TG
Regarding the flash pins, I have used all six because I am working in 4bit mode, but I use W25Q16BV/W25Q32BV(W25Q64BV/W25Q128BV). This is not really needed to boot the prop. The idea behind this was to extend the above state machine functionality and add a kind of flash shadowing (a really fast function to copy flash contents to the sram) after the first boot was done.
I have seen in this way:
- I can copy the background images in the screen area
- I can have multiple small areas (sprites with transparent background) automatically overlapped on the backround (eg. mouse pointer that can change on the fly from arrow to hourglass) done in hardware (cpld)
- Maybe small movie windows
But other users can find other uses (moving tables, preset texts ...)
In order to save pins maybe we can move in other way - reduce the prop pins connected to the cpld (actually I have just 16): what about using p0..7, p24..31, xin, reset and just one port between this two p8..15/p9..23? I think that 24 prop IOs connected to the cpld are enough, we only need to choose the right ones (here again pasm cames in so gurus help will be apreciated)
I'm not a guru; if I was, I probably would not be the right one [noparse]:)[/noparse] There is some speed advantage to having control lines in the upper 8 propeller pins if you keep the data on OUTA which is faster than constantly moving it there from a register. When you want to write a long on an 8 bit interface, you only have to be concerned about the control line state once if it is on pin 24 for example. This is less of an advantage on a 16 bit interface. I think the most flexible approach is to have all pins connected to the FPGA (would likely be more expensive though).
44 pins for Sram: 20 address + 16 data + 4 control (OE,WE,BHE,BLE) + 4 chip select (CE for 4 chips)
6 pins for winbond flash
26 pins for prop: xin + reset + 24 (p0..7 + p24..31 + p8..15/16..23)
1 pin clock oscillator input (2 for crystal connection)
Beside the above I suggest 1 pin as additional CS on spi bus with a small header (CS,CLK,DI,DO,GND). Probably sd card holder, if any, will be panel/housing mounted to be accessible from outside. This way the SD can be accessed through the data bus between the cpld and the prop (in spi (transparent) mode). Further developments on the cpld can allow (by adjusting rokicki/lonesock low level drivers) for data exchange·on parallel bus having the cpld serialize/deserialize them to the sd (big speed gains).
jazzed said...
The video generator shifts out a long on the order of micro-seconds and can wait 10x that. This is a non-starter.
Could you explain better this concept?
My thoughts was:
for composite video mode
- plla setup at 160MHz feeding the video hardware and outputing data strobe on pina
- cmode 0: two color
- vscl pixelclocks: 1
- vscl frameclocks:32
- pixel register contains data to send
I was hoping that by outputing bits at 160 so two bits per system clock cycle so 8 bits per cog instruction time this is equivalent to use 4 consecutive mov instructions on 8bit bus but if I need to read the data I do not have to change the dira register between the write address and read data phases.
for vga mode
- plla setup at 160MHz feeding the video hardware and outputing data strobe on pina
- vscl pixelclocks: 1
- vscl frameclocks:4
- color register contains data to send
I was hoping that by outputing bytes at 160 so two bytes per system clock cycle so potentially 8 bytes·per cog instruction time: when out of waitvid data already delivered.
An other thing of the datasheet turn on a lamp in my brain
When FrameClocks cycles occur and the cog is not in a [font=Parallax,Parallax][font=Parallax,Parallax]WAITVID [/font][/font]instruction, whatever data is on the source and destination busses at the time will be fetched and used. So it is important to be in a [font=Parallax,Parallax][font=Parallax,Parallax]WAITVID [/font][/font]instruction before this occurs.
so if we look at this from an other point of view waitvid is not the only method to deliver data to the video hardware. Whatever instruction that places the right data on the right bus on the right time will fulfil the request ! If the plla is running the same frequency as system clock how much they differ in sync? How difficult is deliver data with an other instruction that beside delivering the data will also make something useful in the same time?
PEDIT: In other words can a waitpne sync to pina and then can eg.·mov Colors, DataToSend put the right data (DataToSend) on destination bus on the right time? Colors in this case is a temp register since the destination of the mov is not important, important is the value on the destination bus at the right time!
1) EPM570M256C5N 440 macro, 160 io, 570 logic blocks, 5.4ns.
11x11mm with 4 row of pins
2) EPM570ZM144C7N 440 macro, 116 io, 570 logic blocks, 9.0ns
7x7mm with 4 rows of pins
Both cost a little more for the ic but not to much. (2) can only handle max speed of 160 so overclocking prop to 100 would not be an option. I have not checked what pins are where but with both pin layouts i would probably have to switch to a more expensive board layout. At present i am using via depths of 1..6 and 2..6 for either of those options if the middle is not entirely ground i would need 1..6,3..6,4..6,5..6 which doubles the amount of work for the assembler.
42 pins for Sram: 20 address + 16 data + 4 control (OE,WE) + 4 chip select (CE for 4 chips), ,BHE,BLE tied low
4 pins for winbond flash(W25X64VZEIG): cs,do,clk,dio + wp, hold tied high
29 pins for prop: xin + reset + 27 (p0..15 + p21..31) (17..20 on 240 if 570 is pin compatible)
1 pin clock oscillator input (2 for crystal connection)
what about not trying to tie to 28-31 since these have limited usage. if we boot from eeprom stil it can have a loader to load anything you want using a different set of pins and still leaving 28-29 for i2c devices and 30-31 for programing the prop+serial with other devices. in that case
p0..p26 + p27..30 for 240
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dMajo said...
so if we look at this from an other point of view waitvid is not the only method to deliver data to the video hardware. Whatever instruction that places the right data on the right bus on the right time will fulfil the request ! If the plla is running the same frequency as system clock how much they differ in sync? How difficult is deliver data with an other instruction that beside delivering the data will also make something useful in the same time?
PEDIT: In other words can a waitpne sync to pina and then can eg. mov Colors, DataToSend put the right data (DataToSend) on destination bus on the right time? Colors in this case is a temp register since the destination of the mov is not important, important is the value on the destination bus at the right time!
@dMajo, This is worth further examination.
The video generator however, seems to be working on a separate schedule from the COG and PLLA ... this is what I see with a scope, and I don't see any way to control it ... I could be wrong. Also WAITVID is a HUB instruction like RDLONG, but that can be managed.
@mctrivia, Why don't you just route the P28..31 pins transparently through the CPLD? This would allow control over the behavior of these pins. After boot, they could be anything you want with an appropriate CPLD configuration register bit set.
1) EPM570M256C5N 440 macro, 160 io, 570 logic blocks, 5.4ns.
11x11mm with 4 row of pins
2) EPM570ZM144C7N 440 macro, 116 io, 570 logic blocks, 9.0ns
7x7mm with 4 rows of pins
I have not looked at the datasheet but probably those are also compatible with the 1270 which is not bad if the cpld internal design will request it.
mctrivia said...
42 pins for Sram: 20 address + 16 data + 4 control (OE,WE) + 4 chip select (CE for 4 chips), ,BHE,BLE tied low
4 pins for winbond flash(W25X64VZEIG): cs,do,clk,dio + wp, hold tied high
29 pins for prop: xin + reset + 27 (p0..15 + p21..31) (17..20 on 240 if 570 is pin compatible)
1 pin clock oscillator input (2 for crystal connection)
what about not trying to tie to 28-31 since these have limited usage. if we boot from eeprom stil it can have a loader to load anything you want using a different set of pins and still leaving 28-29 for i2c devices and 30-31 for programing the prop+serial with other devices. in that case
p0..p26 + p27..30 for 240
- ram: you need the bhe and ble otherwise the 8 bit writes became: 16 bit reads, replace the "under writing" byte, write 16 bits
- prop: why p21..31 and not p24..31. With p0..15 two configurations are possible: 16bit data bus and 8bit databus+ 8IO available for other purposes. P24..31 as control lines are enough even if you consider double function the p28..31.·On the other side having a entire clean byte/port available exclusively as IO it's useful when dealing with native video/vga where you can chose the outputs only in groups. In case of cpld vga output you will have p0..7(data bus to cpld), p8..15(video dac), P16..17 (v/h sync) one from P24..31 (pixelclock)
- flash: the one you have choosen is max dual bit, mine was 4 bit. The signals you have tied high for me was data lines. Having my flash 50MB/s capacity (4 bits @100MHz), 25Mword/s and the ram 100Mword/s it was supposed to make background (DMA) transfers from flash to sram while it is outputing video and/or prop is accessing it (eg. changing the background picture with a new one stored in flash). It's true a vga screen will be no more than 2MB but I you have all the ram filled with graphics there is no place for LMM(XMM) code. If the design will be good I foresee some Catalina development on it (maybe also ImageCraftC, some clever code porting from Morpheus)
As per cpld size (I have not undestood what functions you want from it) if you want to implement half the functions I have discussed here I think that you should forget the 240 and focus on 570 (maybe 1270) and search a package that fit both. Prop<>ram, flash>ram, ram>vga,·spiboot,·means a virtual 3 port implementation to the ram interface, state machines for boot and flash>ram then if you want parallel flash(sd) access a serializer/deserializer. I am quite sure 240 is not enough.
PEDIT: BTW the devices without G and Z are equal to the G ones (same frequency domain) but with integrated (built-in) 1.8V regulator so can be supplied with 3.3V
Every pin can. The problem is with out going to a bigger chip there is not enough pins to do all of them.
240 short 1
570 short 5
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i think the spiboot is probably a little over rated eeprom are a lot cheaper then trying to implement pll on the board.
the 4bit flash does not come in 8MB size and I would like the entire ram contents to be capable of backing up.
the ram to vga as I understand it does not use the prop at all but since with this package the only link to the real world is the prop pins your output would have to be on one of the pins routed to a prop pin the prop will just not have to use those pins.
the 1270 and 570 do both come in 256MBGA package i will check out if the pin orientation makes possible for use without super increasing price or leaving not enough room for flash.
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so the 570 and 240 are both compatible with each other if there is a jumper select on the 4 different pins.
using a SN74LVC1G139YZPR for the ram chip selects would save 2 pins.
Do we need 8 bit write capabilities? or can the cpld simulate 8 bit access with 16 bit hardware?
I can fit the 570 or 1270 but not all IO would be accessible but they both have way more then needed so that should not be a problem. They are pricey though EPM1270M256C5N is $34 and the non Z 570 are not available in small quantities.
pro/con
EPM1270M256C5N - $34.08
EPM570M256C5N - $26.23 minimum quantity 176
EPM570M100C5N - $16.07 short even more pins more logic
EPM240M100C5N - $7.25 short a few pins and little logic
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with 240 extra pin used for an usd card header along with spi pins.
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i think the spiboot is probably a little over rated eeprom are a lot cheaper then trying to implement pll on the board.
the 4bit flash does not come in 8MB size and I would like the entire ram contents to be capable of backing up.
the ram to vga as I understand it does not use the prop at all but since with this package the only link to the real world is the prop pins your output would have to be on one of the pins routed to a prop pin the prop will just not have to use those pins.
the 1270 and 570 do both come in 256MBGA package i will check out if the pin orientation makes possible for use without super increasing price or leaving not enough room for flash.
The spiboot was indended because the flash is already there and you save time during power up. If you provide the clock to the cpld from prop (beside impossible spiboot) you waste a prop io more just for clock and the power savings obtained by 1) reducing the prop clock down to 1MHz 2)freezing and wake-up the prop by holding the xin are not possible
The 4bit flash: 8MB and 16MB are under design and planned soon (datasheet already available)
ram to vga: yes, on the other side if you want classic vga you still need 8 prop IOs, in this case is the same but they will be driven by the cpld (this way up to 1600*1200*256col @60Hz should be possible)
1270/570 it will be nice. 240 is not enough. It will be good to have the opportunity to move to 1270 without pcb rework (if 570 still not enough). in this case you will have two products cheeper (less performance), more expensive (more performance), with several choices on ram/flash sizes
mctrivia said...
using a SN74LVC1G139YZPR for the ram chip selects would save 2 pins.
Do we need 8 bit write capabilities? or can the cpld simulate 8 bit access with 16 bit hardware?
I can fit the 570 or 1270 but not all IO would be accessible but they both have way more then needed so that should not be a problem. They are pricey though EPM1270M256C5N is $34 and the non Z 570 are not available in small quantities.
SN74LVC1G139YZPR: not have had a look at datasheet but probably it's a decoder. If so I agree
8bits writes: you need this otherwise you will loose more then half the bandwidth to the ram. Specially when making cpld vga you are forced to 8 bit data bus on the prop and most of the operations will be writings to the ram
570 & small qty: I have seen it on altera site, but have not looked arround for other distributors (maybe ...)
20 address lines + 4 chipselects = 4MB. Never mind 16 bit data .... You don't need OE* if your address/data lines are directly connected and have CS* for each. Surely there is an 8MB cs/di/do SPI flash (di/do can be connected in a pinch) ?
If I can find in smaller quantities 570 in 256mbga would be probably best. Lots of io.
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OE* is shown on the timing on the datasheet .... so you will know how to use it if you need to use it. It is optional on SRAM if your address/data lines are directly connected and you have CS* for each device. The only other reason you might need it is to lower the power consumption if the SRAM is idle.
well I have now switched to the 570/1270 so io is not a problem and saving power is useful so i will run a line for it. Now if only I could find the headers used on the basic stamp.
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Actually, the spec indicates that low power mode is set when CE pins are disasserted.
I would trade some propeller pins for the extra cost of the CPLD ($16 to you $40+ to the customer) unless the device is too small.
I am pretty sure the 240 could do all the basics but the large package of the 570m256 makes routing pins easier and will hopefully allow a sd card/io expansion module. Very tight bored though.
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mctrivia said...
I am pretty sure the 240 could do all the basics but the large package of the 570m256 makes routing pins easier and will hopefully allow a sd card/io expansion module. Very tight bored though.
Because now you have plenty of IOs I hope we can turn back to 4bit(6pin)·flash implementation. wp, hold can be tied high by cpld initially if you do not want to wait for the 8/16M 4bit one
I presume now all the prop pins will be routed to cpld?
Regarding the SD and unused cpld IOs (I have seen your other thread): do you have enough space to place 10 pads more (5 on top and 5 on bottom side/edge, without pins, just pads) connected to the cpld? It will be up to the end user to solder wires/pins on them to enjoy of the additional IOs (SD or whatever he wants).
One request more: after all that there is some spare pins still available? If so it will be nice to have just some of the prop pins connected to two of the cpld. To one directly and to the other through a resistor. This allows set/reset comm on single pin (eg. cpld outputs a state to the prop through a resistor, when prop perform the required action output the opposite state on the same pin that before was an input, cpld know this because on the directly connected pin reads the opposite state as on the other one going through the resistor). I will think over this during the weekend and let you know which pop pins are the best maches to do this. (maybe not needed because of the bus-hold feature, need to reserch what happens during por cycles)
BTW: prop reset should go only to the cpld with a pulldown resistor and the cpld reset should instead to the dip40. if enough room a jumper between the two will be appreciated.
160 io some get wasted to route but still lots left.
Was hoping to find a fine pitch board connector that could go over end with jtag and 20+io
I may be able to do a few double pins. Space for resister is restriction
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Any vhdl I write will be open and I will make a method for others to upload there's. Some may chose to sell there vhdl I will sell on there behalf.
Schematic will be available to aid development but pcb and schematic are my ip
As for rational to wrote pins to cpld and prop there is 2 reasons.
1) max versatility for prop to ram communication
2) cpld can take some of workload(ie generate video from ram)
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If i can get the pins i want then i can use HSEC8-110-01-SM-DV-A for 20 pins on the end of the board. if i can't then the board will be a little wider and i can use HSEC8-120-01-SM-DV-A which has 40 pos.
4-JTAG
2-Power
14-IO
the problem is i need 4.2mm past last device to use these headers.
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mctrivia said...
Any vhdl I write will be open and I will make a method for others to upload there's. Some may chose to sell there vhdl I will sell on there behalf.
Schematic will be available to aid development but pcb and schematic are my ip
As for rational to wrote pins to cpld and prop there is 2 reasons.
1) max versatility for prop to ram communication
2) cpld can take some of workload(ie generate video from ram)
Just an integration (for others)
2) cpld can take some of workload:
Output VGA video up to max. 1600*1200*256colors @60Hz (with hardware support for transparent backround sprites useful in eg. mousepointer, games)
Can sample from adc at very high speeds (above prop capabilities) and store data to ram for further prop analyses
Can integrate prop's ALU (with missing multiplication/division), make conversions (string<>decimal, dec<>bcd, floating<>integer, big<>middle<>little endians, ...),
Can encode/decode (manchester, simple encryption), serialize/deserialize (eg. selfclocked spi with parallel data exchange with the prop)
So I have 2 options make board 4mm longer then dip and get 12 extra io via edge connector or make exact same size and have some pads on top for extra io.
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The edge connector idea is to big. Would take up 7mm past edge will have to make solder pads for spare
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i want to know if LP3990TL-1.8/NOPB is to small. 150mA
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The solution is (because the cpld is already there) to replace the eeprom with a much larger spi (but the same can be done on a larger i2c eeprom, of course not connected to the prop but to the cpld)
The prop after the reset, when the internal rc clock stabilizes,·makes the first boot attempt on serial port (P30/31), if nothing foung it try from the eeprom (P28/29) and if still nothing it shutdown till the next reset/power cycle.
Now the prop do not need the clock to boot, but if you do not boot you can not provide the clock to the cpld, and if you do not provide the clock to the cpld you can not boot. I need this clock because also the cpld have its start-up (booting) time. When the cpld is started it prepares itself for spi access (setup the commands for the quad continous read mode) and when ready takes the prop out of reset so it not loose the prop eeprom-boot time-window. The external cpld clock clocks the state machine and the spi flash. Now this is working from the spi firsts 32k but it is easy to add a register to boot from the second, third ... 32k block on next reset (using the ufm also on next power-up) This opens the possibilty of really secure field/remote firmware upgrade.
Theoretically with·EPM family the prop boot from the spi flash could be possible even without external clocks because if the UFM internal oscillator (3.3<>5.5MHz), but it suffers the same problems as the prop one: stability. So you have two asynchronous (unstable) blocks that must in synchronous way communicate between them. Practically some trials with different devices must be done (actually I am developing on coolrunner - I haven't EPM hardware). Usually I not rely on theory without practical tests on such things. Simulators exists but I am not skilled enough to rely on them when cames to tight synchronization timings.
Regarding the flash pins, I have used all six because I am working in 4bit mode, but I use W25Q16BV/W25Q32BV(W25Q64BV/W25Q128BV). This is not really needed to boot the prop. The idea behind this was to extend the above state machine functionality and add a kind of flash shadowing (a really fast function to copy flash contents to the sram) after the first boot was done.
I have seen in this way:
- I can copy the background images in the screen area
- I can have multiple small areas (sprites with transparent background) automatically overlapped on the backround (eg. mouse pointer that can change on the fly from arrow to hourglass) done in hardware (cpld)
- Maybe small movie windows
But other users can find other uses (moving tables, preset texts ...)
In order to save pins maybe we can move in other way - reduce the prop pins connected to the cpld (actually I have just 16): what about using p0..7, p24..31, xin, reset and just one port between this two p8..15/p9..23? I think that 24 prop IOs connected to the cpld are enough, we only need to choose the right ones (here again pasm cames in so gurus help will be apreciated)
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· Propeller Object Exchange (last Publications / Updates)
Post Edited (dMajo) : 8/27/2009 10:05:32 AM GMT
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--Steve
Propeller Tools
6 pins for winbond flash
26 pins for prop: xin + reset + 24 (p0..7 + p24..31 + p8..15/16..23)
1 pin clock oscillator input (2 for crystal connection)
Beside the above I suggest 1 pin as additional CS on spi bus with a small header (CS,CLK,DI,DO,GND). Probably sd card holder, if any, will be panel/housing mounted to be accessible from outside. This way the SD can be accessed through the data bus between the cpld and the prop (in spi (transparent) mode). Further developments on the cpld can allow (by adjusting rokicki/lonesock low level drivers) for data exchange·on parallel bus having the cpld serialize/deserialize them to the sd (big speed gains).
What about a higher pin count package?
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· Propeller Object Exchange (last Publications / Updates)
My thoughts was:
for composite video mode
- plla setup at 160MHz feeding the video hardware and outputing data strobe on pina
- cmode 0: two color
- vscl pixelclocks: 1
- vscl frameclocks:32
- pixel register contains data to send
I was hoping that by outputing bits at 160 so two bits per system clock cycle so 8 bits per cog instruction time this is equivalent to use 4 consecutive mov instructions on 8bit bus but if I need to read the data I do not have to change the dira register between the write address and read data phases.
for vga mode
- plla setup at 160MHz feeding the video hardware and outputing data strobe on pina
- vscl pixelclocks: 1
- vscl frameclocks:4
- color register contains data to send
I was hoping that by outputing bytes at 160 so two bytes per system clock cycle so potentially 8 bytes·per cog instruction time: when out of waitvid data already delivered.
An other thing of the datasheet turn on a lamp in my brain so if we look at this from an other point of view waitvid is not the only method to deliver data to the video hardware. Whatever instruction that places the right data on the right bus on the right time will fulfil the request ! If the plla is running the same frequency as system clock how much they differ in sync? How difficult is deliver data with an other instruction that beside delivering the data will also make something useful in the same time?
PEDIT: In other words can a waitpne sync to pina and then can eg.· mov Colors, DataToSend put the right data (DataToSend) on destination bus on the right time? Colors in this case is a temp register since the destination of the mov is not important, important is the value on the destination bus at the right time!
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· Propeller Object Exchange (last Publications / Updates)
Post Edited (dMajo) : 8/27/2009 5:02:03 PM GMT
1) EPM570M256C5N 440 macro, 160 io, 570 logic blocks, 5.4ns.
11x11mm with 4 row of pins
2) EPM570ZM144C7N 440 macro, 116 io, 570 logic blocks, 9.0ns
7x7mm with 4 rows of pins
Both cost a little more for the ic but not to much. (2) can only handle max speed of 160 so overclocking prop to 100 would not be an option. I have not checked what pins are where but with both pin layouts i would probably have to switch to a more expensive board layout. At present i am using via depths of 1..6 and 2..6 for either of those options if the middle is not entirely ground i would need 1..6,3..6,4..6,5..6 which doubles the amount of work for the assembler.
42 pins for Sram: 20 address + 16 data + 4 control (OE,WE) + 4 chip select (CE for 4 chips), ,BHE,BLE tied low
4 pins for winbond flash(W25X64VZEIG): cs,do,clk,dio + wp, hold tied high
29 pins for prop: xin + reset + 27 (p0..15 + p21..31) (17..20 on 240 if 570 is pin compatible)
1 pin clock oscillator input (2 for crystal connection)
what about not trying to tie to 28-31 since these have limited usage. if we boot from eeprom stil it can have a loader to load anything you want using a different set of pins and still leaving 28-29 for i2c devices and 30-31 for programing the prop+serial with other devices. in that case
p0..p26 + p27..30 for 240
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The video generator however, seems to be working on a separate schedule from the COG and PLLA ... this is what I see with a scope, and I don't see any way to control it ... I could be wrong. Also WAITVID is a HUB instruction like RDLONG, but that can be managed.
@mctrivia, Why don't you just route the P28..31 pins transparently through the CPLD? This would allow control over the behavior of these pins. After boot, they could be anything you want with an appropriate CPLD configuration register bit set.
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--Steve
Propeller Tools
- prop: why p21..31 and not p24..31. With p0..15 two configurations are possible: 16bit data bus and 8bit databus+ 8IO available for other purposes. P24..31 as control lines are enough even if you consider double function the p28..31.·On the other side having a entire clean byte/port available exclusively as IO it's useful when dealing with native video/vga where you can chose the outputs only in groups. In case of cpld vga output you will have p0..7(data bus to cpld), p8..15(video dac), P16..17 (v/h sync) one from P24..31 (pixelclock)
- flash: the one you have choosen is max dual bit, mine was 4 bit. The signals you have tied high for me was data lines. Having my flash 50MB/s capacity (4 bits @100MHz), 25Mword/s and the ram 100Mword/s it was supposed to make background (DMA) transfers from flash to sram while it is outputing video and/or prop is accessing it (eg. changing the background picture with a new one stored in flash). It's true a vga screen will be no more than 2MB but I you have all the ram filled with graphics there is no place for LMM(XMM) code. If the design will be good I foresee some Catalina development on it (maybe also ImageCraftC, some clever code porting from Morpheus)
As per cpld size (I have not undestood what functions you want from it) if you want to implement half the functions I have discussed here I think that you should forget the 240 and focus on 570 (maybe 1270) and search a package that fit both. Prop<>ram, flash>ram, ram>vga,·spiboot,·means a virtual 3 port implementation to the ram interface, state machines for boot and flash>ram then if you want parallel flash(sd) access a serializer/deserializer. I am quite sure 240 is not enough.
BTW: cpld 1) is missing a G after the 570; cpld 2) is Z, the second last digit (7) indicate the speed grade search for a G device (speed garade 5 or below) and there will be no problems for the speed.
http://www.buyaltera.com/scripts/partsearch.dll/multisearch?site=ALTERA&lang=EN&keywords=EPM570G
http://www.buyaltera.com/scripts/partsearch.dll/multisearch?site=ALTERA&lang=EN&keywords=EPM1270G
PEDIT: BTW the devices without G and Z are equal to the G ones (same frequency domain) but with integrated (built-in) 1.8V regulator so can be supplied with 3.3V
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· Propeller Object Exchange (last Publications / Updates)
Post Edited (dMajo) : 8/27/2009 6:33:50 PM GMT
240 short 1
570 short 5
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the 4bit flash does not come in 8MB size and I would like the entire ram contents to be capable of backing up.
the ram to vga as I understand it does not use the prop at all but since with this package the only link to the real world is the prop pins your output would have to be on one of the pins routed to a prop pin the prop will just not have to use those pins.
the 1270 and 570 do both come in 256MBGA package i will check out if the pin orientation makes possible for use without super increasing price or leaving not enough room for flash.
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using a SN74LVC1G139YZPR for the ram chip selects would save 2 pins.
Do we need 8 bit write capabilities? or can the cpld simulate 8 bit access with 16 bit hardware?
I can fit the 570 or 1270 but not all IO would be accessible but they both have way more then needed so that should not be a problem. They are pricey though EPM1270M256C5N is $34 and the non Z 570 are not available in small quantities.
pro/con
EPM1270M256C5N - $34.08
EPM570M256C5N - $26.23 minimum quantity 176
EPM570M100C5N - $16.07 short even more pins more logic
EPM240M100C5N - $7.25 short a few pins and little logic
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20 Address Lines
16 Data Lines
4 control (oe,we,bhe,ble)
2 chip select(ce through SN74LVC1G139YZPR)
4 pin flash
30/33 pins for prop: 570: reset + p0..p28
240: reset, p0..p31
with 240 extra pin used for an usd card header along with spi pins.
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The 4bit flash: 8MB and 16MB are under design and planned soon (datasheet already available)
ram to vga: yes, on the other side if you want classic vga you still need 8 prop IOs, in this case is the same but they will be driven by the cpld (this way up to 1600*1200*256col @60Hz should be possible)
1270/570 it will be nice. 240 is not enough. It will be good to have the opportunity to move to 1270 without pcb rework (if 570 still not enough). in this case you will have two products cheeper (less performance), more expensive (more performance), with several choices on ram/flash sizes
SN74LVC1G139YZPR: not have had a look at datasheet but probably it's a decoder. If so I agree
8bits writes: you need this otherwise you will loose more then half the bandwidth to the ram. Specially when making cpld vga you are forced to 8 bit data bus on the prop and most of the operations will be writings to the ram
570 & small qty: I have seen it on altera site, but have not looked arround for other distributors (maybe ...)
PEDIT: added datasheet
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· Propeller Object Exchange (last Publications / Updates)
Post Edited (dMajo) : 8/28/2009 7:28:38 AM GMT
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--Steve
Propeller Tools
- Propalyzer: Propeller PC Logic Analyzer
- BMA: An on-chip PASM Debugger
- SPUD: Spin Source Level Debugger
Post Edited (jazzed) : 8/27/2009 11:05:19 PM GMTYes chip mentioned is tiny 2 to 4 decoder.
If I can find in smaller quantities 570 in 256mbga would be probably best. Lots of io.
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--Steve
Propeller Tools
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· Propeller Object Exchange (last Publications / Updates)
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I would trade some propeller pins for the extra cost of the CPLD ($16 to you $40+ to the customer) unless the device is too small.
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--Steve
Propeller Tools
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I presume now all the prop pins will be routed to cpld?
Regarding the SD and unused cpld IOs (I have seen your other thread): do you have enough space to place 10 pads more (5 on top and 5 on bottom side/edge, without pins, just pads) connected to the cpld? It will be up to the end user to solder wires/pins on them to enjoy of the additional IOs (SD or whatever he wants).
One request more: after all that there is some spare pins still available? If so it will be nice to have just some of the prop pins connected to two of the cpld. To one directly and to the other through a resistor. This allows set/reset comm on single pin (eg. cpld outputs a state to the prop through a resistor, when prop perform the required action output the opposite state on the same pin that before was an input, cpld know this because on the directly connected pin reads the opposite state as on the other one going through the resistor). I will think over this during the weekend and let you know which pop pins are the best maches to do this. (maybe not needed because of the bus-hold feature, need to reserch what happens during por cycles)
BTW: prop reset should go only to the cpld with a pulldown resistor and the cpld reset should instead to the dip40. if enough room a jumper between the two will be appreciated.
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· Propeller Object Exchange (last Publications / Updates)
160 io some get wasted to route but still lots left.
Was hoping to find a fine pitch board connector that could go over end with jtag and 20+io
I may be able to do a few double pins. Space for resister is restriction
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Whats the rationale behind routing all the Prop's pins through the MaxII?
Also will the SuperProp be proprietary or will the VHDL and schematics be open source?
Walt
Schematic will be available to aid development but pcb and schematic are my ip
As for rational to wrote pins to cpld and prop there is 2 reasons.
1) max versatility for prop to ram communication
2) cpld can take some of workload(ie generate video from ram)
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4-JTAG
2-Power
14-IO
the problem is i need 4.2mm past last device to use these headers.
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2) cpld can take some of workload:
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· Propeller Object Exchange (last Publications / Updates)
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