Just found the price of the altera design software. $1000 that is probably a little steep for most of us. I am guessing you can probably load code on with a free programmer of source but would be nice if most people could look through the CPLD code and not just use what is available.
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There is also a free version of Altera's Quartus that you can download and can pretty do anything you need from glue logic to rolling your own microprocessor.
dMajo you wanted double buffer capability. with the ram I chose you can control upper and lower byte seperately. If I have 4 pins as such
(all pins are inverted but left out for easier reading)
CPLD:we0,we1,bc0,bc1
ram0:we0-we,bc0-lb,bc1-ub
ram1:we1-we,bc1-lb,bc0-ub
ram2:we0-we,bc0-lb,bc1-ub
ram3:we1-we,bc1-lb,bc0-ub
then you could
*write 8bits to ram 1 while reading 8bits from ram 0
or
*read 16 bits from ram 0 or write 16bits to ram0
just by manipulating those pins and the appropriate chip select pins.
This would leave the 80 io lines distributed 45 for RAM, 34 for PROP, 1 for High Speed Clock:
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Ale said...
I think it could be very useful if either of those solutions could be used to get higher resolutions say 800x600 or 1024x768, 640x480 only needs a 25 MHz clock . Maybe the cpld could have a latch to keep the data available for some time while in between the SRAM is read or written again ?
It can be done (I suppose). I have made a dual port ram (with cpld) out of a normal sram: I was able to read data from the ram at the same time while the second prop was writing them.
That's the reason I think that it is possible. I don't now really deep the prop video hardware right now, but I immagine that the V/H signal frequency is not a problem. What I have understood from other posts is the lack of memory that make high resolutions and high colors impraticable. The idea is to have a dac formed the same way as on the prop but on cpld (eg. 3/3/2 to increase the color depth). Now by using the single ended pll mode instead of the video one the counter apin can provide pixel clock to the cpld that is latching ram contents on the dac while v/h sync will be provided directly by the prop. Some other cog (or another prop) can read and write to the ram at the same time transparently. Now 1024*768(256 colors)=786.432Bytes and 1600*1200(256 colors)=1.920.000Bytes and the ram I have choosen is 2MB (1M*16bit)
I suspect that more cogs can access the ram at the same time (my target is infact to have a quad-port ram connected through 4 busses to four props). Quiet sure if reading words (remember I use a 10nS 16bit ram: word reading at 100MHz while the best single cog capabilities is 20M(80/4)). Dual-port and VGA output latch should be also doable.
For the moment the dual port is working and capable to deliver/receive·data to/from every prop instruction cycle·(4 prop clocks) to both the props at the same time. Remember that the cpld is running at 160M delivering divided 80M clock to props (so pll are not used for the system clock).
mctrivia said...
Just found the price of the altera design software. $1000 that is probably a little steep for most of us. I am guessing you can probably load code on with a free programmer of source but would be nice if most people could look through the CPLD code and not just use what is available.
waltc has answered before, while I was quoting the previous post. Altera MaxII family is doable with the free web downloadable edition. The only thing it is missing is·the full IP stuff library but most of them are not for MAXII family.
dMajo what do you think of my pin out? You would get 4MB or 8MB of double buffered ram in dip 40 package with a prop. I think it would do everything you are looking for except with fewer io lines since I have only 1 cpld, and 1 prop.
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dMajo you wanted double buffer capability. with the ram I chose you can control upper and lower byte seperately. If I have 4 pins as such
(all pins are inverted but left out for easier reading)
CPLD:we0,we1,bc0,bc1
ram0:we0-we,bc0-lb,bc1-ub
ram1:we1-we,bc1-lb,bc0-ub
ram2:we0-we,bc0-lb,bc1-ub
ram3:we1-we,bc1-lb,bc0-ub
then you could
*write 8bits to ram 1 while reading 8bits from ram 0
or
*read 16 bits from ram 0 or write 16bits to ram0
just by manipulating those pins and the appropriate chip select pins.
This would leave the 80 io lines distributed 45 for RAM, 34 for PROP, 1 for High Speed Clock:
Have to go now so I have no time to think on your pin assignments but seems going to the right way. Supposing the rams are on the same bus we can speak just as it is a bigger single chip one, the cpld will take care on address decode and CS and other handshake signals management. Now with a single and fast ram 16 wide but accessible also at 8 bit and all prop pins connected to the cpld it's really up to the final user the choice on what to do.
But you have misunderstood the double buffering with dual-port. Having the ram running faster than the prop you can multiplex the same chip: read and write to the same chip at the same time looking from prop side while from the ram point of view this is of course sequential reads on random locations.
Now going back to your desing I can see a wonderful graphic engine: one cog outputing vga h/v sync and cpld pixel clock, cpld providing dac functionality through a 8bit(3/3/2) latched port and up to 2 cogs writing/reading ram at the same through a virtual dual-port implementation inside the cpld.
I must understand some things before on prop video hardware since this is really bad explained on prop manual/datasheet. Parallax is only saying that to make this you must do this. They are not providing informations on how the hardware works nor how the counter is interconnected with the video side. (I know of the pixel clock because of another forum user: what it cost to them to draw a line from the plla interconnection to the counter output mux to the video circuitry showing how the clock is routed to the video hardware.) In the manual they say the opposite what they say in the datasheet. In one case the color bytes are 6 bits and v/h sync are dont care since the hardware is providing them automatically. In the other case they say that v/h sync it's up to you based on the bits of the color register (all the 4 bytes 8 bits are multiplexed out of the port. This will allow higher speed data writes to the ram. On the other side using one pin of the composite video mode can allow serial high speed address delivery to the cpld. Maybe I am a newbie, maybe I am wrong, but the data provided by Parallax on this argument is really less than zero IMO. If you look at serial/spi/i2c/timer hardware of eg.8052 core microcontrollers you will find much better informations, timing diagrams ...
I will have a deeper look starting from the middle of the next week. Maybe here Baggers or PhiPi, Chip if is not too busy with PropII, can help. Any other counter/video guru is welcome
If this thread is stemming from the challenge that I made in another thread, my idea was to have a stand-alone memory board that could be accessed by some kind of connector (ribbon cable?) to a proto board or something along those lines. Of course the drivers that would be necessary for accessing the memory module would be included. A stand-alone memory board could be used with a breadboard, proto board, or the new propeller board that GadgetGangters just introduced. It would also be a plus if everything was socketed on the memory board, and the memory chips could be replaced with bigger memory chips. My intent was to have an apples to apples comparison, then, when all was said and done, we would know how the pricing stacked up.
If this thread is in regards to something else, then disregard what I just wrote.
Yes and no. It has morefed to make more useful. It would be silly to build a board like mit has done. By changing the way it is done I have made it much smaller a and more versatile.
Prop does not need to be on the board so physical double buffered would allow for maximum versatility.
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Yea, but then how can we ever resolve the issue of greed? I think that mit has a good concept with the memory board. It is always easy enough to knock somebodies product by saying you can do it cheaper, and better, but your product is not even close to what you are knocking, just saying!
I still think that a stand-alone memory board via connectors would be an easier sell, for those that are into such a product, than what you are proposing.
Who cares about greed. If MIT had a working AI people would happily pay $10,000 for there module. They don't though. The point is not to duplicate someone elses design but to give a product to do what people want at a price they are willing to pay. I am all for people getting rich that is not my purpose for this project. My purpose is to make a product I can afford to buy myself.
The product I have design is capable of doing everything that MIT's does. It can be used separately with a ribbon if you like. The difference is by making the architecture open source it allows for much more diversity. MIT could write the code to make my module act like theirs and sell my modules with there code on it I will not stop them.
However not everyone wants there ram for the same purpose of MIT. MIT has optimized there board for bulk transfers.
My board can be optimized for what ever you want:
*Bulk transfer
*Random Access
*Dual Port...
However unlike MIT which is stuck to some mystique secret 12 bit bus that they will not tell how it works, with this module you could use anything from 1 to 32 bit bus, using any pins you want, or ignore the prop altogether and access it at 100MHz from some other processor. All in a space no bigger then the 40pin dip prop itself.
Also unlike MIT's module this module could even preprocess the data for you, keeping pointers and allow for accessing data relative to last byte read or better yet accessing the byte stored at last 3 bytes xored together + 6. Depending on your application you could have this module feed you every byte you want without you sending any info to it(i.e. video driver receive sync pulse then just keep streaming necessary bits.)
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Well I have run all the traces for the ram. all that is left is connecting everything to the CPLD.
board would unfortunately have to be 6 layers with 4mil traces/clearance. Prop is not on board anymore but a dip40 prop will fit through board.
My Costs:
*$720 for PCB Panel(makes 90)
*$2090 for RAM(makes 25 8MB/50 4MB/100 2MB)
*$258 for CPLD(makes 25)
*$1 for Caps(makes 25)
*$200 for Assembly.
$3069
Now Assuming 80% pass rate after assembly I could build 20 8MB boards for $164.
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Had to. To many via in the way but dip 40 prop fits on top.
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I think you have done some mistakes on your schematic. Since the four ram chips share the same data/address bus then only the CE should be independent: the OE,WE,LB,UB should be connected in parallel like address/data. You can not read/read or read/write to two chips at the same time since the data/address bus is common.
So we should end speaking of double buffering and swap to multiplexing. Independently of how many chips are on the bus you can access only one at the same time. So virtually we have one big chip that is the sum of all the real. Now if the cpld+ram is the server and props are clients: if the server is running at double speed than the cliens, it can provide data to two clients in real time without bandwidth looses (from the client point of view: this is why I supply the cpld with 160MHz and let it deliver the 80MHz to props). If by double buffering you intend like in video writing to one screen while displaying the other this is again virtually done in such design: It's enough to provide the "cpld video latch circuitry" with a dynamic base and loop counter registers, considering that the prop can access to any ram location at the same time: so it's up to the user to choose where to write and/or read and by changing the base address what to show.
dMajo said...
... For the cpld I am considering xilinx coolrunner ii (XC2C128/XC2C256/XC2C384) and altera max ii (epm570/epm1270) both in TQ144 package. ...
BTW Have you noted that I have chosen two/three possibilities that fit the same package? This is because in cpld/fpga design I defend myself but I am not a guru. I always look for more possibilities. The important things for me, of course, is the needed IOs and the final result, but when it comes to product terms/macrocells/logic elements it's difficult to me to size them before. I always develop to a bigger one and then go lower for cost reduction: because you have chosen Altera EPM240F100C4N(192 Macroscells, 240 Logic Blocks, 80 IO pins) I will suggest you to consider only the 76 IOs available to the EPM570 (same package) because 240 seems not enough to me.
Considering that I was able to boot the prop from a Winbond spi flash in 4 bit mode (eeprom emulation done in cpld) it will be nice if you can find a place (socket) also for this one. You can gain much bigger space than the prop 32K eeprom, and cpld can provide some kind of ram shadowing (block copies from flash to ram) for code (lmm stuff and similar) or graphics (stored bitmaps, backgrounds, pre-designed GUI/menu systems). In this case the spi flash needs independent connection to the cpld; the prop can still access the flash through a classic spi driver through the cpld<->prop bus.
what about for a faster controller then the prop or 2 props at once?
we0=0
we1=1
bs0=0
bs1=1
cs0=0
cs1=0
cs1=1
cs2=1
will set ram0 to write D0..D7 to Ram and Ram1 to read D8..D15 from Ram or have I missed something?
To bad this could not work for your use large quantities would help.
Yes I have the equipment and expertise to solder BGA components. If I can make enough at once I will have assembled by automated machinery.
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i guess it would be more usefull to drop the ability to do real dual port ram and add a 8MB Flash chip9M25PX64-VZM6TP) would be tight fit though not sure if posible.
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Not sure if dmajo is for sale or not. Mine will be very cheap for early buyers willing to write cpld code little more later so I can keep stock.
I need to sell 20 imedietly to get wifes permission to make.
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I have modified your schematic (because it was easier to me) to let me explain better. Maybe our misunderstandings was due to my bad english. With the attached design you can read/write at the same time to the ram·from both the prop chips while the cpld is outputing a vga screen.
Eg. from cpld point of view:
both·the props can simultaneously write/read the ram at 20MB each, while the cpld is outputing at 50MB on VGA (1024*768*60Hz=47.1MHz) @256colors
both·the props can simultaneously write/read the ram at 10MB each, while the cpld is outputing at 80MB on VGA (1280*1024*60Hz=78.6MHz) @256colors
BTW:
If prop pins P28/P29 are connected to the cpld the prop can boot from spi flash instead of the 32k eeprom.
Background (DMA) copy function (from spi flash to ram) is available: eg. 1)SpiAddress,RamAddress,NumberOfBytes; 2)Go
waltc said...
Let me get this straight both Mctrivia and dMajo have competing CPLD based memory boards for sale?
Mine is not intended directly for forum sales. It is also not exclusively a ram expansion. I need a small and powerful microntroller board to be used in several (finished) products (target product availability 1st quarter 2010). For some of them I already have a long term agreement but I hope that sales can increase. Because of this the idea is to make a small daughterboard with an eurocard or dimm connector and have several motherboards with specialized·IO circuitry and connectors upon projects needs. This will lower my costs because the daugterboard will be produced in larger number of units. For some low volume products the moderboards will be homemade.
That sad I will have no problems to design a propdemo like motherboard with a connector to hold the daughterboard and make it available for forum users if enough interest nor I will have problems give away the gerber files. I consider IP the idea behind the projects and the software running on that products (prop/cpld) not the hardware design as itself. I will release also the low level prop drivers, not sure under which license, but as already stated no secrets in the low level
i can get the flash and clock in but will have to extend the board slightly past the dip 40 specs so the crstal can be mounted on the top side of the board beside the dip 40 prop.
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Jazzed will a slightly longer then dip40 pack board work for you?
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mctrivia said...
Jazzed will a slightly longer then dip40 pack board work for you?
How much longer? No more than 5mm or so extra. Is this the same schematic or a different one?
If a CPLD connection, what is the Propeller/CPLD interface?
Was planning only as wide as crystal itself so 5mm or so.
Just found out my manufacturer will do blind vis. So 16mb is now possible at sacrifice of flash or prop on board is possible.
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Holy Moly [noparse]:)[/noparse] Guess I need to get BigSpin working [noparse]:)[/noparse]
If the CPLD is between the Prop and SRAM DBUS, the CPLD latency will make the 12ns SRAM much less usable for high performance although the pin-out would be flexible (8 -vs- 16 data for example). I guess it would be good to offer an optional lower cost speed grade if possible. I'm very concerned about current draw though. leaving a PropPlug connected when the rest of board power is off could cause PropPlug to fail. This has happened to me.
10ns SRAM 4.7ns CPLD. CPLD can prefetch next byte or word in block transfers and the hit in speed is not that much for true random compared to number of pins needed.
Which would be preferred? 16MB of RAM(at almost double the price) or on board prop. I am thinking prop because I can then shrink board down to fit dip40 package almost perfectly and still get a 8MB flash chip in there for backing up ram contents.
Also I can't find a 160MHz Crystal. It should be possible to make a PLL on the CPLD and use a 5MHz Crystal like normal and have the CPLD run the Prop to have perfectly in sync.
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Ok. So you have all Propeller pins connected to CPLD?
It would be sweet to have word at a time transfers for burst access where extra I/O is not important.
Either that or byte at a time transfers where extra I/O is important. Too bad uSD is too big for DIP40.
I think on-board Prop would be an attractive first option with 8MB Flash / 8MB SRAM.
Will CPLD be big enough to register address/data and do counters too ?
Yes I will connect all prop pins. They can be programed hiz if used for other use.
This way also cpld could take over outputs also and generate video or other things.
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Comments
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There is also a free version of Altera's Quartus that you can download and can pretty do anything you need from glue logic to rolling your own microprocessor.
dMajo you wanted double buffer capability. with the ram I chose you can control upper and lower byte seperately. If I have 4 pins as such
(all pins are inverted but left out for easier reading)
CPLD:we0,we1,bc0,bc1
ram0:we0-we,bc0-lb,bc1-ub
ram1:we1-we,bc1-lb,bc0-ub
ram2:we0-we,bc0-lb,bc1-ub
ram3:we1-we,bc1-lb,bc0-ub
then you could
*write 8bits to ram 1 while reading 8bits from ram 0
or
*read 16 bits from ram 0 or write 16bits to ram0
just by manipulating those pins and the appropriate chip select pins.
This would leave the 80 io lines distributed 45 for RAM, 34 for PROP, 1 for High Speed Clock:
RAM
16 IO Lines
20 Address Lines
4 Chip Enable Lines
1 Output Enable Line
2 Write Enable Lines
2 Byte Selection Lines
PROP
32 IO Lines
1 Crystal
1 Reset
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That's the reason I think that it is possible. I don't now really deep the prop video hardware right now, but I immagine that the V/H signal frequency is not a problem. What I have understood from other posts is the lack of memory that make high resolutions and high colors impraticable. The idea is to have a dac formed the same way as on the prop but on cpld (eg. 3/3/2 to increase the color depth). Now by using the single ended pll mode instead of the video one the counter apin can provide pixel clock to the cpld that is latching ram contents on the dac while v/h sync will be provided directly by the prop. Some other cog (or another prop) can read and write to the ram at the same time transparently. Now 1024*768(256 colors)=786.432Bytes and 1600*1200(256 colors)=1.920.000Bytes and the ram I have choosen is 2MB (1M*16bit)
I suspect that more cogs can access the ram at the same time (my target is infact to have a quad-port ram connected through 4 busses to four props). Quiet sure if reading words (remember I use a 10nS 16bit ram: word reading at 100MHz while the best single cog capabilities is 20M(80/4)). Dual-port and VGA output latch should be also doable.
For the moment the dual port is working and capable to deliver/receive·data to/from every prop instruction cycle·(4 prop clocks) to both the props at the same time. Remember that the cpld is running at 160M delivering divided 80M clock to props (so pll are not used for the system clock).
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· Propeller Object Exchange (last Publications / Updates)
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· Propeller Object Exchange (last Publications / Updates)
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
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But you have misunderstood the double buffering with dual-port. Having the ram running faster than the prop you can multiplex the same chip: read and write to the same chip at the same time looking from prop side while from the ram point of view this is of course sequential reads on random locations.
Now going back to your desing I can see a wonderful graphic engine: one cog outputing vga h/v sync and cpld pixel clock, cpld providing dac functionality through a 8bit(3/3/2) latched port and up to 2 cogs writing/reading ram at the same through a virtual dual-port implementation inside the cpld.
I must understand some things before on prop video hardware since this is really bad explained on prop manual/datasheet. Parallax is only saying that to make this you must do this. They are not providing informations on how the hardware works nor how the counter is interconnected with the video side. (I know of the pixel clock because of another forum user: what it cost to them to draw a line from the plla interconnection to the counter output mux to the video circuitry showing how the clock is routed to the video hardware.) In the manual they say the opposite what they say in the datasheet. In one case the color bytes are 6 bits and v/h sync are dont care since the hardware is providing them automatically. In the other case they say that v/h sync it's up to you based on the bits of the color register (all the 4 bytes 8 bits are multiplexed out of the port. This will allow higher speed data writes to the ram. On the other side using one pin of the composite video mode can allow serial high speed address delivery to the cpld. Maybe I am a newbie, maybe I am wrong, but the data provided by Parallax on this argument is really less than zero IMO. If you look at serial/spi/i2c/timer hardware of eg.8052 core microcontrollers you will find much better informations, timing diagrams ...
I will have a deeper look starting from the middle of the next week. Maybe here Baggers or PhiPi, Chip if is not too busy with PropII, can help. Any other counter/video guru is welcome
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· Propeller Object Exchange (last Publications / Updates)
If this thread is in regards to something else, then disregard what I just wrote.
Prop does not need to be on the board so physical double buffered would allow for maximum versatility.
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
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I still think that a stand-alone memory board via connectors would be an easier sell, for those that are into such a product, than what you are proposing.
The product I have design is capable of doing everything that MIT's does. It can be used separately with a ribbon if you like. The difference is by making the architecture open source it allows for much more diversity. MIT could write the code to make my module act like theirs and sell my modules with there code on it I will not stop them.
However not everyone wants there ram for the same purpose of MIT. MIT has optimized there board for bulk transfers.
My board can be optimized for what ever you want:
*Bulk transfer
*Random Access
*Dual Port...
However unlike MIT which is stuck to some mystique secret 12 bit bus that they will not tell how it works, with this module you could use anything from 1 to 32 bit bus, using any pins you want, or ignore the prop altogether and access it at 100MHz from some other processor. All in a space no bigger then the 40pin dip prop itself.
Also unlike MIT's module this module could even preprocess the data for you, keeping pointers and allow for accessing data relative to last byte read or better yet accessing the byte stored at last 3 bytes xored together + 6. Depending on your application you could have this module feed you every byte you want without you sending any info to it(i.e. video driver receive sync pulse then just keep streaming necessary bits.)
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
Want to make projects and have Gadget Gangster sell them for you? propmod-us_ps_sd and propmod-1x1 are now available for use in your Gadget Gangster Projects.
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Post Edited (mctrivia) : 8/22/2009 8:33:50 PM GMT
board would unfortunately have to be 6 layers with 4mil traces/clearance. Prop is not on board anymore but a dip40 prop will fit through board.
My Costs:
*$720 for PCB Panel(makes 90)
*$2090 for RAM(makes 25 8MB/50 4MB/100 2MB)
*$258 for CPLD(makes 25)
*$1 for Caps(makes 25)
*$200 for Assembly.
$3069
Now Assuming 80% pass rate after assembly I could build 20 8MB boards for $164.
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
Want to make projects and have Gadget Gangster sell them for you? propmod-us_ps_sd and propmod-1x1 are now available for use in your Gadget Gangster Projects.
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Post Edited (mctrivia) : 8/23/2009 5:39:51 AM GMT
Welcome back and great work!
I would pay $164 for an 8MB board that will do at least 5MB/Sec. It sound's like a great deal.
I didn't see a prop on it. Did you drop the prop?
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
Want to make projects and have Gadget Gangster sell them for you? propmod-us_ps_sd and propmod-1x1 are now available for use in your Gadget Gangster Projects.
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I think you have done some mistakes on your schematic. Since the four ram chips share the same data/address bus then only the CE should be independent: the OE,WE,LB,UB should be connected in parallel like address/data. You can not read/read or read/write to two chips at the same time since the data/address bus is common.
So we should end speaking of double buffering and swap to multiplexing. Independently of how many chips are on the bus you can access only one at the same time. So virtually we have one big chip that is the sum of all the real. Now if the cpld+ram is the server and props are clients: if the server is running at double speed than the cliens, it can provide data to two clients in real time without bandwidth looses (from the client point of view: this is why I supply the cpld with 160MHz and let it deliver the 80MHz to props). If by double buffering you intend like in video writing to one screen while displaying the other this is again virtually done in such design: It's enough to provide the "cpld video latch circuitry" with a dynamic base and loop counter registers, considering that the prop can access to any ram location at the same time: so it's up to the user to choose where to write and/or read and by changing the base address what to show.
BTW Have you noted that I have chosen two/three possibilities that fit the same package? This is because in cpld/fpga design I defend myself but I am not a guru. I always look for more possibilities. The important things for me, of course, is the needed IOs and the final result, but when it comes to product terms/macrocells/logic elements it's difficult to me to size them before. I always develop to a bigger one and then go lower for cost reduction: because you have chosen Altera EPM240F100C4N(192 Macroscells, 240 Logic Blocks, 80 IO pins) I will suggest you to consider only the 76 IOs available to the EPM570 (same package) because 240 seems not enough to me.
Considering that I was able to boot the prop from a Winbond spi flash in 4 bit mode (eeprom emulation done in cpld) it will be nice if you can find a place (socket) also for this one. You can gain much bigger space than the prop 32K eeprom, and cpld can provide some kind of ram shadowing (block copies from flash to ram) for code (lmm stuff and similar) or graphics (stored bitmaps, backgrounds, pre-designed GUI/menu systems). In this case the spi flash needs independent connection to the cpld; the prop can still access the flash through a classic spi driver through the cpld<->prop bus.
BTW: will you solder bgas by yourself?
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· Propeller Object Exchange (last Publications / Updates)
we0=0
we1=1
bs0=0
bs1=1
cs0=0
cs1=0
cs1=1
cs2=1
will set ram0 to write D0..D7 to Ram and Ram1 to read D8..D15 from Ram or have I missed something?
To bad this could not work for your use large quantities would help.
Yes I have the equipment and expertise to solder BGA components. If I can make enough at once I will have assembled by automated machinery.
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
Want to make projects and have Gadget Gangster sell them for you? propmod-us_ps_sd and propmod-1x1 are now available for use in your Gadget Gangster Projects.
Need to upload large images or movies for use in the forum. you can do so at uploader.propmodule.com for free.
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
Want to make projects and have Gadget Gangster sell them for you? propmod-us_ps_sd and propmod-1x1 are now available for use in your Gadget Gangster Projects.
Need to upload large images or movies for use in the forum. you can do so at uploader.propmodule.com for free.
I need to sell 20 imedietly to get wifes permission to make.
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
Want to make projects and have Gadget Gangster sell them for you? propmod-us_ps_sd and propmod-1x1 are now available for use in your Gadget Gangster Projects.
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I have modified your schematic (because it was easier to me) to let me explain better. Maybe our misunderstandings was due to my bad english. With the attached design you can read/write at the same time to the ram·from both the prop chips while the cpld is outputing a vga screen.
Eg. from cpld point of view:
BTW:
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· Propeller Object Exchange (last Publications / Updates)
Post Edited (dMajo) : 8/24/2009 8:31:08 PM GMT
That sad I will have no problems to design a propdemo like motherboard with a connector to hold the daughterboard and make it available for forum users if enough interest nor I will have problems give away the gerber files. I consider IP the idea behind the projects and the software running on that products (prop/cpld) not the hardware design as itself. I will release also the low level prop drivers, not sure under which license, but as already stated no secrets in the low level
http://www.elbag.net/it/modulari-new.htm
http://www.italtronic.com/prod.asp?seg=4&cat=12&prod=91
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· Propeller Object Exchange (last Publications / Updates)
Post Edited (dMajo) : 8/24/2009 9:19:31 PM GMT
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
Want to make projects and have Gadget Gangster sell them for you? propmod-us_ps_sd and propmod-1x1 are now available for use in your Gadget Gangster Projects.
Need to upload large images or movies for use in the forum. you can do so at uploader.propmodule.com for free.
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
Want to make projects and have Gadget Gangster sell them for you? propmod-us_ps_sd and propmod-1x1 are now available for use in your Gadget Gangster Projects.
Need to upload large images or movies for use in the forum. you can do so at uploader.propmodule.com for free.
If a CPLD connection, what is the Propeller/CPLD interface?
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--Steve
Propeller Tools
Just found out my manufacturer will do blind vis. So 16mb is now possible at sacrifice of flash or prop on board is possible.
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
Want to make projects and have Gadget Gangster sell them for you? propmod-us_ps_sd and propmod-1x1 are now available for use in your Gadget Gangster Projects.
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If the CPLD is between the Prop and SRAM DBUS, the CPLD latency will make the 12ns SRAM much less usable for high performance although the pin-out would be flexible (8 -vs- 16 data for example). I guess it would be good to offer an optional lower cost speed grade if possible. I'm very concerned about current draw though. leaving a PropPlug connected when the rest of board power is off could cause PropPlug to fail. This has happened to me.
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--Steve
Propeller Tools
Which would be preferred? 16MB of RAM(at almost double the price) or on board prop. I am thinking prop because I can then shrink board down to fit dip40 package almost perfectly and still get a 8MB flash chip in there for backing up ram contents.
Also I can't find a 160MHz Crystal. It should be possible to make a PLL on the CPLD and use a 5MHz Crystal like normal and have the CPLD run the Prop to have perfectly in sync.
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
Want to make projects and have Gadget Gangster sell them for you? propmod-us_ps_sd and propmod-1x1 are now available for use in your Gadget Gangster Projects.
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Post Edited (mctrivia) : 8/25/2009 4:07:12 AM GMT
It would be sweet to have word at a time transfers for burst access where extra I/O is not important.
Either that or byte at a time transfers where extra I/O is important. Too bad uSD is too big for DIP40.
I think on-board Prop would be an attractive first option with 8MB Flash / 8MB SRAM.
Will CPLD be big enough to register address/data and do counters too ?
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--Steve
Propeller Tools
Yes I will connect all prop pins. They can be programed hiz if used for other use.
This way also cpld could take over outputs also and generate video or other things.
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
Want to make projects and have Gadget Gangster sell them for you? propmod-us_ps_sd and propmod-1x1 are now available for use in your Gadget Gangster Projects.
Need to upload large images or movies for use in the forum. you can do so at uploader.propmodule.com for free.
What sort of data xfer rates have you gotten out your prototype?
Also did you use Verilog or VHDL?
Walt