At this point no prototype just digital simulation. Trying to see what I can fit in the size jazzed proposed. But I see no reason why you would not be able to max specs. Bga is ideal package for reflection and I have shielded all signal traces.
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@waltc, there is a prototype and is more or less like the above schematic exept that have two spi flash so that both the props can boot at the same time. The virtual dual port implementation was tested with this kind of code:
Prop 1 Prop2
mov outa,#1 mov one,ina
mov outa,#2 mov two,ina
mov outa,#3 mov three,ina
. .
. .
. .
mov outa,#63 mov sixtythree,ina
mov outa,#64 mov sixtyfour, ina
one RES 1
two RES 1
.
.
this is like burst reads, the two props was accessing the sram the same time, the bandwidth (if math is not an opinion) is 20MB/s (sram to·cog register). The cpld design has no sram contention circuitry (semaphores, looks ...) because the ram access is sequential and hierarchical (if both read the same location·at the same time both read the same data, if both write prop2 overwrites prop1 data: in the cpld pipeline prop1 cames first prop2 is second of course regarding the same ram address)
Regarding data transfer speed (when I' have back my hardware and my laboratory) I need to test waitvid (with forum support, both for hardware and PASM):
ram address delivery through composite video circuitry (@160MHz) maybe two pins (SSI): to improve random access bandwidth
ram write data delivery through vga video circuitry (if all 8 bits 6color and 2sync are multiplexed out): to improve write speed
@Jazzed do you know props video hardware?
@mctrivia: There is no crystals for such speeds so I am using my laboratory generator for testing. Both the cplds (CoolRunner and MaxII) haven't PLL inside and you can not create/program it. This are builtin features (they are partially analog circuits).
The only way is to try a lower crystal with a clock multiplier (from my knowleage a xor with shorted inputs, one of two delayed will multiply by 2. The delay give the duty cycle of the doubled clock. Now with several of this stages linked serially you can multiply by·2N the clock. Need to test if it is stable in frequency and duty cycle under diferent conditions (cpld: temperature, power supply ...).
The second way is to have an external crystal oscillator.
@jazzed
The ram I have chosen is 10nS (100MHz) 5 times more the best single cog performance speaking in frequency. The rams 100MHz frequency becames 200MB/s bandwith since it is 16 bits. Now if you have a 16· bit ram that means that the data are word aligned so the need to have upper/lower byte selection (just for writing: in classic 16 ram if you want to write a byte you need to read the word, and/or mask it with your byte data and write again as word since all the 16 data bus bits are transferred to ram cell. During reads the cpld will always read a word and if a byte is required it will cache the second one for the next sequential access (if any) in order to not access again the ram and save the power (CE deselected))
jazzed said...
If the CPLD is between the Prop and SRAM DBUS, the CPLD latency will make the 12ns SRAM much less usable for high performance although the pin-out would be flexible (8 -vs- 16 data for example).
What is transfer rate you are expecting from such design?
As per cpld I am actually working on a XC2C256 CoolRunner-II CPLD·and I think (but I am not a guru) the EPM240 will not be enough so I suggested to count on 76 IOs only because that is the number available on the EPM570 in the same package. I have chosen tqfp 144 pin because it can fit both epm570 end epm1270 (and because I have never soldered bga )
Why would you need 570? For the logic blocks? It is a 1.8v ic so a voltage regulator would be needed for core. But more importantly it is a slower chip 5.7ns 155mhz
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dMajo said...
@Jazzed do you know props video hardware?
I've played with it for various non-video related things like Manchester encoding, but I'm not an expert.
dMajo said...
@jazzed
The ram I have chosen is 10nS (100MHz) 5 times more the best single cog performance speaking in frequency. The rams 100MHz frequency becames 200MB/s bandwith since it is 16 bits. ...
A 16 bit design option with byte enables is tasty for some applications. Take a CMD* bit (Command asserted low), UEN*/LEN* (byte enables so we don't have to do read/modify/write), CLK (prefer synchronous), and 16 data bits for example. This allows a 2 word command/address phase and N word data so that single cog single word access time could be on the order of 650ns (includes setup), and 12 pins are left for the user. The 8 bit alternative could use as little as 9 pins.
I'm working on different read algorithms to get better 16 bit data-rate ideas. In any event, the ability to use more than one COG requires less than 12.5ns access per transaction. Kuroneko posted a 5 COG program that gives ~20MB burst for 8 bit reads.
well this design should be able to beet 12.5nS per transaction on 8 and 12 bit sequential reads no problem. should be possible to handle 16 bit at that speed with enough of a read ahead buffer.
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mctrivia, you have a good generic idea going. Embedding the access type in the command word would solve the byte enable issue so that Propeller would only need to specify the type rather than use 2 extra pins. Example: C#AA_AAAA_AAAA_AAAA ... C is type R*/W, # is size 0/1, A is address.
mctrivia said...
Why would you need 570? For the logic blocks? It is a 1.8v ic so a voltage regulator would be needed for core. But more importantly it is a slower chip 5.7ns 155mhz
Where you get this data?
Handbook MII5V1-3.3 (08/2009)········Table 1–5,·Table 5–2··············Table 1–1..2,·Table 5–14, Table 5–23..24(part 2), Table 5–32..33
==================================================================================
MAX II······························VCCint(core) 3.3/2.5V········· max freq 304MHz·········Speed Grades -3, -4, -5
MAX IIG··························· VCCint(core) 1.8V··············· max freq 304MHz·········· Speed Grades -3, -4, -5
MAX IIZ·························· VCCint(core) 1.8V············· max freq 152/184MHz····· Speed Grades -6, -7, -8
Someone of the forum users (I can not recall right now) have written "datasheet is your best friend ..."
In my downloaded library I have the MII5V1-3.1 (12/2007) edition end it is written the same
As I said in the above post (hope you have read it including the links) I have already done some work (dual port circuitry, i2c interface switching, prop boot-up state machine, serial port switching, vector interrupt controller ...). The hardware have setup registers so that the prop can configure/change on the fly the working mode of the hardware modules. I have tested them alone (not together at the same time).
The flash to ram background copy (shadowing) will partially reuse the prop boot-up state machine to manage the spi protocol and probably became a third port on the already made dual-port ram interface.
During the above developments I had the feeling that the XC2C256 will not be enough for all of them together (epm240 is smaller) and that the options remains XC2C384, EPM570, EPM1270
I was doing from memmory and believe only the z comes in mbga package witch is the only package small enough
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1) What about using the video hardware in composite 2 color mode with a single ended plla mode having clock outputed on pina and data shifted out on the video pin? one waitvid operation can shift out (SSI - synchronous serioal interface) the 32 bits embedding the address anc command than you can done directly mov, mov, mov ... and get one byte/word (depending on the databus width between the prop and cpld) per instruction. I was able to get 20MB/s on 64 consecutive ram locations in transfers between sram and cog ram. The problem is I do not know enougs pasm tricks on how to take advantege of this speed (I am missing a way to write just one byte in the cog long preserving the other three without and/or masking)
2)what about using video hardware in vga mode and using colors register as data send interface, again with plla outputing the clock through pina, so a single waitvid can write 32 bits (8bits in four steps) to the cpld.
With the cpld it's possible to handle this comms at max prop speed (if I am not wrong: 160MHz)
@dMajo, I think having the Propeller supply the clock is a good idea. I know ctra can do 160MHz; not sure about waitvid. Guess you need that for write strobe? I wouldn't bother trying to sending some serialized address, etc... to the CPLD with it though - transaction setup performance would go in the toilette. The Kuroneko number was just for reference .... Added: as you know, it's pretty easy to sample into the cog at 20MB/s, but a little harder to get it back into hub ram which can reduce the rate a lot.
Was thinking I would tie 1 clock line to the props scl seldom used after boot
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there will be a pin on sda but i will not be trying to use that as one of the 4 clock pins.
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yes there is now a prop, and 8MB flash chip on boards. prop and flash will be optional once full scale production but for now I am sticking with everything on as only choice.
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and i was wrong the 570 is available in speed and size package i want: EPM570GM100C5N
1.8V 5.4ns
i will add the apropriate regulator. having fun finding pinout for epm570 to compare and see what is different.
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mctrivia said...
and i was wrong the 570 is available in speed and size package i want: EPM570GM100C5N
1.8V 5.4ns
i will add the apropriate regulator. having fun finding pinout for epm570 to compare and see what is different.
If you consider your board a daughterboard, a part of a bigger circuit (no connectors, no dedicated circuitry), than there is no need to provide 1.8 regulator (up to you). In this case the user that will provide the regutated 3.3v can also provide the 1.8V. Many times this can be done with single regulator with multiple outputs (eg. maxim have many of this kind).
In test&development phase the final user can also have a choice to drop down the voltage to 1.8V from a well regulated 3.3V source with two Si and one Ge diodes in series.
A second poin of view on the 1.8V the cpld core needs is: this is the same as prop II so less rework to do in the future if you want to upgrede the design.
jazzed said...
@dMajo, I think having the Propeller supply the clock is a good idea. I know ctra can do 160MHz; not sure about waitvid. Guess you need that for write strobe? I wouldn't bother trying to sending some serialized address, etc... to the CPLD with it though - transaction setup performance would go in the toilette. The Kuroneko number was just for reference .... Added: as you know, it's pretty easy to sample into the cog at 20MB/s, but a little harder to get it back into hub ram which can reduce the rate a lot.
mctrivia said...
Was thinking I would tie 1 clock line to the props scl seldom used after boot
Maybe I was misunderstood. The system clock is provided to the cpld which provide a divided one to the prop (xin). In my idea the clock taken out from pll/pina to the cpld is a parallel/serial (vga/video) data strobe not the cpld clock.
Sending serialized address idea comes to me to avoid dira switching during random reads: parallel data bus always in, serial address always out = data/address pin count reduction (less prop io used).
On my prototype I have p0..7 and p24..31 wired to the cpld because of that thoughts:
p0..7: 8bit data bus
easy to put the real value in the lower 8 bits
vector interrupt controller with priority control: the cpld will have 8 registers (where you write the vectors) 8 int inputs and one int output. When/If using this function you need to wire one of the remaining (not connected to cpld) prop pins to the cpld int out, make waitpne on that pin followed by a jmp ina
P30..31: in the cpld there is a serial switcher for the dual prop design and after a reset, for a given time, through the proptool option dtr/rts the program can be send to the appropriate prop. Then it was supposed to be the serial address bus
P28..P29 I2C bus
during boot each prop is isolated and
can boot from an eeprom which address not conflict with the other prop one (because buses are isolated)
through cpld circuitry can boot from the spi flash
after boot the props I2C busses connect together with other two cpld pins (where other i2c devices can be) forming a I2C repeater
if two eeproms was used to boot the props than they becames inaccessible because their adresses conflict on the same bus
if both the props are accessing common I2C devices than both must support multimaster arbitration on bus
P24..27 bus control lines
Now maybe the choosen pins are not the best ones (I don't know), I need that someone provide me with the best pasm code solutions (bandwidth optimized, self modifying code??) and explanations in order to choose the right pins, the ones that makes prop code faster.
The idea of serial address bus can be developed arround a 2 cog scheme ? ones cog video harware always sending addresses (read/write) and cog code making parallel reads, second cog vga hardware performing high speed data writes synced with first cog addresses? (Some inputs to the gurus to develop an idea)
Where the overhead in waitvid the address+command? mov,movi,movd,movs? If a clever and easy bit pattern is found (easy prop coding) it's ok: the address/command bits can be mixed and not consecutive in the 32bit message, the cpld can easily reestablish the right order and extract the information. A vga clolor waitvid can deliver 4 bytes out (write long to ram) on 8 bit data bus at very high speed compared to any 4 pasm instructions can do? Maybe with a small increase of transaction setup overhead it is still faster? I am not enough skilled on pasm and since now I have focused on the hardware ideas (mainly cpld single modules development and testing).
I had a feeling that with a good and functional hardware design, being many gurus in the forum, they will (help me/us) extract all the juice till the last drop from the orange.
dMajo said...
If you consider your board a daughterboard, a part of a bigger circuit (no connectors, no dedicated circuitry), than there is no need to provide 1.8 regulator (up to you). In this case the user that will provide the regutated 3.3v can also provide the 1.8V
This can not be done as the project has morphed to a pin for pin prop replacement. same size as dip 40 but with large ram and flash on board. Since the prop has no 1.8V pin i need to get it from the props 3.3V pin.
dMajo said...
Maybe I was misunderstood. The system clock is provided to the cpld which provide a divided one to the prop (xin).
Since I can not find a 160MHz Crystal the best alternative is allow the user to run the prop at 5/6.25MHz and have the prop provide an insync 160/200MHz signal. Still locks the 2 chips together but sacrifices a prop pin. If enough io lines i will still have the crystal pin go to the cpld and then through a 0 ohm jumper to the prop. that way by removing the jumper you can provide a 160MHz signal to the cpld and have cpld provide 80MHz to prop but I am pretty sure there will not be enough pins on the 570.
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Since I can not find a 160MHz Crystal the best alternative is allow the user to run the prop at 5/6.25MHz and have the prop provide an insync 160/200MHz signal. Still locks the 2 chips together but sacrifices a prop pin. If enough io lines i will still have the crystal pin go to the cpld and then through a 0 ohm jumper to the prop. that way by removing the jumper you can provide a 160MHz signal to the cpld and have cpld provide 80MHz to prop but I am pretty sure there will not be enough pins on the 570.
I (or someone else) need to try the attached circuit principle (I can do it in middle of October when I get back my hardware stuff and laboratory) eg 5MHz*32 or 10MHz*16·or still better 20MHz*8. The other choice is an external "crystal oscillator"
The benefits of cpld clocking the prop are:
- boot from spi flash (prop reset driven by cpld when is ready to emulate the eeprom)
- clocking at 80/40/20/10/5/2.5/1.25 MHz the prop/s (eventually user selectable - power saving applications)
- freeze and wake up the prop/s at predefined (eventually user selectable) intervals by enabling/disabling the prop clock (power saving applications)
From a quick search in my digital library I have attached one example of clock oscillator up to 200M (unfortunately it is missing the 160M but for sure someone produce it)
I have the pll schematic and theory in one of my text books I can easily find but space and io are limited see what I can do.
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Could you not boot from the 5mhz xin attached to prop pin? Having an eeprom not to big of inconvience.
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I am, occasionally. Mostly I am writing video drivers right now (and graphics libraries for them)
These modules look really interesting, and I have ordered an EPM240 board and USB programmer [noparse]:)[/noparse]
I may entertain using a CPLD/FPGA for a future surface mount version of Morpheus, or for the future 8MB (possibly 16MB) surface mount memory board for Morpheus.
dMajo said...
BTW are Catalina and Morpheus fathers following this thread?
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Please use mikronauts _at_ gmail _dot_ com to contact me off-forum, my PM is almost totally full Morpheus & Mem+dual Prop SBC w/ 512KB kit $119.95, 2MB memory IO board kit $89.95, both kits $189.95 www.mikronauts.com - my site 6.250MHz custom Crystals for running Propellers at 100MHz Las - Large model assembler for the Propeller Largos - a feature full nano operating system for the Propeller
i see chip select is used in the timing but do not see write protect and hold with the M25P64-VME6TG
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Comments
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--Steve
Propeller Tools
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first have a look to this posts, hope they can clarify what I have (done) and what we are discussing about:
http://forums.parallax.com/showthread.php?p=831720
http://forums.parallax.com/showthread.php?p=834382
http://forums.parallax.com/showthread.php?p=832773
@waltc, there is a prototype and is more or less like the above schematic exept that have two spi flash so that both the props can boot at the same time. The virtual dual port implementation was tested with this kind of code:
Prop 1 Prop2 mov outa,#1 mov one,ina mov outa,#2 mov two,ina mov outa,#3 mov three,ina . . . . . . mov outa,#63 mov sixtythree,ina mov outa,#64 mov sixtyfour, ina one RES 1 two RES 1 . .this is like burst reads, the two props was accessing the sram the same time, the bandwidth (if math is not an opinion) is 20MB/s (sram to·cog register). The cpld design has no sram contention circuitry (semaphores, looks ...) because the ram access is sequential and hierarchical (if both read the same location·at the same time both read the same data, if both write prop2 overwrites prop1 data: in the cpld pipeline prop1 cames first prop2 is second of course regarding the same ram address)
Regarding data transfer speed (when I' have back my hardware and my laboratory) I need to test waitvid (with forum support, both for hardware and PASM):
@Jazzed do you know props video hardware?
@mctrivia: There is no crystals for such speeds so I am using my laboratory generator for testing. Both the cplds (CoolRunner and MaxII) haven't PLL inside and you can not create/program it. This are builtin features (they are partially analog circuits).
The only way is to try a lower crystal with a clock multiplier (from my knowleage a xor with shorted inputs, one of two delayed will multiply by 2. The delay give the duty cycle of the doubled clock. Now with several of this stages linked serially you can multiply by·2N the clock. Need to test if it is stable in frequency and duty cycle under diferent conditions (cpld: temperature, power supply ...).
The second way is to have an external crystal oscillator.
@jazzed
The ram I have chosen is 10nS (100MHz) 5 times more the best single cog performance speaking in frequency. The rams 100MHz frequency becames 200MB/s bandwith since it is 16 bits. Now if you have a 16· bit ram that means that the data are word aligned so the need to have upper/lower byte selection (just for writing: in classic 16 ram if you want to write a byte you need to read the word, and/or mask it with your byte data and write again as word since all the 16 data bus bits are transferred to ram cell. During reads the cpld will always read a word and if a byte is required it will cache the second one for the next sequential access (if any) in order to not access again the ram and save the power (CE deselected))
What is transfer rate you are expecting from such design?
As per cpld I am actually working on a XC2C256 CoolRunner-II CPLD·and I think (but I am not a guru) the EPM240 will not be enough so I suggested to count on 76 IOs only because that is the number available on the EPM570 in the same package. I have chosen tqfp 144 pin because it can fit both epm570 end epm1270 (and because I have never soldered bga
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· Propeller Object Exchange (last Publications / Updates)
Post Edited (dMajo) : 8/25/2009 12:26:26 PM GMT
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A 16 bit design option with byte enables is tasty for some applications. Take a CMD* bit (Command asserted low), UEN*/LEN* (byte enables so we don't have to do read/modify/write), CLK (prefer synchronous), and 16 data bits for example. This allows a 2 word command/address phase and N word data so that single cog single word access time could be on the order of 650ns (includes setup), and 12 pins are left for the user. The 8 bit alternative could use as little as 9 pins.
I'm working on different read algorithms to get better 16 bit data-rate ideas. In any event, the ability to use more than one COG requires less than 12.5ns access per transaction. Kuroneko posted a 5 COG program that gives ~20MB burst for 8 bit reads.
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--Steve
Propeller Tools
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
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--Steve
Propeller Tools
Handbook MII5V1-3.3 (08/2009)········Table 1–5,·Table 5–2··············Table 1–1..2,·Table 5–14, Table 5–23..24(part 2), Table 5–32..33
==================================================================================
MAX II··························· ···VCCint(core) 3.3/2.5V········· max freq 304MHz· ····· · ··Speed Grades -3, -4, -5
MAX IIG·························· · VCCint(core) 1.8V··············· max freq 304MHz········ ·· Speed Grades -3, -4, -5
MAX IIZ······················· ·· · VCCint(core) 1.8V······· ····· · max freq 152/184MHz····· Speed Grades -6, -7, -8
Someone of the forum users (I can not recall right now) have written "datasheet is your best friend ..."
In my downloaded library I have the MII5V1-3.1 (12/2007) edition end it is written the same
As I said in the above post (hope you have read it including the links) I have already done some work (dual port circuitry, i2c interface switching, prop boot-up state machine, serial port switching, vector interrupt controller ...). The hardware have setup registers so that the prop can configure/change on the fly the working mode of the hardware modules. I have tested them alone (not together at the same time).
The flash to ram background copy (shadowing) will partially reuse the prop boot-up state machine to manage the spi protocol and probably became a third port on the already made dual-port ram interface.
During the above developments I had the feeling that the XC2C256 will not be enough for all of them together (epm240 is smaller) and that the options remains XC2C384, EPM570, EPM1270
cheers
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· Propeller Object Exchange (last Publications / Updates)
Post Edited (dMajo) : 8/26/2009 7:30:38 AM GMT
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
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1) What about using the video hardware in composite 2 color mode with a single ended plla mode having clock outputed on pina and data shifted out on the video pin? one waitvid operation can shift out (SSI - synchronous serioal interface) the 32 bits embedding the address anc command than you can done directly mov, mov, mov ... and get one byte/word (depending on the databus width between the prop and cpld) per instruction. I was able to get 20MB/s on 64 consecutive ram locations in transfers between sram and cog ram. The problem is I do not know enougs pasm tricks on how to take advantege of this speed (I am missing a way to write just one byte in the cog long preserving the other three without and/or masking)
2)what about using video hardware in vga mode and using colors register as data send interface, again with plla outputing the clock through pina, so a single waitvid can write 32 bits (8bits in four steps) to the cpld.
With the cpld it's possible to handle this comms at max prop speed (if I am not wrong: 160MHz)
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· Propeller Object Exchange (last Publications / Updates)
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· Propeller Object Exchange (last Publications / Updates)
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· Propeller Object Exchange (last Publications / Updates)
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--Steve
Propeller Tools
- Propalyzer: Propeller PC Logic Analyzer
- BMAD: An on-chip PASM Debugger
- SPUD: Spin Source Level Debugger for Linux/Cygwin
Post Edited (jazzed) : 8/25/2009 9:06:43 PM GMT▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
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--Steve
Propeller Tools
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
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So is a Prop part of your CPLD SRAM board?
Walt.
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
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1.8V 5.4ns
i will add the apropriate regulator. having fun finding pinout for epm570 to compare and see what is different.
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
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In test&development phase the final user can also have a choice to drop down the voltage to 1.8V from a well regulated 3.3V source with two Si and one Ge diodes in series.
A second poin of view on the 1.8V the cpld core needs is: this is the same as prop II so less rework to do in the future if you want to upgrede the design.
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· Propeller Object Exchange (last Publications / Updates)
Sending serialized address idea comes to me to avoid dira switching during random reads: parallel data bus always in, serial address always out = data/address pin count reduction (less prop io used).
On my prototype I have p0..7 and p24..31 wired to the cpld because of that thoughts:
Now maybe the choosen pins are not the best ones (I don't know), I need that someone provide me with the best pasm code solutions (bandwidth optimized, self modifying code??) and explanations in order to choose the right pins, the ones that makes prop code faster.
The idea of serial address bus can be developed arround a 2 cog scheme ? ones cog video harware always sending addresses (read/write) and cog code making parallel reads, second cog vga hardware performing high speed data writes synced with first cog addresses? (Some inputs to the gurus to develop an idea)
Where the overhead in waitvid the address+command? mov,movi,movd,movs? If a clever and easy bit pattern is found (easy prop coding) it's ok: the address/command bits can be mixed and not consecutive in the 32bit message, the cpld can easily reestablish the right order and extract the information. A vga clolor waitvid can deliver 4 bytes out (write long to ram) on 8 bit data bus at very high speed compared to any 4 pasm instructions can do? Maybe with a small increase of transaction setup overhead it is still faster? I am not enough skilled on pasm and since now I have focused on the hardware ideas (mainly cpld single modules development and testing).
I had a feeling that with a good and functional hardware design, being many gurus in the forum, they will (help me/us) extract all the juice till the last drop from the orange.
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· Propeller Object Exchange (last Publications / Updates)
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· Propeller Object Exchange (last Publications / Updates)
This can not be done as the project has morphed to a pin for pin prop replacement. same size as dip 40 but with large ram and flash on board. Since the prop has no 1.8V pin i need to get it from the props 3.3V pin.
Since I can not find a 160MHz Crystal the best alternative is allow the user to run the prop at 5/6.25MHz and have the prop provide an insync 160/200MHz signal. Still locks the 2 chips together but sacrifices a prop pin. If enough io lines i will still have the crystal pin go to the cpld and then through a 0 ohm jumper to the prop. that way by removing the jumper you can provide a 160MHz signal to the cpld and have cpld provide 80MHz to prop but I am pretty sure there will not be enough pins on the 570.
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
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The benefits of cpld clocking the prop are:
- boot from spi flash (prop reset driven by cpld when is ready to emulate the eeprom)
- clocking at 80/40/20/10/5/2.5/1.25 MHz the prop/s (eventually user selectable - power saving applications)
- freeze and wake up the prop/s at predefined (eventually user selectable) intervals by enabling/disabling the prop clock (power saving applications)
From a quick search in my digital library I have attached one example of clock oscillator up to 200M (unfortunately it is missing the 160M but for sure someone produce it)
PEDIT: Added MCSOHVT.pdf
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· Propeller Object Exchange (last Publications / Updates)
Post Edited (dMajo) : 8/26/2009 3:42:47 PM GMT
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
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▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
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--Steve
Propeller Tools
These modules look really interesting, and I have ordered an EPM240 board and USB programmer [noparse]:)[/noparse]
I may entertain using a CPLD/FPGA for a future surface mount version of Morpheus, or for the future 8MB (possibly 16MB) surface mount memory board for Morpheus.
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Please use mikronauts _at_ gmail _dot_ com to contact me off-forum, my PM is almost totally full
Morpheus & Mem+dual Prop SBC w/ 512KB kit $119.95, 2MB memory IO board kit $89.95, both kits $189.95
www.mikronauts.com - my site 6.250MHz custom Crystals for running Propellers at 100MHz
Las - Large model assembler for the Propeller Largos - a feature full nano operating system for the Propeller
i see chip select is used in the timing but do not see write protect and hold with the M25P64-VME6TG
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propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5
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