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Open Source High Speed SRAM Module(AKA Super Prop) - Page 6 — Parallax Forums

Open Source High Speed SRAM Module(AKA Super Prop)

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Comments

  • mctriviamctrivia Posts: 3,772
    edited 2009-09-08 19:05
    I have made theentire outside a power rail on layers 2-5 with gnd on 1 and 6. Will act as small cap all the way around.

    I also have 4 10uF caps 1 for each side.

    These are on top of many decoupling caps. Space is limited though so part placement is done as close as possible.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5

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  • jazzedjazzed Posts: 11,803
    edited 2009-09-08 19:42
    OK, you are counting on the "NEXT window of opportunity" to stay on sync.
    That makes sense. Sorry I missed that "NEXT window" idea before.
    The code below proves the point by producing jitter free square-waves.

    Nice smile.gif

    {{
    NextWindow.spin
    }}
    
      _CLKMODE      = XTAL1 + PLL16x
      _XINFREQ      = 5_000_000
    
    pub main
      cognew(@entry, 0)
      
    dat
      entry        org 0
      or           dira,    #1
      rdlong val1, ptr
      nop  
    '{      ' this loop makes a jitter free 1.19MHz square wave (5MHz crystal) 
    :loop
      xor          outa,  #1    ' 0
      rdlong       val1, ptr    ' 4
      nop                       ' 11
      nop                       ' 15
      rdlong       val1, ptr    ' 19
      jmp          #:loop       ' 26
    '}
    '{      ' this loop also makes a jitter free 1.19MHz square wave (5MHz crystal)
    :loop2
      xor          outa,  #1    ' 0
      nop                       ' 4
      nop                       ' 8
      nop                       ' 12
      rdlong       val1, ptr    ' 16
      nop                       ' 23
      jmp    #:loop2            ' 27
    '}
    
    ptr     long 4
    val1    long 0
    val2    long 0
    
    

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    --Steve

    Propeller Tools
  • NetHogNetHog Posts: 104
    edited 2009-09-08 20:31
    mctrivia said...

    The board is pretty tight but i will try to squeeze it in if can. what is your request?

    Actually I think you're doing wonders as it is.
    Having a configuration which is Prop + CPLD + RAM gives lots of flexability.
    ·
  • mctriviamctrivia Posts: 3,772
    edited 2009-09-09 06:39
    P0-P15 connected to bank 4
    sig-cpld pad
    P0-Y19
    P1-W18
    P2-W17
    P3-Y17
    P4-Y16
    P5-W16
    P6-W15
    P7-W14
    P8-w13
    P9-Y18
    P10-Y15
    P11-Y14
    P12-Y10
    P13-Y9
    P14-Y3
    P15-Y2

    RES-Y13(clrn)
    PROP RES-Y12
    BOE-Y11

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    propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5

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  • dMajodMajo Posts: 855
    edited 2009-09-09 09:17
    jazzed said...
    OK, you are counting on the "NEXT window of opportunity" to stay on sync.
    That makes sense. Sorry I missed that "NEXT window" idea before.
    The code below proves the point by producing jitter free square-waves.

    Nice smile.gif

    {{
    NextWindow.spin
    }}
    
      _CLKMODE      = XTAL1 + PLL16x
      _XINFREQ      = 5_000_000
    
    pub main
      cognew(@entry, 0)
      
    dat
      entry        org 0
      or           dira,    #1
      rdlong val1, ptr
      nop  
    '{      ' this loop makes a jitter free 1.19MHz square wave (5MHz crystal) 
    :loop
      xor          outa,  #1    ' 0
      rdlong       val1, ptr    ' 4
      nop                       ' 11
      nop                       ' 15
      rdlong       val1, ptr    ' 19 [color=red][s](7 instructions clock + 1 clock waiting window)[/s] (1 clock waiting window + 7 instructions clocks)[/color]
      jmp          #:loop       ' [s]26[/s] [color=red]27[/color]
    '}
    '{      ' this loop also makes a jitter free 1.19MHz square wave (5MHz crystal)
    :loop2
      xor          outa,  #1    ' 0
      nop                       ' 4
      nop                       ' 8
      nop                       ' 12
      rdlong       val1, ptr    ' 16
      nop                       ' 23
      jmp    #:loop2            ' 27
    '}
    
    ptr     long 4
    val1    long 0
    val2    long 0
    
    

    Thank you Jazzed Steve. Actually I am just writing down and developing concepts/ideas because I·still need a month to be operative on hardware again (I am moving·to new house). I was pretty sure that I was right and therefore I have insisted so much. I was convinced to have known how to explain the "next-window" concept/idea but obviously I was wrong (I still need to improove my English a lot).I have gotten used (trained) to reach the objectives with success and when the things go wrong I need to understand (proof) where and why this is happened. I know how to be very obstinate in to pursue this because I have found this a good method to improve my knowledge/skills (keeping them in the indelible brain's memory area) and avoid the same errors again.

    Once more thank you for having borne me and to have reasoned together with me. I am preparing another concept/idea and I will appreciate a lot the comparison/discussion with you so remain tuned
    Sincerely, Dario

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    Post Edited (dMajo) : 9/9/2009 1:19:47 PM GMT
  • mctriviamctrivia Posts: 3,772
    edited 2009-09-10 04:03
    talk about tight. think this is the final position of all components on top side.

    you can see i have 3 alignment wholes to allow for easy alignment of programing/test rig and also to make sure rig is not acidently installed upside down.



    top right is 3 jumpers that shere common pad
    bottom left is 2 jumpers that share a common pad
    top and bottom in middle is jumpers.
    all the rest of 0603 and 0402 are caps except 2 pull up/down resisters.

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  • dMajodMajo Posts: 855
    edited 2009-09-10 07:44
    I cannot recognize the JP_CLK jumper (4 pin SIL - or same funtion ones). Where are the resistors between the prop<->cpld pins?

    Can you post/pm the schematics?



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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-10 13:14
    I hope to have a schematic up today. need to clean up a fair bit and still have a few traces to connect on middle layers.

    A) is series resisters between cpld and pin
    B) clk jumper
    C) GND jumper
    D) 3.3V Jumper
    E) cpld core voltage enable jumper
    F) reset jumper
    G) pullup/down
    H) Flash
    I) Prop
    J) Regulator

    all others are caps.

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  • dMajodMajo Posts: 855
    edited 2009-09-10 18:37
    @mctrivia
    Am I blind or you have fogotten the letters G..J on the picture smilewinkgrin.gif

    Seriously, can you explain the function of the jumpers (specially the clk one because it seems you have not implemented my suggestion)

                    Prop.28(XI)    CPLD_GCLK[noparse][[/noparse]0..3]
    
                           [sup]  [/sup]|     [sup]  [/sup]|                             Case 1                    Case 2
                           [sub]  [/sub]|     [sub]  [/sub]|                         
    JP_CLK ----->       [sup]1[/sup]o  [sup]2[/sup]o  [sup]3[/sup]o  [sup]4[/sup]o                          [sup]1[/sup]o--[sup]2[/sup]o  [sup]3[/sup]o--[sup]4[/sup]o              [sup]1[/sup]o  [sup]2[/sup]o--[sup]3[/sup]o  [sup]4[/sup]o
                        [sup] [/sup]|     [sup]  [/sup]|
                        [sub] [/sub]|     [sub]  [/sub]|
                    CPLD_IO    DIP40.p30(XI)
    

    Case1 (no off-board 5MHz crystal - new design):
    JP 1-2: will connect CPLD generated clock to PropPin28(XI)
    JP 3-4: will connect CPLD_GCLK[noparse][[/noparse]eg.1] to DIP40pin30(XI) thus allowing to clock the cpld trough an off-board oscillator up to 200MHz

    Case2 (off-board·usual prop 5/6.25MHz crystal):
    JP 3-4: will connect the DIP40pin30(XI) to the PropPin28(XI) thus allowing classic(existing) Prop crystal scheme (direct replacement)
    in this situation the CPLD can be clocked through the other CPLD_GCLK[noparse][[/noparse]eg.0] that's connected on PropPin29(XO). Of course it will run at 5MHz but synced with prop.·Different·clock can be provided trough the other two CPLD_GCLK[noparse][[/noparse]eg.2..3] available on the top/bottom side pads. Or Prop can provide counter/pll clock to one of the cpld generic IOs that they share.

    Case1bis (without crystal -high speed):
    JP 1-2 (only): don't forget that the CPLD have a built-in oscillator (3..5.5MHz) that can be PLLed by the Prop (48..88MHz). Not accurate (suffer the same problem like RCslow/fast) but where processing power is needed without big time accuracy it is OK.
    JP 3-4 (optional): The CPLD_GCLK[noparse]/noparse in this case can be used as GPIO

    Case1ter & Case2bis: there is also two other opportunities but I don't want to speak about them now, I need to make a hardware test before.


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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-10 18:41
    there are 2 Gs. top right and bottom left by flash
    J is the small 3x3 square to the right center of all the caps

    will post schematic in 5min

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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-10 18:55
    here are the prop and flash portions of the schematic.

    the clock jumper connects A20 to xin to allow high speed clock from cpld. if not placed then outside pin is used.

    P28 of prop is routed to one of general clock pins for the option of prop providing cpld with high speed clock.

    160Mhz cpld clock must be provided off board through extra pin or from prop.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    propmod_us and propmod_1x1 are in stock. Only $30. PCB available for $5

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    Post Edited (mctrivia) : 9/10/2009 7:00:31 PM GMT
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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-10 21:42
    here is the power and the extra 10pins/14 pads

    you will notice i use 0ohm resisters for jumpers. they are small and the jumpers allow for different configurations. they are not ment to be changed by the end user.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-11 03:06
    Updated schematics had to move XI.

    Also switch the optional 3.3V and GND pins can get 3 times the current to an expansion board this way.

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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-12 02:49
    PCB is now done. just double checking all layers. will get ram schematic up later tonight.

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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-13 05:18
    dMajo I know you want me to run xo to the cpld. I have a few option to do this which do you and others think best.

    Option 1: Leave as is only clock options are:
    A) Crystal on prop, prop uses 1 pin to send 160MHz clock, internal used while prop not providing clock
    B) Crystal on CPLD, cpld divides by 2 and runs prop xin

    Option 2: Leave small gap between a trace on xo that can be easily soldered over to a trace running to cpld.

    Option 2 requires p28 to be relocated to either A20 or D20.
    A20) means P28 is on bank 2 and p24-27,p29-31 are on bank 1. for 570 this is same bank so nonissue but 1270 they are separate.
    D20) only down side is signal has to go through a via then run on trace on bottom of pcb.
    both choices will result in p28 running directly below p29 which could potentially cause problems if running 160 to 200MHz signal but not to likely.

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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-13 05:44
    here is the ram schematic. day late but the wife needed my computer.

    also included some part placement diagrams that make easier to see part density.

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  • dMajodMajo Posts: 855
    edited 2009-09-13 10:39
    I am in the new house so no literature here (and also no time - other jobs to do) but no problem for Option2-A20. The only signals that should be close are the ones are probably being used for bus: so P0..15 and ram address/data busses (because of routing/propagation delays (timings) inside the cpld - less things to care on during the design, perhaps also less internal logic used). The bank placement is important only if you need to have different voltage levels bacause all the IOs in the same bank share the same VCCIO.
    My question, some posts ago, regarding the possibility to use as much as possible bank3 was due to the fact that, if you use 1270, it have configurable clamping diodes (pci compatibility). Now, no one, I think, will ever connect this pcb to the pc's pci bus, but the need for clamping diodes can arise and because you already have them on the cpld it will be nice if you could use them.


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    Post Edited (dMajo) : 9/13/2009 10:47:12 AM GMT
  • mctriviamctrivia Posts: 3,772
    edited 2009-09-13 14:41
    Without going to an 8 layer board there is no way to keep ram on same bank. I am limited by physical layout of pins on ram chip.

    As for bank 3 it is connected to extra pins a-e. Can't use it for prop pins and still make good electrical connection to cpld.

    I am designing a simple daughter board with a use card and 160 mhz crystal. Any suggestions what to do with extra 4 io?

    second sd(4)
    Usb uart(2)
    Connector
    ...

    Edit crystal takes 1 so that leaves 3

    Usd is spi so 3 of 4 can be reused for other spi devices

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    Post Edited (mctrivia) : 9/13/2009 3:03:26 PM GMT
  • mctriviamctrivia Posts: 3,772
    edited 2009-09-14 02:50
    Here are simulations of the board. My simulation software is not perfect but close.

    pads will be gold and some of the lines shown are notes only(circles around programing pads, lines over cpld pads)

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    Post Edited (mctrivia) : 9/14/2009 2:55:51 AM GMT
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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-14 02:55
    here are final schematics.

    I am getting quotes at the moment for costs hope to be able to give some final numbers soon.

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  • jazzedjazzed Posts: 11,803
    edited 2009-09-14 05:56
    Will the SRAM get hot on the bottom side of the DIP40 in a socket?

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    --Steve

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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-14 06:18
    good question depends on air flow and heat generated by the ics. placing on top would be ideal but means i can't put the prop itself on the board.



    pin standoff is 2mm ram and cpld are both 1.2mm so that leaves a 0.8mm air gap.

    a heat sink could be made and attached to ic but would not help much without air flow. if side pins are mounted up or not at all then heat sink fins could be used to get rid of the heat.

    pin length is not shown on diagram but looks to be about 10mm if so then there should be a relatively large air gap if socketed.

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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-14 13:32
    Just got final pcb cost
    1 panel 6 layers $990
    1 panel 8 layers $1200 2 layers just for power and gnd
    15 panels 8 layers $1900

    Panel does 70 super props.

    In large quantities this could be made relatively inexpensive.

    Quoted price was for 60 mil board thickness seeing if I can get 50mil so legs fit better.

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  • AleAle Posts: 2,363
    edited 2009-09-21 13:00
    mctrivia:

    Those are quite a few boards. Are you sure it is a good idea to make the board that small ? Maybe using a 64 DIP size can reduce the number of layers to 4 or maybe to 2 as make everything cheaper ?.
    Just a thought. I read somewhere here (I think Leon said it), that placing VIAs in the pads of BGA components complicates the soldering. I always thought it was a great idea. I never did it.
    Which SRAM are you using ? If I may ask.

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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-21 14:25
    The reason dip 40 is for compatibility to prop. Only way ro get to 4 layers is to make much wider length will not help.

    As for type I wrote it a couple pages back.

    Placing via under pads is only way with mbga and also makes soldering easy.
    Via will probably plate over though.

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  • AleAle Posts: 2,363
    edited 2009-09-22 09:35
    I understand the compatibility factor but as there are SMT SIL connectors It may have passed on your mind to make it a bit bigger.
    Depending on how you solder the BGAs I think it may not be such a good idea, VIAs in the PADs because the solder could flow to the other side, any ideas here ?

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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-22 13:23
    I am using 8mil vias. They will more then likely plate shut so solder can not run through. Also most vias go from bottom to layer 2 and stop so it can't go through anyways.

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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-25 15:27
    here is the test/programming rig. i like the idea of having the prop testing itself.

    rig is actually 2 pcb that are stacked.

    need to find footprint for power connectors.

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  • dMajodMajo Posts: 855
    edited 2009-09-25 16:14
    @mctrivia

    I suggest you to have two 3way jumpers on eeprom's A0/1 address pins so that you can choose high or low. If you want the SP boot from flash then the cpld and eeprom addresses will conflict on same I2C bus. Beside this the cpld UFM can also be available on the I2C.

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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-25 16:16
    ah very good point. i will make the change.

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