Understanding that development for the Prop II has been a fluid process and there are still possibilities of change, I've refrained from doing anything concrete in preparing for the Prop II's arrival, however, now having silicone in test and having the 128 pin package defined on the Prop II wiki, I'm wondering if it might be reasonably "Safe" to start doing some general lay-out work for my next generation boards?
Are things getting "Locked" enough that it might be OK to create a new Prop II part for the layout programs ( PCB123 & ExpressPCB ) to play with spacing and general fit? I don't mind moving a few pins around later if that's all it might be, but I also don't want to waste ALL of the time done in preliminary design work.
I have a board I designed with 3 Props on it ( because I needed the extra I/O ) That I would be nice to start "transferring" over to the Prop II. Is it still premature to start this kind of preliminary stuff... or are we getting close enough to a defined product that it might be OK to start doing something "REAL" to prepare for it's arrival?
I know better than to ask for a delivery date, but is there a fair degree of confidence that the pinout as currently defined might actually be final?
What happens to the chips along the process of being tested? What kind of testing? Do they ever become destroyed? Is there a board that is designed right off the bat to use with it?
What current products would have an advantage to have Prop II added to them?
What size breadboard should we use with the Prop II? It is bigger and has more pins. Are the acrylic cases going to have to be redesigned to allow for more board space?
Well, from what I saw and heard last time this was explained to me, this run will have all the key structures needed to verify functionality, and I suspect test some limits to see where the silicon does vary from the theory used to design it.
It's really a proto propeller, and it's got a removable top, so it can be measured and poked at in extreme detail.
After that data is collected, potentially some decisions change, others solidify, the real Propeller is then designed from the test data, and often referring to it.
That cycle will produce real chips that are going to be a lot like, if not ideally, the real deal.
IMHO, I agree with potatohead's assessment - it is way too early for anything to be locked down. If you read a few posts back, there is a description of just what is on the test chip. It is far from being a prototype chip in that sense. It is a conglomeration of blocks to check that certain functions work as expected. If all is OK, then a relaying process will be done with complete blocks which will then be run as another test chip.
Everything so far looks really good. There are a few issues, but we understand what they are.
- The resistors used for the FUSES mistakenly had Salicide Blockage resulting in a much higher resistance value, so we can't 'pop' them to test them. This was an error that was overlooked between both Chip and myself.
- The QUADPORT RAM (<- The MEM_COG) needed better signal isolation between the D and the R lines ... See attached BEFORE and AFTER layout image. The BIT cell has been modified, and a Ground line has been added between the D and the R lines.
Other than that the MEM_DUALPORT memory, the MEM_ROM, and the MEM_RAM were all ok. The other blocks ... PUD (Power Up Detect), BOD (Brown Out Detect), OSC (Internal Oscillator), PLL_MUL (Phase Lock Loop Multiplier) all tested ok as well.
Everything so far looks really good. There are a few issues, but we understand what they are.
- The resistors used for the FUSES mistakenly had Salicide Blockage resulting in a much higher resistance value, so we can't 'pop' them to test them. This was an error that was overlooked between both Chip and myself.
- The QUADPORT RAM (<- The MEM_COG) needed better signal isolation between the D and the R lines ... See attached BEFORE and AFTER layout image. The BIT cell has been modified, and a Ground line has been added between the D and the R lines.
Other than that the MEM_DUALPORT memory, the MEM_ROM, and the MEM_RAM were all ok. The other blocks ... PUD (Power Up Detect), BOD (Brown Out Detect), OSC (Internal Oscillator), PLL_MUL (Phase Lock Loop Multiplier) all tested ok as well.
It's because of the capacitance that D and R were coupling together. Placing a GND line between them doesn't eliminate the capacitance, and does increase it some, but the important part here is that D and R are no longer directly coupled together. Instead they are individually coupled to Ground
Sapieha,
I'm not sure I completely understand your question... the scale between the memory cell, and the XTAL I/O's is so different, you really can't look at them the same.
It's because of the capacitance that D and R were coupling together. Placing a GND line between them doesn't eliminate the capacitance, and does increase it some, but the important part here is that D and R are no longer directly coupled together. Instead they are individually coupled to Ground
We are finally in production with our Polaris PoS Terminal. We shipped the first 50 to customers before the
holidays. We couldn't cram in all the features that we wanted to but the Propeller II should help us do this
and more.
We make very smart Point of Sale Terminals for school cafeterias. Our first product was a PAD (Personal Access Device) so the kids could identify themselves.
The kids can enter there ID number into a keyboard, bar code reader or Bio Metric finger scanner. We have sold over 3000 of these Prop I based systems and they are doing very well. I am working on a similar PAD now that will control vending machines, we call it a Vending Pad. The whole idea is cashless sales, the parents put money in the kids accounts over the internet and can monitor exactly what they are eating.
Our latest product is a large PoS Terminal, it has 80 programmable food keys and 32 function keys. It also has a large 7" Color touch screen LCD display (232 x 480 x 16). Two Pads plug into the terminal so there can be two lines of kids feeding the cashier. The kids come up with there food, they can use the finger scanner on the Pads to identify them selves and there picture pops up on the terminal along with there account information. The cashier hits the proper food keys and the account is updated.
All of this is accomplished with one poor little over clocked Propeller 1 chip and a handful of I2C & Spi chips. I tried to include the spec sheet but it is over the forum's size limit.
Thank you BigFoot for the interesting info. Nice to hear so many Props are 'quietly' going into products such as yours. One Prop 1 doing all that work; great use of Parallax's neat IC,
Bigfoot: Congratulations, this is a great use of the prop. Perhaps you could put this up on a separate thread where others may find it and search for it.
Thanks for the kind words, we couldn't have done it with out the forum. You guys have some great ideas and we bypassed many a potential problem
by reading what others have done.
My guess would be this: if the testing went well, Beau is in a "a$$holes and elbows" mode (as the sergeant used say in the Army when we were about to pick up any litter). If problems in testing then there might be a revision of their test chip. Anyway, Chip and/or Beau might be very busy.
I too am awaiting any news on Prop 2 progress.....
Edit...apologies, by time I added my comment, I wasn't aware of previous posts for some reason. I had to reboot my iMac.
Edit#2..OK, just noticed the previous posts were 'old' ones. I think if they were ready to let us know more, we'd be told about their progress.
That's a good assessment, I must have left my web-cam on by mistake. Seriously though you are exactly right. Sorry I haven't posted any video in awhile, The test Die was one thing (small in size), but the Propeller II has 128 I/O pins around the peripheral. ... right now video is too much of a resource. Currently just for the I/O's there are 662,200 transistors.
Ramblings:
Currently I'm working on putting the I/O PAD frame together, while Chip is busy with the Verilog 'glue logic' for the COGs. Basically the I/O PAD frame is complete, but I'm having to step back a little and systematically check a few things because of some quirk issues in the layout tool. Tying all of the I/O's together is a HUGE wire buss that traverses the core perimeter consisting of 320+ wires. Each wire is 1um wide with 1um separation which normally would mean that the wire buss would need to occupy a width of at least 640 um. With multiple wire layers and allowing for escapement for Power/Ground into the core the wire buss is 216 um wide. The hardest part with 320+ wires is making a 90 deg turn at the corners. (Actually done with two 45 deg turns)
Basically we are moving forward, and are very busy.
Hi Beau! Thanks for the update! It sounds like exciting times continue at Parallax.
Any chance someone could post the Propeller II instruction set sometime soon?
Thanks very much for the update. Also, sorry to be so blunt but isn't 128 I/O somewhat excessive? (unless you plan for DRAM/parallel flash but that seems overkill).
Beau:
Ok, I get it, you mean from the chiop itself you have 128 pins connecting to your on chip circuit.
Also, nudge Chip about the Prop 2 instruction set, he said he would post them to the forums when he was chatting with us on the Savage Circuits Friday Night Chat.
Comments
Are things getting "Locked" enough that it might be OK to create a new Prop II part for the layout programs ( PCB123 & ExpressPCB ) to play with spacing and general fit? I don't mind moving a few pins around later if that's all it might be, but I also don't want to waste ALL of the time done in preliminary design work.
I have a board I designed with 3 Props on it ( because I needed the extra I/O ) That I would be nice to start "transferring" over to the Prop II. Is it still premature to start this kind of preliminary stuff... or are we getting close enough to a defined product that it might be OK to start doing something "REAL" to prepare for it's arrival?
I know better than to ask for a delivery date, but is there a fair degree of confidence that the pinout as currently defined might actually be final?
Ken Bash
What current products would have an advantage to have Prop II added to them?
What size breadboard should we use with the Prop II? It is bigger and has more pins. Are the acrylic cases going to have to be redesigned to allow for more board space?
It's really a proto propeller, and it's got a removable top, so it can be measured and poked at in extreme detail.
After that data is collected, potentially some decisions change, others solidify, the real Propeller is then designed from the test data, and often referring to it.
That cycle will produce real chips that are going to be a lot like, if not ideally, the real deal.
IMHO, it's early to be building boards.
Is there anything that you can tell us about the Prop II test chip, you guys must of had a chance to fire it up by now ?
Everything so far looks really good. There are a few issues, but we understand what they are.
- The resistors used for the FUSES mistakenly had Salicide Blockage resulting in a much higher resistance value, so we can't 'pop' them to test them. This was an error that was overlooked between both Chip and myself.
- The QUADPORT RAM (<- The MEM_COG) needed better signal isolation between the D and the R lines ... See attached BEFORE and AFTER layout image. The BIT cell has been modified, and a Ground line has been added between the D and the R lines.
Other than that the MEM_DUALPORT memory, the MEM_ROM, and the MEM_RAM were all ok. The other blocks ... PUD (Power Up Detect), BOD (Brown Out Detect), OSC (Internal Oscillator), PLL_MUL (Phase Lock Loop Multiplier) all tested ok as well.
The I/O is still under test.
Have You even that Ground line's betwen External Crystal inputs on XI, XO signals?
Sapieha,
I'm not sure I completely understand your question... the scale between the memory cell, and the XTAL I/O's is so different, you really can't look at them the same.
I know that BUT it still not answer my question
Thanks for the update.
We are finally in production with our Polaris PoS Terminal. We shipped the first 50 to customers before the
holidays. We couldn't cram in all the features that we wanted to but the Propeller II should help us do this
and more.
Interesting. Could you elaborate more. That was such a tease.
POS = point of sale? or something else? Any photo to give an idea of what's referred to?
We make very smart Point of Sale Terminals for school cafeterias. Our first product was a PAD (Personal Access Device) so the kids could identify themselves.
The kids can enter there ID number into a keyboard, bar code reader or Bio Metric finger scanner. We have sold over 3000 of these Prop I based systems and they are doing very well. I am working on a similar PAD now that will control vending machines, we call it a Vending Pad. The whole idea is cashless sales, the parents put money in the kids accounts over the internet and can monitor exactly what they are eating.
Our latest product is a large PoS Terminal, it has 80 programmable food keys and 32 function keys. It also has a large 7" Color touch screen LCD display (232 x 480 x 16). Two Pads plug into the terminal so there can be two lines of kids feeding the cashier. The kids come up with there food, they can use the finger scanner on the Pads to identify them selves and there picture pops up on the terminal along with there account information. The cashier hits the proper food keys and the account is updated.
All of this is accomplished with one poor little over clocked Propeller 1 chip and a handful of I2C & Spi chips. I tried to include the spec sheet but it is over the forum's size limit.
Bigfoot: Congratulations, this is a great use of the prop. Perhaps you could put this up on a separate thread where others may find it and search for it.
by reading what others have done.
I was wondering if you could give us an update on the Propeller II chip ?
I too am awaiting any news on Prop 2 progress.....
Edit...apologies, by time I added my comment, I wasn't aware of previous posts for some reason. I had to reboot my iMac.
Edit#2..OK, just noticed the previous posts were 'old' ones. I think if they were ready to let us know more, we'd be told about their progress.
That's a good assessment, I must have left my web-cam on by mistake. Seriously though you are exactly right. Sorry I haven't posted any video in awhile, The test Die was one thing (small in size), but the Propeller II has 128 I/O pins around the peripheral. ... right now video is too much of a resource. Currently just for the I/O's there are 662,200 transistors.
Ramblings:
Currently I'm working on putting the I/O PAD frame together, while Chip is busy with the Verilog 'glue logic' for the COGs. Basically the I/O PAD frame is complete, but I'm having to step back a little and systematically check a few things because of some quirk issues in the layout tool. Tying all of the I/O's together is a HUGE wire buss that traverses the core perimeter consisting of 320+ wires. Each wire is 1um wide with 1um separation which normally would mean that the wire buss would need to occupy a width of at least 640 um. With multiple wire layers and allowing for escapement for Power/Ground into the core the wire buss is 216 um wide. The hardest part with 320+ wires is making a 90 deg turn at the corners. (Actually done with two 45 deg turns)
Basically we are moving forward, and are very busy.
Any chance someone could post the Propeller II instruction set sometime soon?
Thanks very much for the update. Also, sorry to be so blunt but isn't 128 I/O somewhat excessive? (unless you plan for DRAM/parallel flash but that seems overkill).
If I know correctly 96 I/O external --- All other Internal
Dave Hein,
I don't have any of the instructions. I'm sure when Chip can come up for air, he will post them.
Ok, I get it, you mean from the chiop itself you have 128 pins connecting to your on chip circuit.
Also, nudge Chip about the Prop 2 instruction set, he said he would post them to the forums when he was chatting with us on the Savage Circuits Friday Night Chat.
Roy
instruction mnem oper ---------------------------------------------------------------------------- 000000 EE00CCCC DDDDDDDDD SSSSSSSSS WRBYTE D,S 000000 EE01CCCC DDDDDDDDD 0nnnnnnnn WRBYTE D,#n 000000 EE01CCCC DDDDDDDDD 1SUPIIIII WRBYTE D,PTR 000000 EE10CCCC DDDDDDDDD SSSSSSSSS RDBYTE D,S 000000 EE11CCCC DDDDDDDDD 0nnnnnnnn RDBYTE D,#n 000000 EE11CCCC DDDDDDDDD 1SUPIIIII RDBYTE D,PTR 000001 EE00CCCC DDDDDDDDD SSSSSSSSS WRWORD D,S 000001 EE01CCCC DDDDDDDDD 0nnnnnnnn WRWORD D,#n 000001 EE01CCCC DDDDDDDDD 1SUPIIIII WRWORD D,PTR 000001 EE10CCCC DDDDDDDDD SSSSSSSSS RDWORD D,S 000001 EE11CCCC DDDDDDDDD 0nnnnnnnn RDWORD D,#n 000001 EE11CCCC DDDDDDDDD 1SUPIIIII RDWORD D,PTR 000010 EE00CCCC DDDDDDDDD SSSSSSSSS WRLONG D,S 000010 EE01CCCC DDDDDDDDD 0nnnnnnnn WRLONG D,#n 000010 EE01CCCC DDDDDDDDD 1SUPIIIII WRLONG D,PTR 000010 EE10CCCC DDDDDDDDD SSSSSSSSS RDLONG D,S 000010 EE11CCCC DDDDDDDDD 0nnnnnnnn RDLONG D,#n 000010 EE11CCCC DDDDDDDDD 1SUPIIIII RDLONG D,PTR 000011 EEE0CCCC DDDDDDDDD SSSSSSSSS COGINIT D,S 000011 EE01CCCC DDDDDDDDD 000000000 CLKSET D 000011 EE11CCCC DDDDDDDDD 000000001 COGID D 000011 EEE1CCCC DDDDDDDDD 000000010 ( COGINIT D ) 000011 EE01CCCC DDDDDDDDD 000000011 COGSTOP D 000011 EE11CCCC DDDDDDDDD 000000100 LOCKNEW D 000011 EE01CCCC DDDDDDDDD 000000101 LOCKRET D 000011 EE01CCCC DDDDDDDDD 000000110 LOCKSET D 000011 EE01CCCC DDDDDDDDD 000000111 LOCKCLR D 000011 EEE1CCCC DDDDDDDDD 000001000 GETCNT D 000011 EEE1CCCC DDDDDDDDD 000001001 GETLFSR D 000011 EEE1CCCC DDDDDDDDD 000001010 GETACCL D 000011 EEE1CCCC DDDDDDDDD 000001011 GETACCH D (clears acc) 000011 EEE1CCCC DDDDDDDDD 000001100 GETPTRA D 000011 EEE1CCCC DDDDDDDDD 000001101 GETPTRB D 000011 EEE1CCCC DDDDDDDDD 000001110 GETTOPS D 000011 EEE1CCCC DDDDDDDDD 000001111 GETPIX D (waits for pix) 000011 EEE1CCCC DDDDDDDDD 000010000 GETMULL D (waits for mul) 000011 EEE1CCCC DDDDDDDDD 000010001 GETMULH D (waits for mul) 000011 EEE1CCCC DDDDDDDDD 000010010 GETDIVQ D (waits for div) 000011 EEE1CCCC DDDDDDDDD 000010011 GETDIVR D (waits for div) 000011 EEE1CCCC DDDDDDDDD 000010100 GETSQRT D (waits for sqrt) 000011 EEE1CCCC DDDDDDDDD 000010101 GETCORX D (waits for cordic) 000011 EEE1CCCC DDDDDDDDD 000010110 GETCORY D (waits for cordic) 000011 EEE1CCCC DDDDDDDDD 000010111 GETCORZ D (waits for cordic) 000011 EEE1CCCC DDDDDDDDD 000011000 GETPHSA D 000011 EEE1CCCC DDDDDDDDD 000011001 GETPHZA D (clears phsa) 000011 EEE1CCCC DDDDDDDDD 000011010 GETCOSA D 000011 EEE1CCCC DDDDDDDDD 000011011 GETSINA D 000011 EEE1CCCC DDDDDDDDD 000011100 GETPHSB D 000011 EEE1CCCC DDDDDDDDD 000011101 GETPHZB D (clears phsb) 000011 EEE1CCCC DDDDDDDDD 000011110 GETCOSB D 000011 EEE1CCCC DDDDDDDDD 000011111 GETSINB D 000011 EEE1CCCC DDDDDDDDD 000100000 DECOD2 D 000011 EEE1CCCC DDDDDDDDD 000100001 DECOD3 D 000011 EEE1CCCC DDDDDDDDD 000100010 DECOD4 D 000011 EEE1CCCC DDDDDDDDD 000100011 DECOD5 D 000011 EEE1CCCC DDDDDDDDD 000100100 BLMASK D 000011 EEE1CCCC DDDDDDDDD 000100101 NOT D 000011 EEE1CCCC DDDDDDDDD 000100110 ONECNT D 000011 EEE1CCCC DDDDDDDDD 000100111 ZERCNT D 000011 EEE1CCCC DDDDDDDDD 000101000 INCPAT D 000011 EEE1CCCC DDDDDDDDD 000101001 DECPAT D 000011 EEE1CCCC DDDDDDDDD 000101010 BINGRY D 000011 EEE1CCCC DDDDDDDDD 000101011 GRYBIN D 000011 EEE1CCCC DDDDDDDDD 000101100 MERGEW D 000011 EEE1CCCC DDDDDDDDD 000101101 SPLITW D 000011 EEE1CCCC DDDDDDDDD 000101110 SEUSSF D 000011 EEE1CCCC DDDDDDDDD 000101111 SEUSSR D 000011 E001CCCC DDDDDDDDD 000110000 SNDSER D (waits for tx) 000011 E101CCCC DDDDDDDDD 000110000 SNDSER D wc 000011 E011CCCC DDDDDDDDD 000110000 RCVSER D (waits for rx) 000011 E111CCCC DDDDDDDDD 000110000 RCVSER D wc 000011 EE01CCCC DDDDDDDDD 000110001 WRCLUT D 000011 EE11CCCC DDDDDDDDD 000110001 RDCLUT D (waits one clock) 000011 EE01CCCC 000000000 000110010 SYNCTRA (waits for ctra) 000011 EE01CCCC 000000000 000110011 SYNCTRB (waits for ctrb) 000011 EE01CCCC 000000000 000110100 CAPCTRA 000011 EE01CCCC 000000000 000110101 CAPCTRB 000011 EN01CCCC nnnnnnnnn 010000000 NOPX D/#n 000011 EN01CCCC Dnnnnnnnn 010000001 SETMAP D/#n 000011 EN01CCCC nnnnnnnDD 010000010 SETQUAD D/#n 000011 EN01CCCC DDnnnnnnn 010000011 SETCLUT D/#n 000011 EN01CCCC DDDDDDDDD 010000100 SETPTRA D/#n 000011 EN01CCCC DDDDDDDDD 010000101 SETPTRB D/#n 000011 EN01CCCC DDDDDDDDD 010000110 SETXCHG D/#n 000011 EN01CCCC DDnnDDDDD 010000111 SETPORT D/#n 000011 EN01CCCC DDDDDnnnn 010001000 SETCOG D/#n 000011 EN01CCCC DDDnnnnnn 010001001 SETVID D/#n 000011 EN01CCCC DDDDDDDDD 010001010 SETSER D/#n 000011 EN01CCCC DDDnnnnnn 010001011 SETXFER D/#n 000011 EN01CCCC Dnnnnnnnn 010001100 CFGDACS D/#n * 000011 EN01CCCC nnnnnnnnn 010001101 SETDACS D/#n * 000011 EN01CCCC nnnnnnnnn 010001110 ADDPHSA D/#n 000011 EN01CCCC nnnnnnnnn 010001111 ADDPHSB D/#n 000011 EN01CCCC nnnnnnnnn 010010000 SETPIX D/#n 000011 EN01CCCC nnnnnnnnn 010010001 SETPIXU D/#n 000011 EN01CCCC nnnnnnnnn 010010010 SETPIXV D/#n 000011 EN01CCCC nnnnnnnnn 010010011 SETPIXZ D/#n 000011 EN01CCCC nnnnnnnnn 010010100 SETPIXR D/#n 000011 EN01CCCC nnnnnnnnn 010010101 SETPIXG D/#n 000011 EN01CCCC nnnnnnnnn 010010110 SETPIXB D/#n 000011 EN01CCCC nnnnnnnnn 010010111 SETPIXA D/#n 000011 EN01CCCC nnnnnnnnn 010011000 SETMULA D/#n 000011 EN01CCCC nnnnnnnnn 010011001 SETMULB D/#n 000011 EN01CCCC nnnnnnnnn 010011010 SETDIVA D/#n 000011 EN01CCCC nnnnnnnnn 010011011 SETDIVB D/#n 000011 EN01CCCC nnnnnnnnn 010011100 SETSQRT D/#n 000011 EN01CCCC nnnnnnnnn 010011101 SETCORX D/#n 000011 EN01CCCC nnnnnnnnn 010011110 SETCORY D/#n 000011 EN01CCCC nnnnnnnnn 010011111 SETCORZ D/#n 000011 EN01CCCC DDDDnnnnn 010100000 CORDROT D/#n 000011 EN01CCCC DDDDnnnnn 010100001 CORDATN D/#n 000011 EN01CCCC DDDDnnnnn 010100010 CORDEXP D/#n 000011 EN01CCCC DDDDnnnnn 010100011 CORDLOG D/#n 000011 EN01CCCC DDnnDDDDD 010100100 SETPORA D/#n 000011 EN01CCCC DDnnDDDDD 010100101 SETPORB D/#n 000011 EN01CCCC DDnnDDDDD 010100110 SETPORC D/#n 000011 EN01CCCC DDnnDDDDD 010100111 SETPORD D/#n 000011 EN01CCCC nnnnnnnnn 010101000 SETCTRA D/#n 000011 EN01CCCC nnnnnnnnn 010101001 SETWAVA D/#n 000011 EN01CCCC nnnnnnnnn 010101010 SETFRQA D/#n 000011 EN01CCCC nnnnnnnnn 010101011 SETPHSA D/#n 000011 EN01CCCC nnnnnnnnn 010101100 SETCTRB D/#n 000011 EN01CCCC nnnnnnnnn 010101101 SETWAVB D/#n 000011 EN01CCCC nnnnnnnnn 010101110 SETFRQB D/#n 000011 EN01CCCC nnnnnnnnn 010101111 SETPHSB D/#n 000011 EN01CCCC nnnnnnnnn 010110000 SETVIDM D/#n 000011 EN01CCCC nnnnnnnnn 010110001 SETVIDY D/#n 000011 EN01CCCC nnnnnnnnn 010110010 SETVIDI D/#n 000011 EN01CCCC nnnnnnnnn 010110011 SETVIDQ D/#n 000011 EN01CCCC DDDDDDDnn 010110100 CFGDAC0 D/#n 000011 EN01CCCC DDDDDDDnn 010110101 CFGDAC1 D/#n 000011 EN01CCCC DDDDDDDnn 010110110 CFGDAC2 D/#n 000011 EN01CCCC DDDDDDDnn 010110111 CFGDAC3 D/#n 000011 EN01CCCC nnnnnnnnn 010111000 SETDAC0 D/#n 000011 EN01CCCC nnnnnnnnn 010111001 SETDAC1 D/#n 000011 EN01CCCC nnnnnnnnn 010111010 SETDAC2 D/#n 000011 EN01CCCC nnnnnnnnn 010111011 SETDAC3 D/#n 000011 EN01CCCC 1SUPIIIII 010111100 WRQUAD D/#n/PTR 000011 EN01CCCC 1SUPIIIII 010111101 RDQUAD D/#n/PTR 000011 EN01CCCC nnnnnnnnn 011iiiiii REP D/#n,#i 000011 EEE1CCCC DDDDDDDDD 1000bbbbb ISOB D.b 000011 EEE1CCCC DDDDDDDDD 1001bbbbb NOTB D.b 000011 EEE1CCCC DDDDDDDDD 1010bbbbb CLRB D.b 000011 EEE1CCCC DDDDDDDDD 1011bbbbb SETB D.b 000011 EEE1CCCC DDDDDDDDD 1100bbbbb SETBC D.b 000011 EEE1CCCC DDDDDDDDD 1101bbbbb SETBNC D.b 000011 EEE1CCCC DDDDDDDDD 1110bbbbb SETBZ D.b 000011 EEE1CCCC DDDDDDDDD 1111bbbbb SETBNZ D.b 000100 EE0ICCCC DDDDDDDDD SSSSSSSSS MAC D,S 000100 EE1ICCCC DDDDDDDDD SSSSSSSSS MUL D,S 000101 EE0ICCCC DDDDDDDDD SSSSSSSSS MACS D,S 000101 EE1ICCCC DDDDDDDDD SSSSSSSSS MULS D,S 000110 EEEICCCC DDDDDDDDD SSSSSSSSS ENC D,S 000111 EEEICCCC DDDDDDDDD SSSSSSSSS JMPRET D,S 001000 EEEICCCC DDDDDDDDD SSSSSSSSS ROR D,S 001001 EEEICCCC DDDDDDDDD SSSSSSSSS ROL D,S 001010 EEEICCCC DDDDDDDDD SSSSSSSSS SHR D,S 001011 EEEICCCC DDDDDDDDD SSSSSSSSS SHL D,S 001100 EEEICCCC DDDDDDDDD SSSSSSSSS RCR D,S 001101 EEEICCCC DDDDDDDDD SSSSSSSSS RCL D,S 001110 EEEICCCC DDDDDDDDD SSSSSSSSS SAR D,S 001111 EEEICCCC DDDDDDDDD SSSSSSSSS REV D,S 010000 EEEICCCC DDDDDDDDD SSSSSSSSS MINS D,S 010001 EEEICCCC DDDDDDDDD SSSSSSSSS MAXS D,S 010010 EEEICCCC DDDDDDDDD SSSSSSSSS MIN D,S 010011 EEEICCCC DDDDDDDDD SSSSSSSSS MAX D,S 010100 EEEICCCC DDDDDDDDD SSSSSSSSS MOVS D,S 010101 EEEICCCC DDDDDDDDD SSSSSSSSS MOVD D,S 010110 EEEICCCC DDDDDDDDD SSSSSSSSS MOVI D,S 010111 EEEICCCC DDDDDDDDD SSSSSSSSS JMPRETD D,S 011000 EEEICCCC DDDDDDDDD SSSSSSSSS AND D,S 011001 EEEICCCC DDDDDDDDD SSSSSSSSS ANDN D,S 011010 EEEICCCC DDDDDDDDD SSSSSSSSS OR D,S 011011 EEEICCCC DDDDDDDDD SSSSSSSSS XOR D,S 011100 EEEICCCC DDDDDDDDD SSSSSSSSS MUXC D,S 011101 EEEICCCC DDDDDDDDD SSSSSSSSS MUXNC D,S 011110 EEEICCCC DDDDDDDDD SSSSSSSSS MUXZ D,S 011111 EEEICCCC DDDDDDDDD SSSSSSSSS MUXNZ D,S 100000 EEEICCCC DDDDDDDDD SSSSSSSSS ADD D,S 100001 EEEICCCC DDDDDDDDD SSSSSSSSS SUB D,S 100010 EEEICCCC DDDDDDDDD SSSSSSSSS ADDABS D,S 100011 EEEICCCC DDDDDDDDD SSSSSSSSS SUBABS D,S 100100 EEEICCCC DDDDDDDDD SSSSSSSSS SUMC D,S 100101 EEEICCCC DDDDDDDDD SSSSSSSSS SUMNC D,S 100110 EEEICCCC DDDDDDDDD SSSSSSSSS SUMZ D,S 100111 EEEICCCC DDDDDDDDD SSSSSSSSS SUMNZ D,S 101000 EEEICCCC DDDDDDDDD SSSSSSSSS MOV D,S 101001 EEEICCCC DDDDDDDDD SSSSSSSSS NEG D,S 101010 EEEICCCC DDDDDDDDD SSSSSSSSS ABS D,S 101011 EEEICCCC DDDDDDDDD SSSSSSSSS ABSNEG D,S 101100 EEEICCCC DDDDDDDDD SSSSSSSSS NEGC D,S 101101 EEEICCCC DDDDDDDDD SSSSSSSSS NEGNC D,S 101110 EEEICCCC DDDDDDDDD SSSSSSSSS NEGZ D,S 101111 EEEICCCC DDDDDDDDD SSSSSSSSS NEGNZ D,S 110000 EEEICCCC DDDDDDDDD SSSSSSSSS CMPS D,S 110001 EEEICCCC DDDDDDDDD SSSSSSSSS CMPSX D,S 110010 EEEICCCC DDDDDDDDD SSSSSSSSS ADDX D,S 110011 EEEICCCC DDDDDDDDD SSSSSSSSS SUBX D,S 110100 EEEICCCC DDDDDDDDD SSSSSSSSS ADDS D,S 110101 EEEICCCC DDDDDDDDD SSSSSSSSS SUBS D,S 110110 EEEICCCC DDDDDDDDD SSSSSSSSS ADDSX D,S 110111 EEEICCCC DDDDDDDDD SSSSSSSSS SUBSX D,S 111000 EEEICCCC DDDDDDDDD SSSSSSSSS INCMOD D,S 111001 EEEICCCC DDDDDDDDD SSSSSSSSS DECMOD D,S 111010 EEEICCCC DDDDDDDDD SSSSSSSSS CMPSUB D,S 111011 0E0ICCCC DDDDDDDDD SSSSSSSSS WAITPEQ D,S 111011 1E0ICCCC DDDDDDDDD SSSSSSSSS WAITPNE D,S 111100 00EICCCC DDDDDDDDD SSSSSSSSS WAITCNT D,S 111100 010ICCCC DDDDDDDDD SSSSSSSSS WAITVID D,S 111100 100ICCCC DDDDDDDDD SSSSSSSSS CFGPINS D,S 111100 1100CCCC DDDDDDDDD SSSSSSSSS SETINDA D,S 111100 1101CCCC DDDDDDDDD SSSSSSSSS SETINDB D,S 111101 000ICCCC DDDDDDDDD SSSSSSSSS TJZ D,S 111101 010ICCCC DDDDDDDDD SSSSSSSSS TJZD D,S 111101 100ICCCC DDDDDDDDD SSSSSSSSS TJNZ D,S 111101 110ICCCC DDDDDDDDD SSSSSSSSS TJNZD D,S 111110 00EICCCC DDDDDDDDD SSSSSSSSS IJZ D,S 111110 01EICCCC DDDDDDDDD SSSSSSSSS IJZD D,S 111110 10EICCCC DDDDDDDDD SSSSSSSSS IJNZ D,S 111110 11EICCCC DDDDDDDDD SSSSSSSSS IJNZD D,S 111111 00EICCCC DDDDDDDDD SSSSSSSSS DJZ D,S 111111 01EICCCC DDDDDDDDD SSSSSSSSS DJZD D,S 111111 10EICCCC DDDDDDDDD SSSSSSSSS DJNZ D,S 111111 11EICCCC DDDDDDDDD SSSSSSSSS DJNZD D,S ----------------------------------------------------------------------------Great stuff Beau - thanks to you and Chip.
Pehaps someone could do the whole forum a service and compare this to the existing instruction set and highlight the new/changed instructions?
Then we can all get busy on updating our respective compilers/interpreters/application programs for the Prop II.
Ross.