For all of you guys out there that refuse to give up your dip chips, here is the new Propeller 2 - 128 pin dip package and special socket. A custom chip extractor is also in the works.
BigFoot, that's a peciular package I have ever seen... I sometimes wondered, why not it be made like a FAT 68K DIP-68 package, like on old Macintosh 4G motherboard??? otherwise, if it was actually being made, it will go down the road as "World's Strangest Microcontroller" on Guiness's World Record Book. =____="
This level is mostly complete, but I have been chasing an elusive 'error' yesterday and today which really isn't an error at all but it has to do with having different substrate connections as well as different power connections which causes the LVS tool to go a little nuts.
In order to proceed the error must be understood and a solution needs to be meet. The problem has to do with certain labels that are reserved for power and ground and that are also defined a global labels.
For example... If you define a power connection as "VP" at the top level, that's fine, it's not a reserved global label. The problem happens when you descend in hierarchy and a cell block at a lower level is connected to a global power or ground label such as VDD or GND. The LVS tool sees this as a discrepancy and will hunt you down :smilewinkgrin:
The solution is to encapsulate everything under the hood hierarchically down from where you detour in the labeling convention.
I try my hardest to keep any 'human hands' out of a Spice file (netlist) at all costs to minimize any chance for human error to be introduced, but the only way to represent the above scenario is to make a Spice file change.
LVS at the Top level TestDie will be done soon.
What's next? When the entire Top level TestDie is LVS/DRC clean I will run what's called a density check to determine "low material" metal, poly, and diffusion spots. This is basically a modified DRC that looks at the project in stepped windows over small overlapping areas. This process helps to increase the chip yield by aiding in the planarization process.
We are still on target for an early November tape out for a Test Die.
I have seen 2 64 pin DIP packages although one can hardly be a DIP.
Rockwell used to make modem chips in a QIP 64 package where pin spacing was 0.05" but the length of the pins varied so they formed 2 rows per side at 0.1" pitch and stagged 0.1". I do not recall the width but I suspect they would have been at least 0.9". The legs were quite flimsy and you had to be really careful. initially we put them into sockets but the sockets caused more problems than they saved so we ditched the sockets.
The other one I saw was a Hitachi Z80 variant (HD64180???) that had 0.07" pin spacing and IIRC was 0.6" wide. There were sockets available but $$.
Unfortunately, neither of these were good choices as they were not a common solution.
The best method I would think would be for an smt chip on a small pcb with 0.1" pitch holes for pin stakes and pin stake sockets. A smaller pitch such as 2mm could be used but there are not so common and cause other issues.
The best method I would think would be for an smt chip on a small pcb with 0.1" pitch holes for pin stakes and pin stake sockets. A smaller pitch such as 2mm could be used but there are not so common and cause other issues.
I agree, perf boards, veroboards, and breadboards all use 0.1" pitch. A 2mm pitch would be messy..
I think allot of the older ceramic / gold leaded packages cost more than the chip. The one that inspired my 128 pin dip was that huge Motorola 68000 chip.
"Understanding the 68000", there is one used hard cover copy up on Amazon I'd love to see it.
That was it! It was never available in hard cover, perhaps it's a rebound library copy. They weren't very well bound and fell to pieces quite quickly. I've still got one of my author's copies. It got good reviews at the time, probably because it was the only book available.
There was a mistake in the schematic that prevents the circuit working; one of the enables on the EPROM is tied high instead of low, or vice-versa.
The probleme with a board is that when you burn your prop, or any other component on the board, it's the entire board you have to throw away, even if it's just a 0.5$ component that need to be changed
Also, that increase the entry price. You can have a prop for 5$ and use what you already have at home to start to play with it, but you will never find a board at that price.
So far, my main concern is more to know if beginners like me will be able to use it. I don't know what's a DCA and how it works. I know 0, and I know 1. That's all.
Anyway, like any new toy, I will probably by some to have them on the shelves, and see when I will have some time to use them
Parallax is pretty good at making complex things straightforward for beginners. Compare the SX48 microcontroller by itself with the BS2p which uses it. Also look at the Scribbler II which uses the Propeller, but is very much designed for absolute beginners.
Spin for the Prop II should be no more complicated to use than for the Prop I unless you want to use the new features. Even there, most of those features will be handled by library objects that, hopefully, will be mostly compatible with existing objects where the functionality overlaps.
The main issue will be dealing with the larger package and larger number of pins and, as has already been done with the Prop I, there will be modules and boards with reduced access to I/O pins and some supporting circuitry on the module or board to make things simple for the user.
I believe that Chip said at the conference that it would be a 128 pin tqfp and it
would be the 14mm square version. If I understand correctly the package has
32 leads on a side and they are on a .4mm pitch.
Bobb Fwed, My comment was about the number of pins in the 128pDip photo. 62 per side, times 2, 124 total pins. This has absolutely nothing to do with actual current or future designs. Just a silly comment.
Bobb Fwed, My comment was about the number of pins in the 128pDip photo. 62 per side, times 2, 124 total pins. This has absolutely nothing to do with actual current or future designs. Just a silly comment.
It was a slow night, I was bored, I counted them.
I, and hopefully everyone else, just took his word for it.
Good catch, though, you get a gold star.
When I originally made the post, I was envisioning a small board with removable crystal, prop II, regulators and a series of header sockets.
Insert power, jump the wires to your bread board as needed. All of the power and grounding requirements would already be met on the:
"Prop II Designers Breakout board"
Hmmm, if Parallax gods should so chose to create such an item, there's a good name for it!
The LVS is still going on at the TestDie 'TOP' level which means that no Density checks have been run.
There was a snag in the PAD ring that was causing a circular reference LVS issue which has been resolved.
I'll report before next Friday when LVS/DRC is clean for the TestDie (Should be a day or two), then we can move on to Density checking followed by script based ROM population. Then we're done, off to the FAB!!!
Comments
Is it available in a 0.3" package??
--Rich
How did you know that is exactly what I want?
How many do we get per tube?
only in a .9" package sorry ...
We were going to go with a 1.2" package but that wouldn't leave much in the way on a SBB... :smilewinkgrin:
--> As before, the TestDie Core is LVS/DRC clean!
--> Still at the TestDie 'TOP' level ...
This level is mostly complete, but I have been chasing an elusive 'error' yesterday and today which really isn't an error at all but it has to do with having different substrate connections as well as different power connections which causes the LVS tool to go a little nuts.
In order to proceed the error must be understood and a solution needs to be meet. The problem has to do with certain labels that are reserved for power and ground and that are also defined a global labels.
For example... If you define a power connection as "VP" at the top level, that's fine, it's not a reserved global label. The problem happens when you descend in hierarchy and a cell block at a lower level is connected to a global power or ground label such as VDD or GND. The LVS tool sees this as a discrepancy and will hunt you down :smilewinkgrin:
The solution is to encapsulate everything under the hood hierarchically down from where you detour in the labeling convention.
I try my hardest to keep any 'human hands' out of a Spice file (netlist) at all costs to minimize any chance for human error to be introduced, but the only way to represent the above scenario is to make a Spice file change.
LVS at the Top level TestDie will be done soon.
What's next? When the entire Top level TestDie is LVS/DRC clean I will run what's called a density check to determine "low material" metal, poly, and diffusion spots. This is basically a modified DRC that looks at the project in stepped windows over small overlapping areas. This process helps to increase the chip yield by aiding in the planarization process.
We are still on target for an early November tape out for a Test Die.
That is so funny. Well done!
You should know for a good joke you must get the math right.
Which four pins got dropped in your design?:shakehead:
Rockwell used to make modem chips in a QIP 64 package where pin spacing was 0.05" but the length of the pins varied so they formed 2 rows per side at 0.1" pitch and stagged 0.1". I do not recall the width but I suspect they would have been at least 0.9". The legs were quite flimsy and you had to be really careful. initially we put them into sockets but the sockets caused more problems than they saved so we ditched the sockets.
The other one I saw was a Hitachi Z80 variant (HD64180???) that had 0.07" pin spacing and IIRC was 0.6" wide. There were sockets available but $$.
Unfortunately, neither of these were good choices as they were not a common solution.
The best method I would think would be for an smt chip on a small pcb with 0.1" pitch holes for pin stakes and pin stake sockets. A smaller pitch such as 2mm could be used but there are not so common and cause other issues.
I agree, perf boards, veroboards, and breadboards all use 0.1" pitch. A 2mm pitch would be messy..
Massimo
-phar
And less chance of bridging when dIY toasteroven reflow.
but over 64pin, these seems to go .5mm
I think allot of the older ceramic / gold leaded packages cost more than the chip. The one that inspired my 128 pin dip was that huge Motorola 68000 chip.
Russ
"Understanding the 68000", there is one used hard cover copy up on Amazon I'd love to see it.
That was it! It was never available in hard cover, perhaps it's a rebound library copy. They weren't very well bound and fell to pieces quite quickly. I've still got one of my author's copies. It got good reviews at the time, probably because it was the only book available.
There was a mistake in the schematic that prevents the circuit working; one of the enables on the EPROM is tied high instead of low, or vice-versa.
It does not exist yet.
And I bet many design features are yet to be finalized.
Be patient.
By the way, is that page correct when it says 128 pin package?
Does this mean it is actually 132 pins? Which four pins are listed on the wiki?
Also, that increase the entry price. You can have a prop for 5$ and use what you already have at home to start to play with it, but you will never find a board at that price.
Try to imagine what this board will look like with all those pins exported: http://www.gadgetgangster.com/find-a-project/56.html?projectnum=283
So far, my main concern is more to know if beginners like me will be able to use it. I don't know what's a DCA and how it works. I know 0, and I know 1. That's all.
Anyway, like any new toy, I will probably by some to have them on the shelves, and see when I will have some time to use them
JM
Spin for the Prop II should be no more complicated to use than for the Prop I unless you want to use the new features. Even there, most of those features will be handled by library objects that, hopefully, will be mostly compatible with existing objects where the functionality overlaps.
The main issue will be dealing with the larger package and larger number of pins and, as has already been done with the Prop I, there will be modules and boards with reduced access to I/O pins and some supporting circuitry on the module or board to make things simple for the user.
I believe that Chip said at the conference that it would be a 128 pin tqfp and it
would be the 14mm square version. If I understand correctly the package has
32 leads on a side and they are on a .4mm pitch.
Russ
It was a slow night, I was bored, I counted them.
Good catch, though, you get a gold star.
mistake, it was all in fun anyway.
The model of the 128 pin tqfp is correct though. I already have a board
designed around it.
Russ
Russ
Insert power, jump the wires to your bread board as needed. All of the power and grounding requirements would already be met on the:
"Prop II Designers Breakout board"
Hmmm, if Parallax gods should so chose to create such an item, there's a good name for it!
KK
The LVS is still going on at the TestDie 'TOP' level which means that no Density checks have been run.
There was a snag in the PAD ring that was causing a circular reference LVS issue which has been resolved.
I'll report before next Friday when LVS/DRC is clean for the TestDie (Should be a day or two), then we can move on to Density checking followed by script based ROM population. Then we're done, off to the FAB!!!
Just kind of wondering how big this stuff really is.