Propeller II update - BLOG

178101213223

Comments

  • lanternfishlanternfish Posts: 366
    edited 2011-03-09 - 16:55:42
    Hi Ross

    Are you volunteering?
    ... and when I said "I've been thinking ..." everybody ran
  • RossHRossH Posts: 4,505
    edited 2011-03-09 - 17:11:47
    Hi lanernfish,

    No - Unfortunately, I'm at work at present. But I'm sure that by the time I get home someone else will have already done it!

    Ross.
    Catalina - a FREE ANSI C compiler for the Propeller.
    Download it from http://catalina-c.sourceforge.net/
  • BeanBean Posts: 8,068
    edited 2011-03-09 - 17:46:07
    I really like the ISOB instruction. LOL...

    Too bad it's not USOB, that would be even better. ;)

    Bean
  • David BetzDavid Betz Posts: 13,663
    edited 2011-03-09 - 17:48:21
    Bean wrote: »
    I really like the ISOB instruction. LOL...

    Too bad it's not USOB, that would be even better. ;)

    Bean

    Not as good as the old Lockheed MAC-16 computer which had a SEX instruction for "sign extend".
  • SapiehaSapieha Posts: 2,964
    edited 2011-03-09 - 20:09:45
    Hi Beau.

    SORRY for complains

    Without additional info this list are not so useful


    Here is the latest Propeller II instruction set direct from Chip:
    instruction                                     mnem    oper
    ----------------------------------------------------------------------------
    000000 EE00CCCC DDDDDDDDD SSSSSSSSS             WRBYTE  D,S
    000000 EE01CCCC DDDDDDDDD 0nnnnnnnn             WRBYTE  D,#n
    000000 EE01CCCC DDDDDDDDD 1SUPIIIII             WRBYTE  D,PTR
    
    000000 EE10CCCC DDDDDDDDD SSSSSSSSS             RDBYTE  D,S
    000000 EE11CCCC DDDDDDDDD 0nnnnnnnn             RDBYTE  D,#n
    000000 EE11CCCC DDDDDDDDD 1SUPIIIII             RDBYTE  D,PTR
    
    000001 EE00CCCC DDDDDDDDD SSSSSSSSS             WRWORD  D,S
    000001 EE01CCCC DDDDDDDDD 0nnnnnnnn             WRWORD  D,#n
    000001 EE01CCCC DDDDDDDDD 1SUPIIIII             WRWORD  D,PTR
    
    000001 EE10CCCC DDDDDDDDD SSSSSSSSS             RDWORD  D,S
    000001 EE11CCCC DDDDDDDDD 0nnnnnnnn             RDWORD  D,#n
    000001 EE11CCCC DDDDDDDDD 1SUPIIIII             RDWORD  D,PTR
    
    000010 EE00CCCC DDDDDDDDD SSSSSSSSS             WRLONG  D,S
    000010 EE01CCCC DDDDDDDDD 0nnnnnnnn             WRLONG  D,#n
    000010 EE01CCCC DDDDDDDDD 1SUPIIIII             WRLONG  D,PTR
    
    000010 EE10CCCC DDDDDDDDD SSSSSSSSS             RDLONG  D,S
    000010 EE11CCCC DDDDDDDDD 0nnnnnnnn             RDLONG  D,#n
    000010 EE11CCCC DDDDDDDDD 1SUPIIIII             RDLONG  D,PTR
    
    000011 EEE0CCCC DDDDDDDDD SSSSSSSSS             COGINIT D,S
    
    
    000011 EE01CCCC DDDDDDDDD 000000000             CLKSET  D
    000011 EE11CCCC DDDDDDDDD 000000001             COGID   D
    000011 EEE1CCCC DDDDDDDDD 000000010           ( COGINIT D )
    000011 EE01CCCC DDDDDDDDD 000000011             COGSTOP D
    000011 EE11CCCC DDDDDDDDD 000000100             LOCKNEW D
    000011 EE01CCCC DDDDDDDDD 000000101             LOCKRET D
    000011 EE01CCCC DDDDDDDDD 000000110             LOCKSET D
    000011 EE01CCCC DDDDDDDDD 000000111             LOCKCLR D
    
    000011 EEE1CCCC DDDDDDDDD 000001000             GETCNT  D
    000011 EEE1CCCC DDDDDDDDD 000001001             GETLFSR D
    000011 EEE1CCCC DDDDDDDDD 000001010             GETACCL D
    000011 EEE1CCCC DDDDDDDDD 000001011             GETACCH D                       (clears acc)
    000011 EEE1CCCC DDDDDDDDD 000001100             GETPTRA D
    000011 EEE1CCCC DDDDDDDDD 000001101             GETPTRB D
    000011 EEE1CCCC DDDDDDDDD 000001110             GETTOPS D
    000011 EEE1CCCC DDDDDDDDD 000001111             GETPIX  D                       (waits for pix)
    
    000011 EEE1CCCC DDDDDDDDD 000010000             GETMULL D                       (waits for mul)
    000011 EEE1CCCC DDDDDDDDD 000010001             GETMULH D                       (waits for mul)
    000011 EEE1CCCC DDDDDDDDD 000010010             GETDIVQ D                       (waits for div)
    000011 EEE1CCCC DDDDDDDDD 000010011             GETDIVR D                       (waits for div)
    000011 EEE1CCCC DDDDDDDDD 000010100             GETSQRT D                       (waits for sqrt)
    000011 EEE1CCCC DDDDDDDDD 000010101             GETCORX D                       (waits for cordic)
    000011 EEE1CCCC DDDDDDDDD 000010110             GETCORY D                       (waits for cordic)
    000011 EEE1CCCC DDDDDDDDD 000010111             GETCORZ D                       (waits for cordic)
    
    000011 EEE1CCCC DDDDDDDDD 000011000             GETPHSA D
    000011 EEE1CCCC DDDDDDDDD 000011001             GETPHZA D                       (clears phsa)
    000011 EEE1CCCC DDDDDDDDD 000011010             GETCOSA D
    000011 EEE1CCCC DDDDDDDDD 000011011             GETSINA D
    
    000011 EEE1CCCC DDDDDDDDD 000011100             GETPHSB D
    000011 EEE1CCCC DDDDDDDDD 000011101             GETPHZB D                       (clears phsb)
    000011 EEE1CCCC DDDDDDDDD 000011110             GETCOSB D
    000011 EEE1CCCC DDDDDDDDD 000011111             GETSINB D
    
    000011 EEE1CCCC DDDDDDDDD 000100000             DECOD2  D
    000011 EEE1CCCC DDDDDDDDD 000100001             DECOD3  D
    000011 EEE1CCCC DDDDDDDDD 000100010             DECOD4  D
    000011 EEE1CCCC DDDDDDDDD 000100011             DECOD5  D
    000011 EEE1CCCC DDDDDDDDD 000100100             BLMASK  D
    000011 EEE1CCCC DDDDDDDDD 000100101             NOT     D
    000011 EEE1CCCC DDDDDDDDD 000100110             ONECNT  D
    000011 EEE1CCCC DDDDDDDDD 000100111             ZERCNT  D
    000011 EEE1CCCC DDDDDDDDD 000101000             INCPAT  D
    000011 EEE1CCCC DDDDDDDDD 000101001             DECPAT  D
    000011 EEE1CCCC DDDDDDDDD 000101010             BINGRY  D
    000011 EEE1CCCC DDDDDDDDD 000101011             GRYBIN  D
    000011 EEE1CCCC DDDDDDDDD 000101100             MERGEW  D
    000011 EEE1CCCC DDDDDDDDD 000101101             SPLITW  D
    000011 EEE1CCCC DDDDDDDDD 000101110             SEUSSF  D
    000011 EEE1CCCC DDDDDDDDD 000101111             SEUSSR  D
    
    000011 E001CCCC DDDDDDDDD 000110000             SNDSER  D                       (waits for tx)
    000011 E101CCCC DDDDDDDDD 000110000             SNDSER  D       wc
    000011 E011CCCC DDDDDDDDD 000110000             RCVSER  D                       (waits for rx)
    000011 E111CCCC DDDDDDDDD 000110000             RCVSER  D       wc
    
    000011 EE01CCCC DDDDDDDDD 000110001             WRCLUT  D
    000011 EE11CCCC DDDDDDDDD 000110001             RDCLUT  D                       (waits one clock)
    
    000011 EE01CCCC 000000000 000110010             SYNCTRA                         (waits for ctra)
    000011 EE01CCCC 000000000 000110011             SYNCTRB                         (waits for ctrb)
    
    000011 EE01CCCC 000000000 000110100             CAPCTRA
    000011 EE01CCCC 000000000 000110101             CAPCTRB
    
    000011 EN01CCCC nnnnnnnnn 010000000             NOPX    D/#n
    000011 EN01CCCC Dnnnnnnnn 010000001             SETMAP  D/#n
    000011 EN01CCCC nnnnnnnDD 010000010             SETQUAD D/#n
    000011 EN01CCCC DDnnnnnnn 010000011             SETCLUT D/#n
    000011 EN01CCCC DDDDDDDDD 010000100             SETPTRA D/#n
    000011 EN01CCCC DDDDDDDDD 010000101             SETPTRB D/#n
    000011 EN01CCCC DDDDDDDDD 010000110             SETXCHG D/#n
    000011 EN01CCCC DDnnDDDDD 010000111             SETPORT D/#n
    
    000011 EN01CCCC DDDDDnnnn 010001000             SETCOG  D/#n
    000011 EN01CCCC DDDnnnnnn 010001001             SETVID  D/#n
    000011 EN01CCCC DDDDDDDDD 010001010             SETSER  D/#n
    000011 EN01CCCC DDDnnnnnn 010001011             SETXFER D/#n
    000011 EN01CCCC Dnnnnnnnn 010001100             CFGDACS D/#n    *
    000011 EN01CCCC nnnnnnnnn 010001101             SETDACS D/#n    *
    000011 EN01CCCC nnnnnnnnn 010001110             ADDPHSA D/#n
    000011 EN01CCCC nnnnnnnnn 010001111             ADDPHSB D/#n
    
    000011 EN01CCCC nnnnnnnnn 010010000             SETPIX  D/#n
    000011 EN01CCCC nnnnnnnnn 010010001             SETPIXU D/#n
    000011 EN01CCCC nnnnnnnnn 010010010             SETPIXV D/#n
    000011 EN01CCCC nnnnnnnnn 010010011             SETPIXZ D/#n
    000011 EN01CCCC nnnnnnnnn 010010100             SETPIXR D/#n
    000011 EN01CCCC nnnnnnnnn 010010101             SETPIXG D/#n
    000011 EN01CCCC nnnnnnnnn 010010110             SETPIXB D/#n
    000011 EN01CCCC nnnnnnnnn 010010111             SETPIXA D/#n
    
    000011 EN01CCCC nnnnnnnnn 010011000             SETMULA D/#n
    000011 EN01CCCC nnnnnnnnn 010011001             SETMULB D/#n
    000011 EN01CCCC nnnnnnnnn 010011010             SETDIVA D/#n
    000011 EN01CCCC nnnnnnnnn 010011011             SETDIVB D/#n
    000011 EN01CCCC nnnnnnnnn 010011100             SETSQRT D/#n
    000011 EN01CCCC nnnnnnnnn 010011101             SETCORX D/#n
    000011 EN01CCCC nnnnnnnnn 010011110             SETCORY D/#n
    000011 EN01CCCC nnnnnnnnn 010011111             SETCORZ D/#n
    
    000011 EN01CCCC DDDDnnnnn 010100000             CORDROT D/#n
    000011 EN01CCCC DDDDnnnnn 010100001             CORDATN D/#n
    000011 EN01CCCC DDDDnnnnn 010100010             CORDEXP D/#n
    000011 EN01CCCC DDDDnnnnn 010100011             CORDLOG D/#n
    
    000011 EN01CCCC DDnnDDDDD 010100100             SETPORA D/#n
    000011 EN01CCCC DDnnDDDDD 010100101             SETPORB D/#n
    000011 EN01CCCC DDnnDDDDD 010100110             SETPORC D/#n
    000011 EN01CCCC DDnnDDDDD 010100111             SETPORD D/#n
    
    000011 EN01CCCC nnnnnnnnn 010101000             SETCTRA D/#n
    000011 EN01CCCC nnnnnnnnn 010101001             SETWAVA D/#n
    000011 EN01CCCC nnnnnnnnn 010101010             SETFRQA D/#n
    000011 EN01CCCC nnnnnnnnn 010101011             SETPHSA D/#n
    
    000011 EN01CCCC nnnnnnnnn 010101100             SETCTRB D/#n
    000011 EN01CCCC nnnnnnnnn 010101101             SETWAVB D/#n
    000011 EN01CCCC nnnnnnnnn 010101110             SETFRQB D/#n
    000011 EN01CCCC nnnnnnnnn 010101111             SETPHSB D/#n
    
    000011 EN01CCCC nnnnnnnnn 010110000             SETVIDM D/#n
    000011 EN01CCCC nnnnnnnnn 010110001             SETVIDY D/#n
    000011 EN01CCCC nnnnnnnnn 010110010             SETVIDI D/#n
    000011 EN01CCCC nnnnnnnnn 010110011             SETVIDQ D/#n
    
    000011 EN01CCCC DDDDDDDnn 010110100             CFGDAC0 D/#n
    000011 EN01CCCC DDDDDDDnn 010110101             CFGDAC1 D/#n
    000011 EN01CCCC DDDDDDDnn 010110110             CFGDAC2 D/#n
    000011 EN01CCCC DDDDDDDnn 010110111             CFGDAC3 D/#n
    
    000011 EN01CCCC nnnnnnnnn 010111000             SETDAC0 D/#n
    000011 EN01CCCC nnnnnnnnn 010111001             SETDAC1 D/#n
    000011 EN01CCCC nnnnnnnnn 010111010             SETDAC2 D/#n
    000011 EN01CCCC nnnnnnnnn 010111011             SETDAC3 D/#n
    
    000011 EN01CCCC 1SUPIIIII 010111100             WRQUAD  D/#n/PTR
    000011 EN01CCCC 1SUPIIIII 010111101             RDQUAD  D/#n/PTR
    
    000011 EN01CCCC nnnnnnnnn 011iiiiii             REP     D/#n,#i
    
    000011 EEE1CCCC DDDDDDDDD 1000bbbbb             ISOB    D.b
    000011 EEE1CCCC DDDDDDDDD 1001bbbbb             NOTB    D.b
    000011 EEE1CCCC DDDDDDDDD 1010bbbbb             CLRB    D.b
    000011 EEE1CCCC DDDDDDDDD 1011bbbbb             SETB    D.b
    000011 EEE1CCCC DDDDDDDDD 1100bbbbb             SETBC   D.b
    000011 EEE1CCCC DDDDDDDDD 1101bbbbb             SETBNC  D.b
    000011 EEE1CCCC DDDDDDDDD 1110bbbbb             SETBZ   D.b
    000011 EEE1CCCC DDDDDDDDD 1111bbbbb             SETBNZ  D.b
    
    
    000100 EE0ICCCC DDDDDDDDD SSSSSSSSS             MAC     D,S
    000100 EE1ICCCC DDDDDDDDD SSSSSSSSS             MUL     D,S
    000101 EE0ICCCC DDDDDDDDD SSSSSSSSS             MACS    D,S
    000101 EE1ICCCC DDDDDDDDD SSSSSSSSS             MULS    D,S
    000110 EEEICCCC DDDDDDDDD SSSSSSSSS             ENC     D,S
    000111 EEEICCCC DDDDDDDDD SSSSSSSSS             JMPRET  D,S
    
    001000 EEEICCCC DDDDDDDDD SSSSSSSSS             ROR     D,S
    001001 EEEICCCC DDDDDDDDD SSSSSSSSS             ROL     D,S
    001010 EEEICCCC DDDDDDDDD SSSSSSSSS             SHR     D,S
    001011 EEEICCCC DDDDDDDDD SSSSSSSSS             SHL     D,S
    001100 EEEICCCC DDDDDDDDD SSSSSSSSS             RCR     D,S
    001101 EEEICCCC DDDDDDDDD SSSSSSSSS             RCL     D,S
    001110 EEEICCCC DDDDDDDDD SSSSSSSSS             SAR     D,S
    001111 EEEICCCC DDDDDDDDD SSSSSSSSS             REV     D,S
    
    010000 EEEICCCC DDDDDDDDD SSSSSSSSS             MINS    D,S
    010001 EEEICCCC DDDDDDDDD SSSSSSSSS             MAXS    D,S
    010010 EEEICCCC DDDDDDDDD SSSSSSSSS             MIN     D,S
    010011 EEEICCCC DDDDDDDDD SSSSSSSSS             MAX     D,S
    010100 EEEICCCC DDDDDDDDD SSSSSSSSS             MOVS    D,S
    010101 EEEICCCC DDDDDDDDD SSSSSSSSS             MOVD    D,S
    010110 EEEICCCC DDDDDDDDD SSSSSSSSS             MOVI    D,S
    010111 EEEICCCC DDDDDDDDD SSSSSSSSS             JMPRETD D,S
    
    011000 EEEICCCC DDDDDDDDD SSSSSSSSS             AND     D,S
    011001 EEEICCCC DDDDDDDDD SSSSSSSSS             ANDN    D,S
    011010 EEEICCCC DDDDDDDDD SSSSSSSSS             OR      D,S
    011011 EEEICCCC DDDDDDDDD SSSSSSSSS             XOR     D,S
    011100 EEEICCCC DDDDDDDDD SSSSSSSSS             MUXC    D,S
    011101 EEEICCCC DDDDDDDDD SSSSSSSSS             MUXNC   D,S
    011110 EEEICCCC DDDDDDDDD SSSSSSSSS             MUXZ    D,S
    011111 EEEICCCC DDDDDDDDD SSSSSSSSS             MUXNZ   D,S
    
    100000 EEEICCCC DDDDDDDDD SSSSSSSSS             ADD     D,S
    100001 EEEICCCC DDDDDDDDD SSSSSSSSS             SUB     D,S
    100010 EEEICCCC DDDDDDDDD SSSSSSSSS             ADDABS  D,S
    100011 EEEICCCC DDDDDDDDD SSSSSSSSS             SUBABS  D,S
    100100 EEEICCCC DDDDDDDDD SSSSSSSSS             SUMC    D,S
    100101 EEEICCCC DDDDDDDDD SSSSSSSSS             SUMNC   D,S
    100110 EEEICCCC DDDDDDDDD SSSSSSSSS             SUMZ    D,S
    100111 EEEICCCC DDDDDDDDD SSSSSSSSS             SUMNZ   D,S
    
    101000 EEEICCCC DDDDDDDDD SSSSSSSSS             MOV     D,S
    101001 EEEICCCC DDDDDDDDD SSSSSSSSS             NEG     D,S
    101010 EEEICCCC DDDDDDDDD SSSSSSSSS             ABS     D,S
    101011 EEEICCCC DDDDDDDDD SSSSSSSSS             ABSNEG  D,S
    101100 EEEICCCC DDDDDDDDD SSSSSSSSS             NEGC    D,S
    101101 EEEICCCC DDDDDDDDD SSSSSSSSS             NEGNC   D,S
    101110 EEEICCCC DDDDDDDDD SSSSSSSSS             NEGZ    D,S
    101111 EEEICCCC DDDDDDDDD SSSSSSSSS             NEGNZ   D,S
    
    110000 EEEICCCC DDDDDDDDD SSSSSSSSS             CMPS    D,S
    110001 EEEICCCC DDDDDDDDD SSSSSSSSS             CMPSX   D,S
    110010 EEEICCCC DDDDDDDDD SSSSSSSSS             ADDX    D,S
    110011 EEEICCCC DDDDDDDDD SSSSSSSSS             SUBX    D,S
    110100 EEEICCCC DDDDDDDDD SSSSSSSSS             ADDS    D,S
    110101 EEEICCCC DDDDDDDDD SSSSSSSSS             SUBS    D,S
    110110 EEEICCCC DDDDDDDDD SSSSSSSSS             ADDSX   D,S
    110111 EEEICCCC DDDDDDDDD SSSSSSSSS             SUBSX   D,S
    
    111000 EEEICCCC DDDDDDDDD SSSSSSSSS             INCMOD  D,S
    111001 EEEICCCC DDDDDDDDD SSSSSSSSS             DECMOD  D,S
    111010 EEEICCCC DDDDDDDDD SSSSSSSSS             CMPSUB  D,S
    
    111011 0E0ICCCC DDDDDDDDD SSSSSSSSS             WAITPEQ D,S
    111011 1E0ICCCC DDDDDDDDD SSSSSSSSS             WAITPNE D,S
    
    111100 00EICCCC DDDDDDDDD SSSSSSSSS             WAITCNT D,S
    111100 010ICCCC DDDDDDDDD SSSSSSSSS             WAITVID D,S
    111100 100ICCCC DDDDDDDDD SSSSSSSSS             CFGPINS D,S
    111100 1100CCCC DDDDDDDDD SSSSSSSSS             SETINDA D,S
    111100 1101CCCC DDDDDDDDD SSSSSSSSS             SETINDB D,S
    
    111101 000ICCCC DDDDDDDDD SSSSSSSSS             TJZ     D,S
    111101 010ICCCC DDDDDDDDD SSSSSSSSS             TJZD    D,S
    111101 100ICCCC DDDDDDDDD SSSSSSSSS             TJNZ    D,S
    111101 110ICCCC DDDDDDDDD SSSSSSSSS             TJNZD   D,S
    
    111110 00EICCCC DDDDDDDDD SSSSSSSSS             IJZ     D,S
    111110 01EICCCC DDDDDDDDD SSSSSSSSS             IJZD    D,S
    111110 10EICCCC DDDDDDDDD SSSSSSSSS             IJNZ    D,S
    111110 11EICCCC DDDDDDDDD SSSSSSSSS             IJNZD   D,S
    
    111111 00EICCCC DDDDDDDDD SSSSSSSSS             DJZ     D,S
    111111 01EICCCC DDDDDDDDD SSSSSSSSS             DJZD    D,S
    111111 10EICCCC DDDDDDDDD SSSSSSSSS             DJNZ    D,S
    111111 11EICCCC DDDDDDDDD SSSSSSSSS             DJNZD   D,S
    ----------------------------------------------------------------------------
    
    Regards
    Sapieha
    _____________________________________________________
    Nothing is impossible, there are only different degrees of difficulty.
    For every stupid question there is at least one intelligent answer.
    Don't guess - ask instead.
    If you don't ask you won't know.
    If your gonna construct something, make it as simple as possible yet as versatile/usable as possible.
  • Ken GraceyKen Gracey Posts: 6,550
    edited 2011-03-09 - 21:08:54
    Chip doesn't need any distractions right now. It's not in anybody's interest not to have him frequent the forums while he's immersed in design details and we're preparing for combining Beau's layout with the VHDL design using an external firm. Posting instruction sets will only take away time from coding, so I encourage him to stay away from the forums at this critical stage. Once we order a chip there will be a long delay in which we could request his time for sharing instruction sets. You'll be able to use this time for some development and he'll be more immersed in the tool side of the project.

    Sharing too many early details also creates a problem for P8X32A in that customers continually ask if they should wait for Propeller 2 for a specific design. If we're always talking about the "next chip" then there's less reason to use the current chip.

    You'll need to trust me that it's in everybody's interest that he continue to focus without distraction. The key features requested by our customers are built into the next chip.

    Just a friendly plea to let him work in peace.

    Thanks,

    Ken Gracey
    Parallax Inc.
  • potatoheadpotatohead Posts: 9,957
    edited 2011-03-09 - 21:19:01
    Well, I see two pointers? A B? Indirect mode for some instructions. REP is in there. Counter sync! Color transforms, and instructions for the dacs, and look at all the great math!

    Quad hub ops too. LMM will run sweet.

    Thanks for the look Beau.

    @Ken, yeah agreed. No worries here. I think that's the right call. Besides, now I've got this fun list of instructions to muse about.

    INCMOD? Increment with modulo maybe?
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
  • jazzedjazzed Posts: 11,803
    edited 2011-03-09 - 21:37:05
    There is lots of potential in the new instructions. I trust that they all have value. The list is certainly an interesting tease.
  • SapiehaSapieha Posts: 2,964
    edited 2011-03-09 - 21:42:59
    Hi Ken.

    I understand Yours standpoint. BUT my standpoint from my work on different designs give me other experiences.
    Working alone on one problem give many times back ends that are very difficult to overcome.

    BUT in this stage (Once we order a chip there will be a long delay in which we could request his time for sharing instruction sets.) it is to late if it is some mising instructions that can help be PROPELLER II much better.
    As You maybe already know that are discussions what can be done - It is nothing me else You STOP.
    If we're always talking about the "next chip" then there's less reason to use the current chip.

    P8X32A will never be stoned by Propeller II -- As them are no direct replacements for others "That need all on forum think on"
    Just a friendly plea to let him work in peace.

    YES --- BUT not be lost in space --- That not help him
    Regards
    Sapieha
    _____________________________________________________
    Nothing is impossible, there are only different degrees of difficulty.
    For every stupid question there is at least one intelligent answer.
    Don't guess - ask instead.
    If you don't ask you won't know.
    If your gonna construct something, make it as simple as possible yet as versatile/usable as possible.
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 22,519
    edited 2011-03-09 - 23:15:05
    Sapieha wrote:
    BUT in this stage (Once we order a chip there will be a long delay in which we could request his time for sharing instruction sets.) it is to late if it is some mising instructions that can help be PROPELLER II much better.
    I believe the design is frozen at this stage. So it's already too late to bend Chip's ear with yet more distracting suggestions. We had our chance over prior months to make suggestions and to influence the Prop II's direction. Now its Chip's turn to turn the design into working silicon. I'm with Ken: he should not be bothered at this stage in the process.

    -Phil
    “Perfection is achieved not when there is nothing more to add, but when there is nothing left to take away. -Antoine de Saint-Exupery
  • AleAle Posts: 2,358
    edited 2011-03-10 - 01:04:58
    The HC12 has also a SignEXtend instruction ;-)

    Just the names of the instructions are mind bogging... SNDSER ? RCVSER ? mmm those may be te ones we wanted for serial streams....
  • KaosKiddKaosKidd Posts: 296
    edited 2011-03-10 - 05:56:17
    Thanks for the update. I can well understand about distractions.
    Man, I can't wait to get one of these little puppies... Ok, maybe I can, but still... watching all of this for this long... Yeah... it's building.
    Thanks again for the update and instruction set list.

    KK
    Hope this helps. I can tell what time it is, but don't always know how to make a watch.
    KB3VYZ
  • Dave HeinDave Hein Posts: 5,982
    edited 2011-03-10 - 12:45:37
    RossH wrote: »
    Pehaps someone could do the whole forum a service and compare this to the existing instruction set and highlight the new/changed instructions?
    There's so many new instructions it was easier to highlight the ones that haven't changed. :) I put Spin comment braces around the old instructions so they should show up in blue in the Spin tool. Most of the ALU instructions have remained the same. It would be possble to write code that could run on both versions of the Prop, except the JMPRET instruction was moved to a different opcode, and the JMPRETD instruction uses the old opcode. It might be useful if the JMPRET stayed where it was.
  • RossHRossH Posts: 4,505
    edited 2011-03-10 - 13:53:06
    Dave Hein wrote: »
    There's so many new instructions it was easier to highlight the ones that haven't changed. :) I put Spin comment braces around the old instructions so they should show up in blue in the Spin tool. Most of the ALU instructions have remained the same. It would be possble to write code that could run on both versions of the Prop, except the JMPRET instruction was moved to a different opcode, and the JMPRETD instruction uses the old opcode. It might be useful if the JMPRET stayed where it was.
    Thanks Dave.

    Now comes the fun part - i.e. trying to figure out what the new instructions actually do!

    Ross.
    Catalina - a FREE ANSI C compiler for the Propeller.
    Download it from http://catalina-c.sourceforge.net/
  • Kevin WoodKevin Wood Posts: 1,266
    edited 2011-03-10 - 15:48:02
    Dave Hein wrote:
    It would be possble to write code that could run on both versions of the Prop, except the JMPRET instruction was moved to a different opcode, and the JMPRETD instruction uses the old opcode. It might be useful if the JMPRET stayed where it was.

    #ifdef should take care of that. :)
  • Dave HeinDave Hein Posts: 5,982
    edited 2011-03-10 - 15:58:06
    I should have been more specific about my comment on the JMPRET. If the current opcode is used then small chunks of binary code could run on either the Prop 1 or the Prop 2, as long as they use the instructions that use identical bit mapping. However, if you're only concerned about source level compatibility, then the bit values aren't important, and you don't even need to use an #ifdef. You would just need to use the Prop 1 instruction set. Of course, the #ifdef is needed if we want a single source file that is optimized for both versions of the chip.
  • Kevin WoodKevin Wood Posts: 1,266
    edited 2011-03-10 - 20:04:05
    I just threw that out there since conditional compilation is a frequently requested feature for Propeller Development. Given the point you raise, it's possible that it's planned for the Prop2 era Propeller Tool or IDE or whatever shows up.
  • potatoheadpotatohead Posts: 9,957
    edited 2011-03-10 - 20:22:42
    So... maybe we can start speculating!

    A lot of them make sense to me. Some of them don't!

    What do you guys think ENC is for?

    While waiting for the next bit of news, why not spend some idle time musing over what might be "in the box?"
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 22,519
    edited 2011-03-10 - 20:34:40
    ENC is in the Prop I instruction set as an unimplemented instruction. It's a priority encoder, returning the position of the highest "1" bit of S into D. BTW, I'm spending my "musing" time over how to eke more performance out of the Prop I. The Prop II will get here when it gets here.

    -Phil
    “Perfection is achieved not when there is nothing more to add, but when there is nothing left to take away. -Antoine de Saint-Exupery
  • Dave HeinDave Hein Posts: 5,982
    edited 2011-03-11 - 07:50:27
    I can see that some of the new instructions will greatly improve the performance of the Spin interpreter, as well as other PASM programs. The new pointer addressing modes will make bytecode and stack accesses more efficient. The instructions associated with encode, multiply, divide and square root will speed up those operations and reduce the amount of code needed in the Spin interpreter. The trick for optimal performance will be to hit the HUB access window, which will require six instructions between each HUB operation.

    LMM should also benefit from the new instructions. However, it seems like it will be a challenge to fully utilize each cycle between HUB accesses. The RDQUAD instruction should be very useful for loading up instructions for a LMM FCACHE operation.
  • Cluso99Cluso99 Posts: 15,657
    edited 2011-03-12 - 21:52:21
    I concurr with Ken that the PropII will cause some potential customers to wait for the PropII. In case they read this...
    The PropI is a different beast to the PropII. The PropI uses less power and is a smaller chip and will not be replaced by PropII. PropII is still some time away, so don't wait for it.

    Phil is correct in that we should continue to squeeze every ounce out of the Prop I. There are lots of things still to be found with the prop 1. I am still designing prop 1 pcbs because there is a lt of things yet to be done with the existing prop.

    Now, I have looked at the Prop II instructions. Here are some of those new instructions that I like.....
    * Test/Increment/Decrement Zero/NonZero Jump [Delayed]
    * Bit Set/Clear/Not/ISO and SET C/NC/Z/NC Any guesses as to what ISO means???
    * Repeat instructions
    * A lot of PIX and VID instructions
    * SNDSER/RCVSER look like some nice serial style instructions (probably usable for serial, I2C & SPI and others ???)
    There are certainly some interesting unknown instructions too. We shall have to wait to hear more about these later.
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
    P2: Tools & Code , Tricks & Traps
  • BigFootBigFoot Posts: 259
    edited 2011-03-13 - 08:13:37
    We have added a second Prop1 to our PoS terminal to share the work load and give us more code space,
    we hope to have it on the market by late summer.

    Our ultimate design will be biased on the Prop2 though. 32 megs of ram is really going to come in handy
    and some of the new video and serial instructions should speed things up and simplify our programs.
  • Cluso99Cluso99 Posts: 15,657
    edited 2011-03-13 - 17:38:38
    Overnight I remembered the fifos in the cog. Some of those instructions must be for acessing this.
    The serial instructions will hopefully allow us to also use them for inputting streams of bits. In hindsight it was something we missed in the existing prop.
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
    P2: Tools & Code , Tricks & Traps
  • Beau SchwabeBeau Schwabe Posts: 6,416
    edited 2011-03-19 - 15:38:48
    I had mentioned earlier that there were 320+ buss wires, the physical count is 412, where 316 of those wires extend around the entire peripheral of the core. There is a centroid buss that runs horizontally within the core that will consist of 700 wires. This buss will connect into the 'glue logic' after a proper driver stage.

    The attached views are of the PAD frame which right now is LVS/DRC clean. The Core 'guts' are next on the agenda where much of the 'glue logic' will be synthesized.
    1024 x 781 - 236K
    1024 x 781 - 234K
    1024 x 781 - 235K
    1024 x 781 - 216K
    1024 x 781 - 129K


    Beau Schwabe --- Robotics applications- PCB design, embedded software, and mechanical
    Oklahoma Robotics -

    www.Kit-Start.com - bschwabe@Kit-Start.com ෴෴ www.BScircuitDesigns.com - icbeau@bscircuitdesigns.com ෴෴

  • Cluso99Cluso99 Posts: 15,657
    edited 2011-03-19 - 16:00:04
    Thanks for posting Beau.

    From this I gather that you are back onto the layout for the final PropII (first rev) so that testing of the test die must have gone quite well.

    Can you give us any feedback on the testing when you have time?
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
    P2: Tools & Code , Tricks & Traps
  • Beau SchwabeBeau Schwabe Posts: 6,416
    edited 2011-03-19 - 16:07:41
    Cluso99,

    I'll ask Chip as far as the details with the I/O's but there was only one minor layout change I had to do with the I/O. The fuse test failed, but only because we goofed and left a layer that made the fuses a higher resistance than they should have been. ... as a result we couldn't drive enough current to POP them, instead we just made them a little warm. Other than that all of the memories passed, as well as some of the other blocks we were testing. So basically we have proven critical silicon that we can move forward with to be instantiated into Prop II.


    Beau Schwabe --- Robotics applications- PCB design, embedded software, and mechanical
    Oklahoma Robotics -

    www.Kit-Start.com - bschwabe@Kit-Start.com ෴෴ www.BScircuitDesigns.com - icbeau@bscircuitdesigns.com ෴෴

  • HShankoHShanko Posts: 402
    edited 2011-03-19 - 16:13:12
    Can you give us any feedback on the testing when you have time?
    Many of us 'second' this request. We are 'very thirsty' for such info.
    Harley Shanko
  • jazzedjazzed Posts: 11,803
    edited 2011-03-19 - 16:59:14
    So basically we have proven critical silicon that we can move forward with to be instantiated into Prop II.
    Nice progress. Thanks for the update.
  • Cluso99Cluso99 Posts: 15,657
    edited 2011-03-19 - 17:20:42
    Thanks Beau. That is really great news :) You should be very happy with such an excellent result. Bugs at this level are to be expected, so this seems like a very minor oversight.
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
    P2: Tools & Code , Tricks & Traps
  • Invent-O-DocInvent-O-Doc Posts: 768
    edited 2011-03-20 - 08:09:50
    This is great news! Thanks for the update Beau.

    Thomas Talbot, MD - New Market, Maryland, USA
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