Chip doesn't need any distractions right now. It's not in anybody's interest not to have him frequent the forums while he's immersed in design details and we're preparing for combining Beau's layout with the VHDL design using an external firm. Posting instruction sets will only take away time from coding, so I encourage him to stay away from the forums at this critical stage. Once we order a chip there will be a long delay in which we could request his time for sharing instruction sets. You'll be able to use this time for some development and he'll be more immersed in the tool side of the project.
Sharing too many early details also creates a problem for P8X32A in that customers continually ask if they should wait for Propeller 2 for a specific design. If we're always talking about the "next chip" then there's less reason to use the current chip.
You'll need to trust me that it's in everybody's interest that he continue to focus without distraction. The key features requested by our customers are built into the next chip.
Well, I see two pointers? A B? Indirect mode for some instructions. REP is in there. Counter sync! Color transforms, and instructions for the dacs, and look at all the great math!
Quad hub ops too. LMM will run sweet.
Thanks for the look Beau.
@Ken, yeah agreed. No worries here. I think that's the right call. Besides, now I've got this fun list of instructions to muse about.
I understand Yours standpoint. BUT my standpoint from my work on different designs give me other experiences.
Working alone on one problem give many times back ends that are very difficult to overcome.
BUT in this stage (Once we order a chip there will be a long delay in which we could request his time for sharing instruction sets.) it is to late if it is some mising instructions that can help be PROPELLER II much better.
As You maybe already know that are discussions what can be done - It is nothing me else You STOP.
If we're always talking about the "next chip" then there's less reason to use the current chip.
P8X32A will never be stoned by Propeller II -- As them are no direct replacements for others "That need all on forum think on"
Just a friendly plea to let him work in peace.
YES --- BUT not be lost in space --- That not help him
BUT in this stage (Once we order a chip there will be a long delay in which we could request his time for sharing instruction sets.) it is to late if it is some mising instructions that can help be PROPELLER II much better.
I believe the design is frozen at this stage. So it's already too late to bend Chip's ear with yet more distracting suggestions. We had our chance over prior months to make suggestions and to influence the Prop II's direction. Now its Chip's turn to turn the design into working silicon. I'm with Ken: he should not be bothered at this stage in the process.
Thanks for the update. I can well understand about distractions.
Man, I can't wait to get one of these little puppies... Ok, maybe I can, but still... watching all of this for this long... Yeah... it's building.
Thanks again for the update and instruction set list.
Pehaps someone could do the whole forum a service and compare this to the existing instruction set and highlight the new/changed instructions?
There's so many new instructions it was easier to highlight the ones that haven't changed. I put Spin comment braces around the old instructions so they should show up in blue in the Spin tool. Most of the ALU instructions have remained the same. It would be possble to write code that could run on both versions of the Prop, except the JMPRET instruction was moved to a different opcode, and the JMPRETD instruction uses the old opcode. It might be useful if the JMPRET stayed where it was.
There's so many new instructions it was easier to highlight the ones that haven't changed. I put Spin comment braces around the old instructions so they should show up in blue in the Spin tool. Most of the ALU instructions have remained the same. It would be possble to write code that could run on both versions of the Prop, except the JMPRET instruction was moved to a different opcode, and the JMPRETD instruction uses the old opcode. It might be useful if the JMPRET stayed where it was.
Thanks Dave.
Now comes the fun part - i.e. trying to figure out what the new instructions actually do!
It would be possble to write code that could run on both versions of the Prop, except the JMPRET instruction was moved to a different opcode, and the JMPRETD instruction uses the old opcode. It might be useful if the JMPRET stayed where it was.
I should have been more specific about my comment on the JMPRET. If the current opcode is used then small chunks of binary code could run on either the Prop 1 or the Prop 2, as long as they use the instructions that use identical bit mapping. However, if you're only concerned about source level compatibility, then the bit values aren't important, and you don't even need to use an #ifdef. You would just need to use the Prop 1 instruction set. Of course, the #ifdef is needed if we want a single source file that is optimized for both versions of the chip.
I just threw that out there since conditional compilation is a frequently requested feature for Propeller Development. Given the point you raise, it's possible that it's planned for the Prop2 era Propeller Tool or IDE or whatever shows up.
ENC is in the Prop I instruction set as an unimplemented instruction. It's a priority encoder, returning the position of the highest "1" bit of S into D. BTW, I'm spending my "musing" time over how to eke more performance out of the Prop I. The Prop II will get here when it gets here.
I can see that some of the new instructions will greatly improve the performance of the Spin interpreter, as well as other PASM programs. The new pointer addressing modes will make bytecode and stack accesses more efficient. The instructions associated with encode, multiply, divide and square root will speed up those operations and reduce the amount of code needed in the Spin interpreter. The trick for optimal performance will be to hit the HUB access window, which will require six instructions between each HUB operation.
LMM should also benefit from the new instructions. However, it seems like it will be a challenge to fully utilize each cycle between HUB accesses. The RDQUAD instruction should be very useful for loading up instructions for a LMM FCACHE operation.
I concurr with Ken that the PropII will cause some potential customers to wait for the PropII. In case they read this...
The PropI is a different beast to the PropII. The PropI uses less power and is a smaller chip and will not be replaced by PropII. PropII is still some time away, so don't wait for it.
Phil is correct in that we should continue to squeeze every ounce out of the Prop I. There are lots of things still to be found with the prop 1. I am still designing prop 1 pcbs because there is a lt of things yet to be done with the existing prop.
Now, I have looked at the Prop II instructions. Here are some of those new instructions that I like.....
* Test/Increment/Decrement Zero/NonZero Jump [Delayed]
* Bit Set/Clear/Not/ISO and SET C/NC/Z/NC Any guesses as to what ISO means???
* Repeat instructions
* A lot of PIX and VID instructions
* SNDSER/RCVSER look like some nice serial style instructions (probably usable for serial, I2C & SPI and others ???)
There are certainly some interesting unknown instructions too. We shall have to wait to hear more about these later.
We have added a second Prop1 to our PoS terminal to share the work load and give us more code space,
we hope to have it on the market by late summer.
Our ultimate design will be biased on the Prop2 though. 32 megs of ram is really going to come in handy
and some of the new video and serial instructions should speed things up and simplify our programs.
Overnight I remembered the fifos in the cog. Some of those instructions must be for acessing this.
The serial instructions will hopefully allow us to also use them for inputting streams of bits. In hindsight it was something we missed in the existing prop.
I had mentioned earlier that there were 320+ buss wires, the physical count is 412, where 316 of those wires extend around the entire peripheral of the core. There is a centroid buss that runs horizontally within the core that will consist of 700 wires. This buss will connect into the 'glue logic' after a proper driver stage.
The attached views are of the PAD frame which right now is LVS/DRC clean. The Core 'guts' are next on the agenda where much of the 'glue logic' will be synthesized.
I'll ask Chip as far as the details with the I/O's but there was only one minor layout change I had to do with the I/O. The fuse test failed, but only because we goofed and left a layer that made the fuses a higher resistance than they should have been. ... as a result we couldn't drive enough current to POP them, instead we just made them a little warm. Other than that all of the memories passed, as well as some of the other blocks we were testing. So basically we have proven critical silicon that we can move forward with to be instantiated into Prop II.
Thanks Beau. That is really great news You should be very happy with such an excellent result. Bugs at this level are to be expected, so this seems like a very minor oversight.
Comments
Are you volunteering?
No - Unfortunately, I'm at work at present. But I'm sure that by the time I get home someone else will have already done it!
Ross.
Too bad it's not USOB, that would be even better.
Bean
Not as good as the old Lockheed MAC-16 computer which had a SEX instruction for "sign extend".
SORRY for complains
Without additional info this list are not so useful
Sharing too many early details also creates a problem for P8X32A in that customers continually ask if they should wait for Propeller 2 for a specific design. If we're always talking about the "next chip" then there's less reason to use the current chip.
You'll need to trust me that it's in everybody's interest that he continue to focus without distraction. The key features requested by our customers are built into the next chip.
Just a friendly plea to let him work in peace.
Thanks,
Ken Gracey
Parallax Inc.
Quad hub ops too. LMM will run sweet.
Thanks for the look Beau.
@Ken, yeah agreed. No worries here. I think that's the right call. Besides, now I've got this fun list of instructions to muse about.
INCMOD? Increment with modulo maybe?
I understand Yours standpoint. BUT my standpoint from my work on different designs give me other experiences.
Working alone on one problem give many times back ends that are very difficult to overcome.
BUT in this stage (Once we order a chip there will be a long delay in which we could request his time for sharing instruction sets.) it is to late if it is some mising instructions that can help be PROPELLER II much better.
As You maybe already know that are discussions what can be done - It is nothing me else You STOP.
P8X32A will never be stoned by Propeller II -- As them are no direct replacements for others "That need all on forum think on"
YES --- BUT not be lost in space --- That not help him
-Phil
Just the names of the instructions are mind bogging... SNDSER ? RCVSER ? mmm those may be te ones we wanted for serial streams....
Man, I can't wait to get one of these little puppies... Ok, maybe I can, but still... watching all of this for this long... Yeah... it's building.
Thanks again for the update and instruction set list.
KK
Now comes the fun part - i.e. trying to figure out what the new instructions actually do!
Ross.
#ifdef should take care of that.
A lot of them make sense to me. Some of them don't!
What do you guys think ENC is for?
While waiting for the next bit of news, why not spend some idle time musing over what might be "in the box?"
-Phil
LMM should also benefit from the new instructions. However, it seems like it will be a challenge to fully utilize each cycle between HUB accesses. The RDQUAD instruction should be very useful for loading up instructions for a LMM FCACHE operation.
The PropI is a different beast to the PropII. The PropI uses less power and is a smaller chip and will not be replaced by PropII. PropII is still some time away, so don't wait for it.
Phil is correct in that we should continue to squeeze every ounce out of the Prop I. There are lots of things still to be found with the prop 1. I am still designing prop 1 pcbs because there is a lt of things yet to be done with the existing prop.
Now, I have looked at the Prop II instructions. Here are some of those new instructions that I like.....
* Test/Increment/Decrement Zero/NonZero Jump [Delayed]
* Bit Set/Clear/Not/ISO and SET C/NC/Z/NC Any guesses as to what ISO means???
* Repeat instructions
* A lot of PIX and VID instructions
* SNDSER/RCVSER look like some nice serial style instructions (probably usable for serial, I2C & SPI and others ???)
There are certainly some interesting unknown instructions too. We shall have to wait to hear more about these later.
we hope to have it on the market by late summer.
Our ultimate design will be biased on the Prop2 though. 32 megs of ram is really going to come in handy
and some of the new video and serial instructions should speed things up and simplify our programs.
The serial instructions will hopefully allow us to also use them for inputting streams of bits. In hindsight it was something we missed in the existing prop.
The attached views are of the PAD frame which right now is LVS/DRC clean. The Core 'guts' are next on the agenda where much of the 'glue logic' will be synthesized.
From this I gather that you are back onto the layout for the final PropII (first rev) so that testing of the test die must have gone quite well.
Can you give us any feedback on the testing when you have time?
I'll ask Chip as far as the details with the I/O's but there was only one minor layout change I had to do with the I/O. The fuse test failed, but only because we goofed and left a layer that made the fuses a higher resistance than they should have been. ... as a result we couldn't drive enough current to POP them, instead we just made them a little warm. Other than that all of the memories passed, as well as some of the other blocks we were testing. So basically we have proven critical silicon that we can move forward with to be instantiated into Prop II.