Understanding that development for the Prop II has been a fluid process and there are still possibilities of change, I've refrained from doing anything concrete in preparing for the Prop II's arrival, however, now having silicone in test and having the 128 pin package defined on the Prop II wiki, I'm wondering if it might be reasonably "Safe" to start doing some general lay-out work for my next generation boards?
Are things getting "Locked" enough that it might be OK to create a new Prop II part for the layout programs ( PCB123 & ExpressPCB ) to play with spacing and general fit? I don't mind moving a few pins around later if that's all it might be, but I also don't want to waste ALL of the time done in preliminary design work.
I have a board I designed with 3 Props on it ( because I needed the extra I/O ) That I would be nice to start "transferring" over to the Prop II. Is it still premature to start this kind of preliminary stuff... or are we getting close enough to a defined product that it might be OK to start doing something "REAL" to prepare for it's arrival?
I know better than to ask for a delivery date, but is there a fair degree of confidence that the pinout as currently defined might actually be final?
What happens to the chips along the process of being tested? What kind of testing? Do they ever become destroyed? Is there a board that is designed right off the bat to use with it?
What current products would have an advantage to have Prop II added to them?
What size breadboard should we use with the Prop II? It is bigger and has more pins. Are the acrylic cases going to have to be redesigned to allow for more board space?
Well, from what I saw and heard last time this was explained to me, this run will have all the key structures needed to verify functionality, and I suspect test some limits to see where the silicon does vary from the theory used to design it.
It's really a proto propeller, and it's got a removable top, so it can be measured and poked at in extreme detail.
After that data is collected, potentially some decisions change, others solidify, the real Propeller is then designed from the test data, and often referring to it.
That cycle will produce real chips that are going to be a lot like, if not ideally, the real deal.
IMHO, I agree with potatohead's assessment - it is way too early for anything to be locked down. If you read a few posts back, there is a description of just what is on the test chip. It is far from being a prototype chip in that sense. It is a conglomeration of blocks to check that certain functions work as expected. If all is OK, then a relaying process will be done with complete blocks which will then be run as another test chip.
Everything so far looks really good. There are a few issues, but we understand what they are.
- The resistors used for the FUSES mistakenly had Salicide Blockage resulting in a much higher resistance value, so we can't 'pop' them to test them. This was an error that was overlooked between both Chip and myself.
- The QUADPORT RAM (<- The MEM_COG) needed better signal isolation between the D and the R lines ... See attached BEFORE and AFTER layout image. The BIT cell has been modified, and a Ground line has been added between the D and the R lines.
Other than that the MEM_DUALPORT memory, the MEM_ROM, and the MEM_RAM were all ok. The other blocks ... PUD (Power Up Detect), BOD (Brown Out Detect), OSC (Internal Oscillator), PLL_MUL (Phase Lock Loop Multiplier) all tested ok as well.
Everything so far looks really good. There are a few issues, but we understand what they are.
- The resistors used for the FUSES mistakenly had Salicide Blockage resulting in a much higher resistance value, so we can't 'pop' them to test them. This was an error that was overlooked between both Chip and myself.
- The QUADPORT RAM (<- The MEM_COG) needed better signal isolation between the D and the R lines ... See attached BEFORE and AFTER layout image. The BIT cell has been modified, and a Ground line has been added between the D and the R lines.
Other than that the MEM_DUALPORT memory, the MEM_ROM, and the MEM_RAM were all ok. The other blocks ... PUD (Power Up Detect), BOD (Brown Out Detect), OSC (Internal Oscillator), PLL_MUL (Phase Lock Loop Multiplier) all tested ok as well.
It's because of the capacitance that D and R were coupling together. Placing a GND line between them doesn't eliminate the capacitance, and does increase it some, but the important part here is that D and R are no longer directly coupled together. Instead they are individually coupled to Ground
Sapieha,
I'm not sure I completely understand your question... the scale between the memory cell, and the XTAL I/O's is so different, you really can't look at them the same.
It's because of the capacitance that D and R were coupling together. Placing a GND line between them doesn't eliminate the capacitance, and does increase it some, but the important part here is that D and R are no longer directly coupled together. Instead they are individually coupled to Ground
We are finally in production with our Polaris PoS Terminal. We shipped the first 50 to customers before the
holidays. We couldn't cram in all the features that we wanted to but the Propeller II should help us do this
and more.
We make very smart Point of Sale Terminals for school cafeterias. Our first product was a PAD (Personal Access Device) so the kids could identify themselves.
The kids can enter there ID number into a keyboard, bar code reader or Bio Metric finger scanner. We have sold over 3000 of these Prop I based systems and they are doing very well. I am working on a similar PAD now that will control vending machines, we call it a Vending Pad. The whole idea is cashless sales, the parents put money in the kids accounts over the internet and can monitor exactly what they are eating.
Our latest product is a large PoS Terminal, it has 80 programmable food keys and 32 function keys. It also has a large 7" Color touch screen LCD display (232 x 480 x 16). Two Pads plug into the terminal so there can be two lines of kids feeding the cashier. The kids come up with there food, they can use the finger scanner on the Pads to identify them selves and there picture pops up on the terminal along with there account information. The cashier hits the proper food keys and the account is updated.
All of this is accomplished with one poor little over clocked Propeller 1 chip and a handful of I2C & Spi chips. I tried to include the spec sheet but it is over the forum's size limit.
Thank you BigFoot for the interesting info. Nice to hear so many Props are 'quietly' going into products such as yours. One Prop 1 doing all that work; great use of Parallax's neat IC,
Bigfoot: Congratulations, this is a great use of the prop. Perhaps you could put this up on a separate thread where others may find it and search for it.
Thanks for the kind words, we couldn't have done it with out the forum. You guys have some great ideas and we bypassed many a potential problem
by reading what others have done.
My guess would be this: if the testing went well, Beau is in a "a$$holes and elbows" mode (as the sergeant used say in the Army when we were about to pick up any litter). If problems in testing then there might be a revision of their test chip. Anyway, Chip and/or Beau might be very busy.
I too am awaiting any news on Prop 2 progress.....
Edit...apologies, by time I added my comment, I wasn't aware of previous posts for some reason. I had to reboot my iMac.
Edit#2..OK, just noticed the previous posts were 'old' ones. I think if they were ready to let us know more, we'd be told about their progress.
That's a good assessment, I must have left my web-cam on by mistake. Seriously though you are exactly right. Sorry I haven't posted any video in awhile, The test Die was one thing (small in size), but the Propeller II has 128 I/O pins around the peripheral. ... right now video is too much of a resource. Currently just for the I/O's there are 662,200 transistors.
Ramblings:
Currently I'm working on putting the I/O PAD frame together, while Chip is busy with the Verilog 'glue logic' for the COGs. Basically the I/O PAD frame is complete, but I'm having to step back a little and systematically check a few things because of some quirk issues in the layout tool. Tying all of the I/O's together is a HUGE wire buss that traverses the core perimeter consisting of 320+ wires. Each wire is 1um wide with 1um separation which normally would mean that the wire buss would need to occupy a width of at least 640 um. With multiple wire layers and allowing for escapement for Power/Ground into the core the wire buss is 216 um wide. The hardest part with 320+ wires is making a 90 deg turn at the corners. (Actually done with two 45 deg turns)
Basically we are moving forward, and are very busy.
Hi Beau! Thanks for the update! It sounds like exciting times continue at Parallax.
Any chance someone could post the Propeller II instruction set sometime soon?
Thanks very much for the update. Also, sorry to be so blunt but isn't 128 I/O somewhat excessive? (unless you plan for DRAM/parallel flash but that seems overkill).
Beau:
Ok, I get it, you mean from the chiop itself you have 128 pins connecting to your on chip circuit.
Also, nudge Chip about the Prop 2 instruction set, he said he would post them to the forums when he was chatting with us on the Savage Circuits Friday Night Chat.
Comments
Are things getting "Locked" enough that it might be OK to create a new Prop II part for the layout programs ( PCB123 & ExpressPCB ) to play with spacing and general fit? I don't mind moving a few pins around later if that's all it might be, but I also don't want to waste ALL of the time done in preliminary design work.
I have a board I designed with 3 Props on it ( because I needed the extra I/O ) That I would be nice to start "transferring" over to the Prop II. Is it still premature to start this kind of preliminary stuff... or are we getting close enough to a defined product that it might be OK to start doing something "REAL" to prepare for it's arrival?
I know better than to ask for a delivery date, but is there a fair degree of confidence that the pinout as currently defined might actually be final?
Ken Bash
What current products would have an advantage to have Prop II added to them?
What size breadboard should we use with the Prop II? It is bigger and has more pins. Are the acrylic cases going to have to be redesigned to allow for more board space?
It's really a proto propeller, and it's got a removable top, so it can be measured and poked at in extreme detail.
After that data is collected, potentially some decisions change, others solidify, the real Propeller is then designed from the test data, and often referring to it.
That cycle will produce real chips that are going to be a lot like, if not ideally, the real deal.
IMHO, it's early to be building boards.
Is there anything that you can tell us about the Prop II test chip, you guys must of had a chance to fire it up by now ?
Everything so far looks really good. There are a few issues, but we understand what they are.
- The resistors used for the FUSES mistakenly had Salicide Blockage resulting in a much higher resistance value, so we can't 'pop' them to test them. This was an error that was overlooked between both Chip and myself.
- The QUADPORT RAM (<- The MEM_COG) needed better signal isolation between the D and the R lines ... See attached BEFORE and AFTER layout image. The BIT cell has been modified, and a Ground line has been added between the D and the R lines.
Other than that the MEM_DUALPORT memory, the MEM_ROM, and the MEM_RAM were all ok. The other blocks ... PUD (Power Up Detect), BOD (Brown Out Detect), OSC (Internal Oscillator), PLL_MUL (Phase Lock Loop Multiplier) all tested ok as well.
The I/O is still under test.
Have You even that Ground line's betwen External Crystal inputs on XI, XO signals?
Sapieha,
I'm not sure I completely understand your question... the scale between the memory cell, and the XTAL I/O's is so different, you really can't look at them the same.
I know that BUT it still not answer my question
Thanks for the update.
We are finally in production with our Polaris PoS Terminal. We shipped the first 50 to customers before the
holidays. We couldn't cram in all the features that we wanted to but the Propeller II should help us do this
and more.
Interesting. Could you elaborate more. That was such a tease.
POS = point of sale? or something else? Any photo to give an idea of what's referred to?
We make very smart Point of Sale Terminals for school cafeterias. Our first product was a PAD (Personal Access Device) so the kids could identify themselves.
The kids can enter there ID number into a keyboard, bar code reader or Bio Metric finger scanner. We have sold over 3000 of these Prop I based systems and they are doing very well. I am working on a similar PAD now that will control vending machines, we call it a Vending Pad. The whole idea is cashless sales, the parents put money in the kids accounts over the internet and can monitor exactly what they are eating.
Our latest product is a large PoS Terminal, it has 80 programmable food keys and 32 function keys. It also has a large 7" Color touch screen LCD display (232 x 480 x 16). Two Pads plug into the terminal so there can be two lines of kids feeding the cashier. The kids come up with there food, they can use the finger scanner on the Pads to identify them selves and there picture pops up on the terminal along with there account information. The cashier hits the proper food keys and the account is updated.
All of this is accomplished with one poor little over clocked Propeller 1 chip and a handful of I2C & Spi chips. I tried to include the spec sheet but it is over the forum's size limit.
Bigfoot: Congratulations, this is a great use of the prop. Perhaps you could put this up on a separate thread where others may find it and search for it.
by reading what others have done.
I was wondering if you could give us an update on the Propeller II chip ?
I too am awaiting any news on Prop 2 progress.....
Edit...apologies, by time I added my comment, I wasn't aware of previous posts for some reason. I had to reboot my iMac.
Edit#2..OK, just noticed the previous posts were 'old' ones. I think if they were ready to let us know more, we'd be told about their progress.
That's a good assessment, I must have left my web-cam on by mistake. Seriously though you are exactly right. Sorry I haven't posted any video in awhile, The test Die was one thing (small in size), but the Propeller II has 128 I/O pins around the peripheral. ... right now video is too much of a resource. Currently just for the I/O's there are 662,200 transistors.
Ramblings:
Currently I'm working on putting the I/O PAD frame together, while Chip is busy with the Verilog 'glue logic' for the COGs. Basically the I/O PAD frame is complete, but I'm having to step back a little and systematically check a few things because of some quirk issues in the layout tool. Tying all of the I/O's together is a HUGE wire buss that traverses the core perimeter consisting of 320+ wires. Each wire is 1um wide with 1um separation which normally would mean that the wire buss would need to occupy a width of at least 640 um. With multiple wire layers and allowing for escapement for Power/Ground into the core the wire buss is 216 um wide. The hardest part with 320+ wires is making a 90 deg turn at the corners. (Actually done with two 45 deg turns)
Basically we are moving forward, and are very busy.
Any chance someone could post the Propeller II instruction set sometime soon?
Thanks very much for the update. Also, sorry to be so blunt but isn't 128 I/O somewhat excessive? (unless you plan for DRAM/parallel flash but that seems overkill).
If I know correctly 96 I/O external --- All other Internal
Dave Hein,
I don't have any of the instructions. I'm sure when Chip can come up for air, he will post them.
Ok, I get it, you mean from the chiop itself you have 128 pins connecting to your on chip circuit.
Also, nudge Chip about the Prop 2 instruction set, he said he would post them to the forums when he was chatting with us on the Savage Circuits Friday Night Chat.
Roy
Great stuff Beau - thanks to you and Chip.
Pehaps someone could do the whole forum a service and compare this to the existing instruction set and highlight the new/changed instructions?
Then we can all get busy on updating our respective compilers/interpreters/application programs for the Prop II.
Ross.