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Smartpin Diagram (now with %P..P bit mode table)

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  • RaymanRayman Posts: 11,844
    edited 2020-04-15 00:52
    What mode uses Smart_DAC?
  • evanhevanh Posts: 10,439
    edited 2020-04-15 01:11
    Rayman wrote: »
    Do you think what I called “smart cell” as “smartpin”?
    Yes, it's easy to think of that one block as a processor in its own right.

    Also, the whole custom ring side is entirely separate both geographically and development wise. The smartpin feature set didn't evolve until quite late and there was substantial change in the verilog over that time.

    Geographically, there is a long route out from the cluster of synthesised logic around the smartpins to the physical pad ring. I'd bet they are right in the centre of the die.

  • evanhevanh Posts: 10,439
    Rayman wrote: »
    What mode uses Smart_DAC?
    The first three smartpin modes, DAC noise, DAC 16-bit dither(noise) and 16-bit dither(PWM) are feed the DAC. They need a way to get 8-bit data to the DAC network.

  • evanhevanh Posts: 10,439
    evanh wrote: »
    Rayman wrote: »
    Do you think what I called “smart cell” as “smartpin”?
    Yes, it's easy to think of that one block as a processor in its own right.
    It is actually the main reason I made the first ascii drawing. I wanted to point out how the pin modes have quite some independence of the smartpin modes.

  • RaymanRayman Posts: 11,844
    edited 2020-04-15 01:46
    Is there an M where OUT goes directly to SMART_OUT? If so, maybe show in same way as IN...

    I'll think about "Smart Cell" name... Maybe "Smart Pin" is better...
  • evanhevanh Posts: 10,439
    edited 2020-04-15 02:19
    Rayman wrote: »
    Is there an M where OUT goes directly to SMART_OUT? If so, maybe show in same way as IN...
    I did have it like that in first drawing but OUT is not used as an input by the smartpin processor in any way. So I've got the T block (Logic Output) handling all the OUT spaghetti routing.

    PS: And you'll note I've got DIR going to both, because DIR is used to reset the smartpin processor as well as pin output enable.
  • evanhevanh Posts: 10,439
    edited 2020-04-15 03:53
    I've added Enable to the DAC network. It doesn't show the interlocking but it's a real input for DAC action.
                .......................             :               ..........................
                : Custom I/O Pad Ring :             :               : Synthesised Core Logic :
                '''''''''''''''''''''''             :               ''''''''''''''''''''''''''
                                                    :
                                                    :                             CogDAC (Streamers/Cogs)
                                                    :          [%%%%%%%%%%%%%]<============================= cog0
                                                    :          [             ]<============================= cog1
                                                    :          [   DAC bus   ]<============================= cog2
                           [%%%%%%%%%%%%%]          :          [   select    ]<============================= cog3
                           [  Flash DAC  ]          :          [             ]<============================= cog4
                           [   Network   ]<=====++=============[   (%P...P)  ]<============================= cog5
                    |<-----[             ]      ||  :          [             ]<============================= cog6
                    |      [   (%P...P)  ]      ||  :          [             ]<============================= cog7
                    |      [             ]<-    ||  :          [%%%%%%%%%%%%%]<===\\
                    |      [%%%%%%%%%%%%%]  |   ||  :               ^             ||
                    |                       |   ||  :               |   ------------------------------------- RND
                    |                       |   ||  :        BitDAC |  | Other    ||
                    |      [%%%%%%%%%%%%%]  |   ||  :               |  v          ||SmartDAC
                    |      [    Logic    ]  |   ||  :          [%%%%%%%%%%%%%]    ||
                    |      [    Drive    ]  |   ||  :   Enable [             ]<------------------------------ OUT
                    |      [             ]<-+------------------[    Logic    ]    ||
    [%%%%%%%%]      |<-----[   (%P...P)  ]      ||  :   Output [    Output   ]<---------------------------+-- DIR
    [        ]      |      [             ]<-------------+------[             ]    ||                      |
    [Physical]      |      [%%%%%%%%%%%%%]      ||  :   |      [    (%TT)    ]    ||    [%%%%%%%%%%%%]    |
    [ Even # ]------+            ^              ||  :   |      [  (%MMMMM_0) ]    \\====[            ]    |
    [ Pin Pad]      |            |              ||  :   |  OUT [             ]          [   Even #   ]<---
    [        ]      |       Feed |       CompDAC||  :   |   ---[             ]<---------[  Smartpin  ]
    [%%%%%%%%]      |       back |              ||  :   |  |   [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ]
                    |            |              ||  :   |  |                            [            ]
                    |      [%%%%%%%%%%%%%]      ||  :   |  |                            [  [X reg]===]<==== WXPIN
                    |      [  Comparator ]<=====//  :   |  |     -1  -2  -3             [  [Y reg]===]<==== WYPIN
                    |      [             ]          :   |  |      |   |   |             [  [Z reg]===]====> RDPIN
                    | PinB [             ]          :   |  |      v   v   v             [            ]
                  -------->[  Pin Input  ]          :   |  |   [%%%%%%%%%%%%%]      A   [            ]
                 |  | PinA [   (%P...P)  ]          :   |   -->[ Logic Input ]--------->[---o----o---]-------> IN
                 |  +----->[             ]          :   |      [   (A_B_F)   ]      B   [  (M == 0)  ]
                 |  |      [             ]-------------------->[             ]--------->[            ]
                 |  |      [ Sigma-Delta ]          :   |      [%%%%%%%%%%%%%]          [            ]<------ ACK
                 |  |      [     ADC     ]          :   |         ^   ^   ^             [%%%%%%%%%%%%]
                 |  |      [%%%%%%%%%%%%%]          :   |         |   |   |
                 |  |                               :   |        +1  +2  +3
                 |  |                               :   |
                 |  |                               :   |
                 |  |                               :   |                         CogDAC (Streamers/Cogs)
                 |  |                               :   |      [%%%%%%%%%%%%%]<============================= cog0
                 |  |                               :   |      [             ]<============================= cog1
                 |  |                               :   |      [   DAC bus   ]<============================= cog2
                 |  |      [%%%%%%%%%%%%%]          :   |      [   select    ]<============================= cog3
                 |  |      [  Flash DAC  ]          :   |      [             ]<============================= cog4
                 |  |      [   Network   ]<=====++=============[   (%P...P)  ]<============================= cog5
                 |<--------[             ]      ||  :   |      [             ]<============================= cog6
                 |  |      [   (%P...P)  ]      ||  :   |      [             ]<============================= cog7
                 |  |      [             ]<-    ||  :   |      [%%%%%%%%%%%%%]<===\\
                 |  |      [%%%%%%%%%%%%%]  |   ||  :   |              ^          ||
                 |  |                       |   ||  :    -----------   |          ||
                 |  |                       |   ||  :         Other |  |BitDAC    || SmartDAC
                 |  |      [%%%%%%%%%%%%%]  |   ||  :               v  |          ||
                 |  |      [    Logic    ]  |   ||  :          [%%%%%%%%%%%%%]    ||
                 |  |      [    Drive    ]  |   ||  :   Enable [             ]<------------------------------ OUT
                 |  |      [             ]<-+------------------[    Logic    ]    ||
    [%%%%%%%%]   |<--------[   (%P...P)  ]      ||  :   Output [    Output   ]<---------------------------+-- DIR
    [        ]   |  |      [             ]<--------------------[             ]    ||                      |
    [Physical]   |  |      [%%%%%%%%%%%%%]      ||  :          [    (%TT)    ]    ||    [%%%%%%%%%%%%]    |
    [ Odd #  ]---+  |            ^              ||  :          [  (%MMMMM_0) ]    \\====[            ]    |
    [ Pin Pad]   |  |            |              ||  :      OUT [             ]          [   Odd #    ]<---
    [        ]   |  |       Feed |       CompDAC||  :       ---[             ]<---------[  Smartpin  ]
    [%%%%%%%%]   |  |       back |              ||  :      |   [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ]
                 |  |            |              ||  :      |                            [            ]
                 |  |      [%%%%%%%%%%%%%]      ||  :      |                            [  [X reg]===]<==== WXPIN
                 |  |      [  Comparator ]<=====//  :      |     -1  -2  -3             [  [Y reg]===]<==== WYPIN
                 |  |      [             ]          :      |      |   |   |             [  [Z reg]===]====> RDPIN
                 |  |      [             ]          :      |      v   v   v             [            ]
                 |  | PinB [  Pin Input  ]          :      |   [%%%%%%%%%%%%%]      A   [            ]
                 |   ----->[   (%P...P)  ]          :       -->[ Logic Input ]--------->[---o----o---]-------> IN
                 |    PinA [             ]          :          [   (A_B_F)   ]      B   [  (M == 0)  ]
                  -------->[             ]-------------------->[             ]--------->[            ]
                           [ Sigma-Delta ]          :          [%%%%%%%%%%%%%]          [            ]<------ ACK
                           [     ADC     ]          :             ^   ^   ^             [%%%%%%%%%%%%]
                           [%%%%%%%%%%%%%]          :             |   |   |
                                                    :            +1  +2  +3
                                                    :
                .......................             :               ..........................
                : Custom I/O Pad Ring :             :               : Synthesised Core Logic :
                '''''''''''''''''''''''             :               ''''''''''''''''''''''''''
    

    EDIT2: Drawing reinstated
  • evanhevanh Posts: 10,439
    edited 2020-04-15 03:06
    evanh wrote: »
    evanh wrote: »
    Rayman wrote: »
    Do you think what I called “smart cell” as “smartpin”?
    Yes, it's easy to think of that one block as a processor in its own right.
    It is actually the main reason I made the first ascii drawing. I wanted to point out how the pin modes have quite some independence of the smartpin modes.
    This solidified for me after I got a streamer outputting to a smartpin and that smartpin outputting to its pin all in the one WRPIN config, ie: OUT was being used as an input (Via the F block importantly) to the smartpin while simultaneously the smartpin could still drive the output!

    EDIT: When I say importantly, this is because it needed an A/B selection of OUT to be made. So the smartpin processor only sees it as A and B inputs.
  • evanhevanh Posts: 10,439
    edited 2020-04-15 03:57
    Okay, I could have OUT going directly to the F block instead going via the T block ... I might have to separate OUT into two to prevent clutter though.

    EDIT: Okay, certainly easier to do it that way.
    EDIT2: Err, no, retesting it finds that's wrong. DIR definitely plays a part at that point. OUT has to go through the T block first.

    PS: Exploding the T block would be most useful next thing to attempt.

  • evanhevanh Posts: 10,439
    edited 2020-04-15 07:39
    Chip,
    Thought I start with the easy block and tried to get my head around the de-glitch wiring in the F block. Turns out I haven't got a handle on that at all.

    The principle of it is easy enough but I'm struggling to sort out how the global part of it works. Each instance has to take L samples at T interval with unanimous state changes. Problem I'm struggling with is how these two parameters become effective, via the four global filt, at the F blocks? It can't just be a bit line for each global filt.

  • cgraceycgracey Posts: 13,412
    evanh wrote: »
    Chip,
    Thought I start with the easy block and tried to get my head around the de-glitch wiring in the F block. Turns out I haven't got a handle on that at all.

    The principle of it is easy enough but I'm struggling to sort out how the global part of it works. Each instance has to take L samples at T interval with unanimous state changes. Problem I'm struggling with is how these two parameters become effective, via the four global filt, at the F blocks? It can't just be a bit line for each global filt.

    Using the HUBSET instruction, you can set each of the four global filter settings. On a per-pin basis, you can select one of those four filter settings. If I recall, the hub outputs the four sets of 1-bit enables and 2-bit filter sizes (12 bits, in all), while the pin muxes the specific enable and filter-size signals, using local flops to realize the actual filter.
  • evanhevanh Posts: 10,439
    Sounds like what I need, thanks.

  • RaymanRayman Posts: 11,844
    cgracey wrote: »
    Rayman wrote: »
    What's a good name for this box?

    I don't know, but on the right side, it would be good to show OUT and ACK going into the box.

    @Evanh: Chip said Out should go to "Smart Cell" (or whatever we should call it). You have it just going to Logic Output... Should it go to both?
  • RaymanRayman Posts: 11,844
    edited 2020-04-15 17:35
    I added in that enable for the DAC output.
    Edit: Also changed COMP_DAC to Comp&DAC...
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  • RaymanRayman Posts: 11,844
    I'm thinking the even pin would be the -1 input to the odd pin and the odd pin would be +1 input to the even pin, right?
    Like this:
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  • cgraceycgracey Posts: 13,412
    Rayman wrote: »
    I'm thinking the even pin would be the -1 input to the odd pin and the odd pin would be +1 input to the even pin, right?
    Like this:

    That's right.
  • I don't see any CPU clock delays on Rayman's diagram. Both the inputs and outputs have that optional delay. The DAC and ADC are clocked.

    Plus it takes even more clocks to get to and from each cog. I'm hoping someone could shed some light where the clock delays are in the diagram.
  • I think the ADC -> GETSCP/Streamer path is missing.
  • RaymanRayman Posts: 11,844
    Maybe the Comp&DAC bus is bidirectional ?
  • RaymanRayman Posts: 11,844
    Chip’s diagram has a lot more info
  • evanhevanh Posts: 10,439
    edited 2020-04-16 04:14
    Rayman,
    OUT does not go to the smartpin processor. The only way OUT reaches there is via A/B input selection in the F block.


    Whicker,
    I'm not sure how informative those would be. There is also other places where staging flops exist other than just the extra for distance/fanout.


    Wuerfel_21,
    The GETSCP scope feature uses the RDPIN data buses to gather it's data I believe.

  • evanhevanh Posts: 10,439
    edited 2020-04-16 05:10
    Rayman wrote: »
    Chip’s diagram has a lot more info
    Chip's diagram stops at the dotted line. It only covers the custom pad ring. It was very helpful for nailing down exactly what should be drawn on each side of that line though. It also confirmed a number of things like output+enable rather than driveH+driveL.

    Rayman wrote: »
    Maybe the Comp&DAC bus is bidirectional ?
    Definitely not! It just goes to two DACs is all. The main one is low impedance, the comparator one is high impedance.

    EDIT: Actually, it's not specifically just a DAC bus at that stage. It's actaully M[7:0], as per the old Pad I/O Modes sheet, and gets used for config too. At any rate there is no bidirectional signals crossing the dotted line between the custom ring and the synthesised core.
    PAD_IO_modes.png
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  • evanhevanh Posts: 10,439
    edited 2020-04-16 05:02
    M[12:0] on that sheet is the same M[12:0] in the new I/O block diagram Chip just did - https://forums.parallax.com/discussion/comment/1494131/#Comment_1494131

    EDIT: PI is the only input signal crossing the dotted line. This is what goes into the F block in my diagrams and eventually becomes IN at the cogs. PO is what I've called Output. DIR I've called Enable because DIR from a cog is not always what is controlling it.
  • evanhevanh Posts: 10,439
    edited 2020-04-16 09:30
    One interesting trivia to come from examining Chip's diagram is that "Input" within the pad ring is slightly different to the PI that crosses the dotted line. Practically, they are the same signal though. I don't see any mode, namely with ADC operating, that uses them separately.

  • RaymanRayman Posts: 11,844
    Ok, I moved OUT back where it was...
    Is this better?
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  • evanhevanh Posts: 10,439
    Yep, thanks.
  • evanhevanh Posts: 10,439
    edited 2020-04-16 23:22
    What I've called SmartOUT, Chip has just called SMART in the %TT section in the main doc. So there is three possible sources (OUT/Other/SmartOUT) for both Output and BitDAC.

    DAC_MODE in Chip's docs is not a specific data path so I've dropped its use. DAC mode is a setting to switch over to using the DAC network instead of the logic drive circuit. You could say the two blocks across the top of my diagram is DAC mode.

  • RaymanRayman Posts: 11,844
    @evanh, so you are ok with last version I posted?
  • evanhevanh Posts: 10,439
    I prefer Smartpin over Smartcell.

  • RaymanRayman Posts: 11,844
    Ok, here you go:
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