Thanks. I know Chip has used the term in both contexts but I'd like to see "Smartpin" be used for only one meaning. The docs generally support my interpretation even if not explicitly declared.
rather than "smartpin", which is a registered trademark.
Oh. is that the problem. ... does a google ... LOL, so many of them. There is lots of different trademarks of that name. I doubt that's a concern, they aren't copyright claims.
And Smartcell is a company name. So that's no better.
Extraneous, IN and IN[n] are the same. EDIT: Okay, I guess that is technically better since it does show the two IN's in the block diagram are distinct paths.
EDIT2: You'll be doing it for every label if go down that path though.
An alternative is pack the diagram down to one pin and somehow detail the odd/even differences.
In Chip's schematic for the whole custom pin cell he's used the symbols PA and PB. There is no odd/even naming because there is no difference other than being a pin pair. In the odd # pin PB is the even # pin, and in the even # pin PB is the odd # pin.
Really, the main difference between odd and even pins is how "Other" is treated.
I think we should say something about USB... I'm not exactly sure how even and odd are connected in this mode, but the even pin is D- (master Brain) and the odd pin is D+ (slave Passive).
Added this to Smart Pin sections
Oh, you know how I've said "PI" and "Input" are practically the same signal in Chip's block diagram. Lets just make it so in ours. This means that my "Feedback" is the same as the logic input crossing the dotted line. ie: They can be made the same and it'll look clearer what the feedback is and also match up with the Pad IO Modes sheet.
Oh, bugger, maybe I've put you wrong. It seemed a good idea for a short while. The problem with this new diagram arrangement is it makes it look like the ADC bitstream can reach the feedback when it really can't. That's the one actual difference between Chip's INPUT and the Input I've got there.
Do we care? It looks tidy right now.
EDIT: Maybe I should have a go at breaking that block up ... It'll bloat quite a lot I think ...
Okay, done a halfway job of splitting up the Pin Input block. It corrects that "Input" detail. And I've dumped the block name in favour of full mode list instead.
Chip will need to comment on whether USB has a difference in the smartpins or if it's just the PinA/B pairing that makes the diff.
TDMS encoding for DVI/HDMI is done in the CMOD hardware, which is a stage of the streamers.
In an even/odd pair, all the USB smart pin logic is in the even pin. The odd pin just has conduit for control from the even pin. The even pin controls HHH and LLL modes for both pins in the pair.
Comments
I've always called it "smart pin", as an adjective, rather than "smartpin", which is a registered trademark.
And Smartcell is a company name. So that's no better.
Same for IN
But we don’t have to
Symbol name "INPUT" in Chip's block diagram.
EDIT2: You'll be doing it for every label if go down that path though.
In Chip's schematic for the whole custom pin cell he's used the symbols PA and PB. There is no odd/even naming because there is no difference other than being a pin pair. In the odd # pin PB is the even # pin, and in the even # pin PB is the odd # pin.
Really, the main difference between odd and even pins is how "Other" is treated.
Added this to Smart Pin sections
TDMS encoding for DVI/HDMI is done in the CMOD hardware, which is a stage of the streamers.
[%%%%%%%%%%%%%] | || : v | [ Logic ] | || : [%%%%%%%%%%%%%] [ Drive ] | || : Enable [ ] [ ]<-+------------------[ Logic ] ------[ (%P...P) ] || : Output [ Output ] [ ]<--------------------[ ] [%%%%%%%%%%%%%] || : [ (%TT) ] ^ || : [ (%MMMMM_0) ] | || : OUT [ ] | || : ---[ ] ----------- || : | [%%%%%%%%%%%%%] | || : | [%%%%%%%%%%%%%] | || : | [ Comparator ]<=====// : | -1 -2 -3 [ ] | : | | | | [ ] | : | v v v PinB [ Pin Input ] | : | [%%%%%%%%%%%%%] ----->[ (%P...P) ] | : -->[ Logic Input ] PinA [ ] | : [ (A_B_F) ] ----->[ ]---+---------------->[ ] [ Sigma-Delta ] Input : [%%%%%%%%%%%%%] [ ADC ] : ^ ^ ^ [%%%%%%%%%%%%%] : | | | : +1 +2 +3Do we care? It looks tidy right now.
EDIT: Maybe I should have a go at breaking that block up ... It'll bloat quite a lot I think ...
....................... : .......................... : Custom I/O Pad Ring : : : Synthesised Core Logic : ''''''''''''''''''''''' : '''''''''''''''''''''''''' : : CogDAC (Streamers/Cogs) : [%%%%%%%%%%%%%]<============================= cog0 : [ ]<============================= cog1 [%%%%%%%%%%%%%] : [ DAC bus ]<============================= cog2 | [ Flash DAC ]<=====++=======================[ select ]<============================= cog3 |<-----[ Network ] || : [ ]<============================= cog4 | [ (%P...P) ] || : [ (%P...P) ]<============================= cog5 | [ ]<- || : [ ]<============================= cog6 | [%%%%%%%%%%%%%] | || : [ ]<============================= cog7 | | || : [%%%%%%%%%%%%%]<===\\ | | || : ^ || | [%%%%%%%%%%%%%] | || : | ------------------------------------- RND | [ Logic Drive ]<-+-------------- : BitDAC | | Other || [%%%%%%%%] |<-----[ (%P...P) ] || | : | v ||SmartDAC [ ] | [ ]<-------------- | : [%%%%%%%%%%%%%] || [Physical] | [%%%%%%%%%%%%%] || | | : Enable [ ]<------------------------------ OUT [ Even # ]------+ ^ || | -------------[ Logic ] || [ Pin Pad] | | || | : Output [ Output ]<---------------------------+-- DIR [ ] | ----------- || --------+------[ ] || | [%%%%%%%%] | | || : | [ (%TT) ] || [%%%%%%%%%%%%] | | | || : | [ (%MMMMM_0) ] \\====[ ] | | | || : | OUT [ ] [ Even # ]<--- | [%%%%%%%%%%%%%] | || CompDAC : | ---[ ]<---------[ Smartpin ] | PinB [ Comparator ]<=====// : | | [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ] -------->[ & Logic ] | : | | [ ] | | PinA [ & Schmitt ] | : | | [ (X reg)===]<==== WXPIN | +----->[ (%P...P) ]---+ : | | -1 -2 -3 [ (Y reg)===]<==== WYPIN | | [ ] |"Input" : | | | | | [ (Z reg)===]====> RDPIN | | [%%%%%%%%%%%%%] | : | | v v v [ ] | | | : | | [%%%%%%%%%%%%%] A [ ] | | | [%%%%%%%%] : | -->[ Logic Input ]--------->[---o----o---]-------> IN | | [%%%%%%%%%%%%%] --->[ Mux ] : | [ (A_B_F) ] B [ (M == 0) ] | | PinA [ Sigma-Delta ] [(%P...P)]------------>[ ]--------->[ ] | +----->[ ADC ]------->[ ] : | [%%%%%%%%%%%%%] [ ]<------ ACK | | [ (%P...P) ] [%%%%%%%%] : | ^ ^ ^ [ USB D- ] | | [%%%%%%%%%%%%%] : | | | | [ brain ] | | : | +1 +2 +3 [%%%%%%%%%%%%] | | : | | | : | | | : | CogDAC (Streamers/Cogs) | | : | [%%%%%%%%%%%%%]<============================= cog0 | | : | [ ]<============================= cog1 | | [%%%%%%%%%%%%%] : | [ DAC bus ]<============================= cog2 | | [ Flash DAC ]<=====++=======================[ select ]<============================= cog3 |<--------[ Network ] || : | [ ]<============================= cog4 | | [ (%P...P) ] || : | [ (%P...P) ]<============================= cog5 | | [ ]<- || : | [ ]<============================= cog6 | | [%%%%%%%%%%%%%] | || : | [ ]<============================= cog7 | | | || : | [%%%%%%%%%%%%%]<===\\ | | | || : | ^ || | | [%%%%%%%%%%%%%] | || : ----------- | || | | [ Logic Drive ]<-+-------------- : Other | |BitDAC || SmartDAC [%%%%%%%%] |<--------[ (%P...P) ] || | : v | || [ ] | | [ ]<-------------- | : [%%%%%%%%%%%%%] || [Physical] | | [%%%%%%%%%%%%%] || | | : Enable [ ]<------------------------------ OUT [ Odd # ]---+ | ^ || | -------------[ Logic ] || [ Pin Pad] | | | || | : Output [ Output ]<---------------------------+-- DIR [ ] | | ----------- || ---------------[ ] || | [%%%%%%%%] | | | || : [ (%TT) ] || [%%%%%%%%%%%%] | | | | || : [ (%MMMMM_0) ] \\====[ ] | | | | || : OUT [ ] [ Odd # ]<--- | | [%%%%%%%%%%%%%] | || CompDAC : ---[ ]<---------[ Smartpin ] | | PinB [ Comparator ]<=====// : | [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ] | ----->[ & Logic ] | : | [ ] | PinA [ & Schmitt ] | : | [ (X reg)===]<==== WXPIN +-------->[ (%P...P) ]---+ : | -1 -2 -3 [ (Y reg)===]<==== WYPIN | [ ] |"Input" : | | | | [ (Z reg)===]====> RDPIN | [%%%%%%%%%%%%%] | : | v v v [ ] | | : | [%%%%%%%%%%%%%] A [ ] | | [%%%%%%%%] : -->[ Logic Input ]--------->[---o----o---]-------> IN | [%%%%%%%%%%%%%] --->[ Mux ] : [ (A_B_F) ] B [ (M == 0) ] | PinA [ Sigma-Delta ] [(%P...P)]------------>[ ]--------->[ ] -------->[ ADC ]------->[ ] : [%%%%%%%%%%%%%] [ ]<------ ACK [ (%P...P) ] [%%%%%%%%] : ^ ^ ^ [ USB D+ ] [%%%%%%%%%%%%%] : | | | [ passive ] : +1 +2 +3 [%%%%%%%%%%%%] : ....................... : .......................... : Custom I/O Pad Ring : : : Synthesised Core Logic : ''''''''''''''''''''''' : ''''''''''''''''''''''''''Is it doing more than selecting one of several inputs?
In an even/odd pair, all the USB smart pin logic is in the even pin. The odd pin just has conduit for control from the even pin. The even pin controls HHH and LLL modes for both pins in the pair.