Smartpin Diagram (now with %P..P bit mode table)

245678

Comments

  • I've got the latest version of the schematic editor, SPICE, and waveform viewer running. It actually works okay, though an intermediate version hadn't presented the schematic properly. So, I can make a proper diagram of the smart pin.
  • Happy happy.
  • Rayman,
    I'll get you to update the drawing to match my fix for "Other" - https://forums.parallax.com/discussion/comment/1492991/#Comment_1492991
  • I was thinking Chip was going to post something on this... but maybe not
  • Same. But it was likely tricky/difficult for him to summarise his custom schematic without it being one massive dump.
  • I wonder if we can think of the register written by WRPIN as the "R" register... Might make things easier to understand... (?)
  • I will make a diagram soon.
  • @evanh: This look right?
    1217 x 1184 - 112K
  • Yep. Looks right.
    Are those Cog_DAC buses drawn thicker? They barely stand out. Making everything else thinner would help a lot. BTW, Smart_DAC and DAC_Mode are also 8-bit buses.

  • Output 8- bit too?
  • No, that's the plain logic "OUT" but it's mux'd in various ways. Hmm, the DAC section in the synthesised logic probably should've been separated.
  • How does 8-bit bus from DAC bus select get over to Flash DAC Network?
  • DAC_mode

  • How does it get there without a bus?
  • evanhevanh Posts: 9,958
    edited 2020-04-13 - 22:19:24
    "DAC_mode" is 8-bit wide. As is Smart_DAC.
  • evanhevanh Posts: 9,958
    edited 2020-04-18 - 23:39:12

    NOTE: Latest edition - https://forums.parallax.com/discussion/comment/1473762/#Comment_1473762


    Here's my first attempt to split off the DAC section. It's not complete though, BITDAC mode doesn't fit.
                .......................          :               ..........................
                : Custom I/O Pad Ring :          :               : Synthesised Core Logic :
                '''''''''''''''''''''''          :               ''''''''''''''''''''''''''
                                                 :
                                                 :                             CogDAC (Streamers/Cogs)
                                                 :          [%%%%%%%%%%%%%]<============================= cog0
                                                 :          [             ]<============================= cog1
                                                 :          [   DAC bus   ]<============================= cog2
                           [%%%%%%%%%%%%%]       :          [   select    ]<============================= cog3
                           [  Flash DAC  ]       :          [             ]<============================= cog4
                           [   Network   ]<==++=============[   (%P...P)  ]<============================= cog5
                    |<-----[             ]   ||  :          [             ]<============================= cog6
                    |      [   (%P...P)  ]   ||  :          [             ]<============================= cog7
                    |      [             ]   ||  :          [%%%%%%%%%%%%%]<===\\
                    |      [%%%%%%%%%%%%%]   ||  :               ^             ||
                    |                        ||  :               |   ------------------------------------- RND
                    |                        ||  :        BitDAC |  | Other    ||
                    |      [%%%%%%%%%%%%%]   ||  :               |  v          ||SmartDAC
                    |      [    Logic    ]   ||  :          [%%%%%%%%%%%%%]    ||
                    |      [    Drive    ]   ||  :   Enable [             ]<------------------------------ OUT
                    |      [             ]<-----------------[    Logic    ]    ||
    [%%%%%%%%]      |<-----[   (%P...P)  ]   ||  :   Output [    Output   ]<---------------------------+-- DIR
    [        ]      |      [             ]<----------+------[             ]    ||                      |
    [Physical]      |      [%%%%%%%%%%%%%]   ||  :   |      [    (%TT)    ]    ||    [%%%%%%%%%%%%]    |
    [ Even # ]------+            ^           ||  :   |      [  (%MMMMM_0) ]    \\====[            ]    |
    [ Pin Pad]      |            |           ||  :   |  OUT [             ]          [   Even #   ]<---
    [        ]      |       Feed |    CompDAC||  :   |   ---[             ]<---------[  Smartpin  ]
    [%%%%%%%%]      |       back |           ||  :   |  |   [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ]
                    |            |           ||  :   |  |                            [            ]
                    |      [%%%%%%%%%%%%%]   ||  :   |  |                            [  [X reg]===]<==== WXPIN
                    |      [  Comparator ]<==//  :   |  |     -1  -2  -3             [  [Y reg]===]<==== WYPIN
                    |      [             ]       :   |  |      |   |   |             [  [Z reg]===]====> RDPIN
                    | PinB [             ]       :   |  |      v   v   v             [            ]
                  -------->[  Pin Input  ]       :   |  |   [%%%%%%%%%%%%%]      A   [            ]
                 |  | PinA [   (%P...P)  ]       :   |   -->[ Logic Input ]--------->[---o----o---]-------> IN
                 |  +----->[             ]       :   |      [   (A_B_F)   ]      B   [  (M == 0)  ]
                 |  |      [             ]----------------->[             ]--------->[            ]
                 |  |      [ Sigma-Delta ]       :   |      [%%%%%%%%%%%%%]          [            ]
                 |  |      [     ADC     ]       :   |         ^   ^   ^             [%%%%%%%%%%%%]
                 |  |      [%%%%%%%%%%%%%]       :   |         |   |   |
                 |  |                            :   |        +1  +2  +3
                 |  |                            :   |
                 |  |                            :   |
                 |  |                            :   |                         CogDAC (Streamers/Cogs)
                 |  |                            :   |      [%%%%%%%%%%%%%]<============================= cog0
                 |  |                            :   |      [             ]<============================= cog1
                 |  |                            :   |      [   DAC bus   ]<============================= cog2
                 |  |      [%%%%%%%%%%%%%]       :   |      [   select    ]<============================= cog3
                 |  |      [  Flash DAC  ]       :   |      [             ]<============================= cog4
                 |  |      [   Network   ]<==++=============[   (%P...P)  ]<============================= cog5
                 |<--------[             ]   ||  :   |      [             ]<============================= cog6
                 |  |      [   (%P...P)  ]   ||  :   |      [             ]<============================= cog7
                 |  |      [             ]   ||  :   |      [%%%%%%%%%%%%%]<===\\
                 |  |      [%%%%%%%%%%%%%]   ||  :   |              ^          ||
                 |  |                        ||  :    -----------   |          ||
                 |  |                        ||  :         Other |  |BitDAC    || SmartDAC
                 |  |      [%%%%%%%%%%%%%]   ||  :               v  |          ||
                 |  |      [    Logic    ]   ||  :          [%%%%%%%%%%%%%]    ||
                 |  |      [    Drive    ]   ||  :   Enable [             ]<------------------------------ OUT
                 |  |      [             ]<-----------------[    Logic    ]    ||
    [%%%%%%%%]   |<--------[   (%P...P)  ]   ||  :   Output [    Output   ]<---------------------------+-- DIR
    [        ]   |  |      [             ]<-----------------[             ]    ||                      |
    [Physical]   |  |      [%%%%%%%%%%%%%]   ||  :          [    (%TT)    ]    ||    [%%%%%%%%%%%%]    |
    [ Odd #  ]---+  |            ^           ||  :          [  (%MMMMM_0) ]    \\====[            ]    |
    [ Pin Pad]   |  |            |           ||  :      OUT [             ]          [   Odd #    ]<---
    [        ]   |  |       Feed |    CompDAC||  :       ---[             ]<---------[  Smartpin  ]
    [%%%%%%%%]   |  |       back |           ||  :      |   [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ]
                 |  |            |           ||  :      |                            [            ]
                 |  |      [%%%%%%%%%%%%%]   ||  :      |                            [  [X reg]===]<==== WXPIN
                 |  |      [  Comparator ]<==//  :      |     -1  -2  -3             [  [Y reg]===]<==== WYPIN
                 |  |      [             ]       :      |      |   |   |             [  [Z reg]===]====> RDPIN
                 |  |      [             ]       :      |      v   v   v             [            ]
                 |  | PinB [  Pin Input  ]       :      |   [%%%%%%%%%%%%%]      A   [            ]
                 |   ----->[   (%P...P)  ]       :       -->[ Logic Input ]--------->[---o----o---]-------> IN
                 |    PinA [             ]       :          [   (A_B_F)   ]      B   [  (M == 0)  ]
                  -------->[             ]----------------->[             ]--------->[            ]
                           [ Sigma-Delta ]       :          [%%%%%%%%%%%%%]          [            ]
                           [     ADC     ]       :             ^   ^   ^             [%%%%%%%%%%%%]
                           [%%%%%%%%%%%%%]       :             |   |   |
                                                 :            +1  +2  +3
                                                 :
                .......................          :               ..........................
                : Custom I/O Pad Ring :          :               : Synthesised Core Logic :
                '''''''''''''''''''''''          :               ''''''''''''''''''''''''''
    

    EDIT: Updated with BitDAC
    EDIT2: Updated with BitADC ... and removed the inverter from Other (Should verify ...)
    EDIT3: Removed BitADC and updated CompDAC
    EDIT4: Indicate 8-bit width for DAC buses
    EDIT5: Added X, Y and Z registers to smartpin
  • Oh bother, I just noticed that "Other" and OUT also enables the ADC is some situations. That's definitely more than I had counted on.

  • Here is the low-level I/O pad schematic with detail about the pad driver. I think everything you need to know is in here.

    Note how the M[12:0] ("P[12:0]" bits) pins come in from the core, along with DIR ("DIR" bit), PI ("IN" bit) and PO ("OUT" bit). These signals connect to the smart pin logic in the core.

    For smart pin modes, TT=%01 drives DIR high, to keep the pin outputting.

    4237 x 3546 - 352K
  • evanh wrote: »
    Oh bother, I just noticed that "Other" and OUT also enables the ADC is some situations. That's definitely more than I had counted on.

    That's just kind of incidental to the design. Not really useful, but needed documenting.
  • cgracey wrote: »
    Here is the low-level I/O pad schematic with detail about the pad driver. I think everything you need to know is in here.
    Excellent! Thank you.
    You know I'll be back for more about the core logic. :D

  • cgracey wrote: »
    Note how the M[12:0] ("P[12:0]" bits) pins come in from the core, along with DIR ("DIR" bit), PI ("IN" bit) and PO ("OUT" bit). These signals connect to the smart pin logic in the core.
    Cool. Making sense already. Worked out PA is the physical pin pad. With PB being the odd/even pair.

  • evanh wrote: »
    cgracey wrote: »
    Note how the M[12:0] ("P[12:0]" bits) pins come in from the core, along with DIR ("DIR" bit), PI ("IN" bit) and PO ("OUT" bit). These signals connect to the smart pin logic in the core.
    Cool. Making sense already. Worked out PA is the physical pin pad. With PB being the odd/even pair.

    Correct.
  • evanhevanh Posts: 9,958
    edited 2020-04-14 - 00:38:11
    What's the meaning of all those P's and N's with 4-bit binary names? Do they actually match up symbolically?

    EDIT: I think I can answer: They are the nominal logic polarity, and yes they seem to symbolically connect to other places.
  • DAC drive looks to be Class A.
  • evanh wrote: »
    What's the meaning of all those P's and N's with 4-bit binary names? Do they actually match up symbolically?

    Those names describe the actual logic functions.
  • evanh wrote: »
    DAC drive looks to be Class A.

    It's a sum of 256 equivalent resistors with logic drivers.
  • evanhevanh Posts: 9,958
    edited 2020-04-14 - 00:58:14
    cgracey wrote: »
    It's a sum of 256 equivalent resistors with logic drivers.
    Hehe, I guess that's not the usual Class A structure but I think it still technically is. Namely, I'm looking at those two selectable resistors connected to PA beside the DAC. Selected by M8 and M9. Or are they just some bias?


  • evanh wrote: »
    cgracey wrote: »
    It's a sum of 256 equivalent resistors with logic drivers.
    Hehe, I guess that's not the usual Class A structure but I think it still technically is. Namely, I'm looking at those two selectable resistors connected to PA beside the DAC. Selected by M8 and M9. Or are they just some bias?


    Those two resistors are pull-downs which drop the DAC range to 2.0V, instead of the normal 3.3V, and decrease the impedance while doing so. Impedance in the DACs is always constant.
  • Doh, got that one wrong. So R1 will be for 600 ohms and R1 + R2 for 75 ohms?
  • evanhevanh Posts: 9,958
    edited 2020-04-14 - 01:43:21
    Oh, how slow is the "Slow DAC" in the comparator? I'd assumed there was an analogue link from the Fast DAC. EDIT: Does it latch on low on ENA?
Sign In or Register to comment.