I've got the latest version of the schematic editor, SPICE, and waveform viewer running. It actually works okay, though an intermediate version hadn't presented the schematic properly. So, I can make a proper diagram of the smart pin.
Yep. Looks right.
Are those Cog_DAC buses drawn thicker? They barely stand out. Making everything else thinner would help a lot. BTW, Smart_DAC and DAC_Mode are also 8-bit buses.
EDIT: Updated with BitDAC
EDIT2: Updated with BitADC ... and removed the inverter from Other (Should verify ...)
EDIT3: Removed BitADC and updated CompDAC
EDIT4: Indicate 8-bit width for DAC buses
EDIT5: Added X, Y and Z registers to smartpin
Here is the low-level I/O pad schematic with detail about the pad driver. I think everything you need to know is in here.
Note how the M[12:0] ("P[12:0]" bits) pins come in from the core, along with DIR ("DIR" bit), PI ("IN" bit) and PO ("OUT" bit). These signals connect to the smart pin logic in the core.
For smart pin modes, TT=%01 drives DIR high, to keep the pin outputting.
Note how the M[12:0] ("P[12:0]" bits) pins come in from the core, along with DIR ("DIR" bit), PI ("IN" bit) and PO ("OUT" bit). These signals connect to the smart pin logic in the core.
Cool. Making sense already. Worked out PA is the physical pin pad. With PB being the odd/even pair.
Note how the M[12:0] ("P[12:0]" bits) pins come in from the core, along with DIR ("DIR" bit), PI ("IN" bit) and PO ("OUT" bit). These signals connect to the smart pin logic in the core.
Cool. Making sense already. Worked out PA is the physical pin pad. With PB being the odd/even pair.
It's a sum of 256 equivalent resistors with logic drivers.
Hehe, I guess that's not the usual Class A structure but I think it still technically is. Namely, I'm looking at those two selectable resistors connected to PA beside the DAC. Selected by M8 and M9. Or are they just some bias?
It's a sum of 256 equivalent resistors with logic drivers.
Hehe, I guess that's not the usual Class A structure but I think it still technically is. Namely, I'm looking at those two selectable resistors connected to PA beside the DAC. Selected by M8 and M9. Or are they just some bias?
Those two resistors are pull-downs which drop the DAC range to 2.0V, instead of the normal 3.3V, and decrease the impedance while doing so. Impedance in the DACs is always constant.
Comments
I'll get you to update the drawing to match my fix for "Other" - https://forums.parallax.com/discussion/comment/1492991/#Comment_1492991
Are those Cog_DAC buses drawn thicker? They barely stand out. Making everything else thinner would help a lot. BTW, Smart_DAC and DAC_Mode are also 8-bit buses.
NOTE: Latest edition - https://forums.parallax.com/discussion/comment/1473762/#Comment_1473762
Here's my first attempt to split off the DAC section. It's not complete though, BITDAC mode doesn't fit.
....................... : .......................... : Custom I/O Pad Ring : : : Synthesised Core Logic : ''''''''''''''''''''''' : '''''''''''''''''''''''''' : : CogDAC (Streamers/Cogs) : [%%%%%%%%%%%%%]<============================= cog0 : [ ]<============================= cog1 : [ DAC bus ]<============================= cog2 [%%%%%%%%%%%%%] : [ select ]<============================= cog3 [ Flash DAC ] : [ ]<============================= cog4 [ Network ]<==++=============[ (%P...P) ]<============================= cog5 |<-----[ ] || : [ ]<============================= cog6 | [ (%P...P) ] || : [ ]<============================= cog7 | [ ] || : [%%%%%%%%%%%%%]<===\\ | [%%%%%%%%%%%%%] || : ^ || | || : | ------------------------------------- RND | || : BitDAC | | Other || | [%%%%%%%%%%%%%] || : | v ||SmartDAC | [ Logic ] || : [%%%%%%%%%%%%%] || | [ Drive ] || : Enable [ ]<------------------------------ OUT | [ ]<-----------------[ Logic ] || [%%%%%%%%] |<-----[ (%P...P) ] || : Output [ Output ]<---------------------------+-- DIR [ ] | [ ]<----------+------[ ] || | [Physical] | [%%%%%%%%%%%%%] || : | [ (%TT) ] || [%%%%%%%%%%%%] | [ Even # ]------+ ^ || : | [ (%MMMMM_0) ] \\====[ ] | [ Pin Pad] | | || : | OUT [ ] [ Even # ]<--- [ ] | Feed | CompDAC|| : | ---[ ]<---------[ Smartpin ] [%%%%%%%%] | back | || : | | [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ] | | || : | | [ ] | [%%%%%%%%%%%%%] || : | | [ [X reg]===]<==== WXPIN | [ Comparator ]<==// : | | -1 -2 -3 [ [Y reg]===]<==== WYPIN | [ ] : | | | | | [ [Z reg]===]====> RDPIN | PinB [ ] : | | v v v [ ] -------->[ Pin Input ] : | | [%%%%%%%%%%%%%] A [ ] | | PinA [ (%P...P) ] : | -->[ Logic Input ]--------->[---o----o---]-------> IN | +----->[ ] : | [ (A_B_F) ] B [ (M == 0) ] | | [ ]----------------->[ ]--------->[ ] | | [ Sigma-Delta ] : | [%%%%%%%%%%%%%] [ ] | | [ ADC ] : | ^ ^ ^ [%%%%%%%%%%%%] | | [%%%%%%%%%%%%%] : | | | | | | : | +1 +2 +3 | | : | | | : | | | : | CogDAC (Streamers/Cogs) | | : | [%%%%%%%%%%%%%]<============================= cog0 | | : | [ ]<============================= cog1 | | : | [ DAC bus ]<============================= cog2 | | [%%%%%%%%%%%%%] : | [ select ]<============================= cog3 | | [ Flash DAC ] : | [ ]<============================= cog4 | | [ Network ]<==++=============[ (%P...P) ]<============================= cog5 |<--------[ ] || : | [ ]<============================= cog6 | | [ (%P...P) ] || : | [ ]<============================= cog7 | | [ ] || : | [%%%%%%%%%%%%%]<===\\ | | [%%%%%%%%%%%%%] || : | ^ || | | || : ----------- | || | | || : Other | |BitDAC || SmartDAC | | [%%%%%%%%%%%%%] || : v | || | | [ Logic ] || : [%%%%%%%%%%%%%] || | | [ Drive ] || : Enable [ ]<------------------------------ OUT | | [ ]<-----------------[ Logic ] || [%%%%%%%%] |<--------[ (%P...P) ] || : Output [ Output ]<---------------------------+-- DIR [ ] | | [ ]<-----------------[ ] || | [Physical] | | [%%%%%%%%%%%%%] || : [ (%TT) ] || [%%%%%%%%%%%%] | [ Odd # ]---+ | ^ || : [ (%MMMMM_0) ] \\====[ ] | [ Pin Pad] | | | || : OUT [ ] [ Odd # ]<--- [ ] | | Feed | CompDAC|| : ---[ ]<---------[ Smartpin ] [%%%%%%%%] | | back | || : | [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ] | | | || : | [ ] | | [%%%%%%%%%%%%%] || : | [ [X reg]===]<==== WXPIN | | [ Comparator ]<==// : | -1 -2 -3 [ [Y reg]===]<==== WYPIN | | [ ] : | | | | [ [Z reg]===]====> RDPIN | | [ ] : | v v v [ ] | | PinB [ Pin Input ] : | [%%%%%%%%%%%%%] A [ ] | ----->[ (%P...P) ] : -->[ Logic Input ]--------->[---o----o---]-------> IN | PinA [ ] : [ (A_B_F) ] B [ (M == 0) ] -------->[ ]----------------->[ ]--------->[ ] [ Sigma-Delta ] : [%%%%%%%%%%%%%] [ ] [ ADC ] : ^ ^ ^ [%%%%%%%%%%%%] [%%%%%%%%%%%%%] : | | | : +1 +2 +3 : ....................... : .......................... : Custom I/O Pad Ring : : : Synthesised Core Logic : ''''''''''''''''''''''' : ''''''''''''''''''''''''''EDIT: Updated with BitDAC
EDIT2: Updated with BitADC ... and removed the inverter from Other (Should verify ...)
EDIT3: Removed BitADC and updated CompDAC
EDIT4: Indicate 8-bit width for DAC buses
EDIT5: Added X, Y and Z registers to smartpin
Note how the M[12:0] ("P[12:0]" bits) pins come in from the core, along with DIR ("DIR" bit), PI ("IN" bit) and PO ("OUT" bit). These signals connect to the smart pin logic in the core.
For smart pin modes, TT=%01 drives DIR high, to keep the pin outputting.
That's just kind of incidental to the design. Not really useful, but needed documenting.
You know I'll be back for more about the core logic.
Correct.
EDIT: I think I can answer: They are the nominal logic polarity, and yes they seem to symbolically connect to other places.
Those names describe the actual logic functions.
It's a sum of 256 equivalent resistors with logic drivers.
Those two resistors are pull-downs which drop the DAC range to 2.0V, instead of the normal 3.3V, and decrease the impedance while doing so. Impedance in the DACs is always constant.