Prop2 Analog Test Chip Arrived!

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  • cgraceycgracey Posts: 11,753
    edited 2016-11-09 - 18:53:11
    ErNa wrote: »
    ErNa wrote: »
    Chip, you definitely deserve better scope! Congrates!
    But I learned: You can't always get what you want. But if you try sometime you find: You get what you need
    So, to be more precise: you need a better scope. And I believe, the americans deserved a better scope!

    The new American scope is much more accurate and has better noise rejection, to avoid false triggering (in places like Syria). I'm thinking that design work will be much improved now. I'm glad we didn't wind up with a buggy revision of the prior scope that the sales rep was really pushing hard on us. He was dumb struck when we declined his offer.
  • cgraceycgracey Posts: 11,753
    edited 2016-11-09 - 19:28:55
    Good news about the fuses!!!

    I realized there is no problem, after all.

    Look at the bottom layer:

    Prop2_Test_v1_pcb_bottom.png

    You can see four 0603 resistor land patterns in the lower right. Those 470 ohm resistors were used to keep the four BLOW signals low. The were common-tied to GND on the right side of the board. The problem was that when I hooked up that board in isolation from the FPGA board, that right-side GND was floating, allowing those 470-ohm resistors to connect all the BLOW signals together. What a relief! I was thinking about this before I fell asleep when it dawned on me.

    I will desolder two test chips and solder two new ones onto two test boards and make doubly sure that the fuses work right, in isolation.
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  • jmgjmg Posts: 14,019
    cgracey wrote: »
    You can see four 0603 resistor land patterns in the lower right. Those 470 ohm resistors were used to keep the four BLOW signals low. The were common-tied to GND on the right side of the board. The problem was that when I hooked up that board in isolation from the FPGA board, that right-side GND was floating, allowing those 470-ohm resistors to connect all the BLOW signals together. What a relief! I was thinking about this before I fell asleep when it dawned on me.
    Good news indeed.
    cgracey wrote: »
    I will desolder two test chips and solder two new ones onto two test boards and make doubly sure that the fuses work right, in isolation.

    Surely PCBs are way cheaper than the time to do all that ? (plus those chips could still be used for many other tests, right ?)
    How many test boards did you get made ?
  • I might have gone with a simpler scope, but I gotta say I was really impressed early this a.m. when the new scope was first powered up. Looks to be user-friendly and surprisingly useful.
    Platåberget
  • jmg wrote: »
    cgracey wrote: »
    You can see four 0603 resistor land patterns in the lower right. Those 470 ohm resistors were used to keep the four BLOW signals low. The were common-tied to GND on the right side of the board. The problem was that when I hooked up that board in isolation from the FPGA board, that right-side GND was floating, allowing those 470-ohm resistors to connect all the BLOW signals together. What a relief! I was thinking about this before I fell asleep when it dawned on me.
    Good news indeed.
    cgracey wrote: »
    I will desolder two test chips and solder two new ones onto two test boards and make doubly sure that the fuses work right, in isolation.

    Surely PCBs are way cheaper than the time to do all that ? (plus those chips could still be used for many other tests, right ?)
    How many test boards did you get made ?

    We only have four test PCB's. I'll order more if people want them for their own Prop123-A9's.
  • cgraceycgracey Posts: 11,753
    edited 2016-11-09 - 19:51:15
    User Name wrote: »
    I might have gone with a simpler scope, but I gotta say I was really impressed early this a.m. when the new scope was first powered up. Looks to be user-friendly and surprisingly useful.

    Yes, better an American scope than a foreign-owned ringer with the stuxnet virus.
  • jmgjmg Posts: 14,019
    cgracey wrote: »
    We only have four test PCB's. I'll order more if people want them for their own Prop123-A9's.

    Sounds a good idea to expand the test coverage. So far, nothing seems broken, but some areas could be improved ?

    Getting some Video rasters out of the test chips, could help confirm DAC and Jitter (even if the update rates mean it is blocky)

    I did wonder about adding a P1 footprint, and a 74AUG1G80, to that PCB for the next batch, to make testing more compact ?

    Other possible footprints :
    Crystal XRCGB24M000F0L00R0 Murata 24.0000MHZ 6PF SMD
    VCTCXO TG2016SBN 16.0000M-MCGNEM3 16.0000MHz +/-.5ppm 2.8-3.3V -40C +85C 250 On Order

    The 4 pin 2.0 x 1.6mm package is the same for XRCGB & TG2016SBN, but needs Pin3 -> XI via CAP for TG2016SBN and some means to isolate Pin4 (Vcc on TG2016SBN, is package-shorted to Pin2 on XRCGB)

    That would be:
    Pin 1 - Series cap/jumper 0402 to XO
    Pin 2 - GND
    Pin 3 - Series cap 0402 to XI
    Pin 4 - Series R to 3v3, cap to GND.

  • Did you test the flash yet?
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  • Rayman wrote: »
    Did you test the flash yet?

    No. I will today.
  • The flash works!

    That was just a test board feature, though, and didn't have anything to do the test chip.
  • Thats a big relief about the fuses, Chip.

    Did you put current sources into that test chip? Were they 100uA?
  • jmgjmg Posts: 14,019
    Tubular wrote: »
    Did you put current sources into that test chip? Were they 100uA?

    Can the Test Chip do Cap-Sense type Touch buttons ?

    ie using a combination of Smart-Pin modes, and current-sources or ADC feedback loops ?

    eg for a 0.5ms reading time, and a 80MHz SysClk, you can resolve to one part in 40k, or 25ppm, or detect 1fF in 40pF

  • Tubular wrote: »
    Thats a big relief about the fuses, Chip.

    Did you put current sources into that test chip? Were they 100uA?

    I'll need to see, through a 10-ohm resistor, what the blow current is. I think it will be several to ten mA. Too bad SPICE models can't be used. We probably have 10x the current available over what is needed.
  • We only have four test PCB's. I'll order more if people want them for their own Prop123-A9's.

    Please do. No rush.
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
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  • jmg wrote: »
    Tubular wrote: »
    Did you put current sources into that test chip? Were they 100uA?

    Can the Test Chip do Cap-Sense type Touch buttons ?

    ie using a combination of Smart-Pin modes, and current-sources or ADC feedback loops ?

    eg for a 0.5ms reading time, and a 80MHz SysClk, you can resolve to one part in 40k, or 25ppm, or detect 1fF in 40pF

    Single-pin Schmitt relaxation oscillators can be made from bare smart pins. Their frequency is inversely proportional to capacitance. You'd use a resistive drive mode.
  • cgracey wrote: »
    active_probe_setup.jpg

    One of my go-to setups for high frequency work is to solder on a short twisted pair made using wire-wrap wire from the signal and PCB ground to the probe tip and probe ground. I can extend it out 1-3 inches and got fast clean signals. This assumes you can't directly touch the probe tip to the circuit, and touch a local ground with a little ground spring. Another option for high drive signals is to make a "Low-Z" probe with a 450ohm resistor feeding 50ohm coax terminated at the oscilloscope. As long as it's built small, a Low-Z probe has good signal quality up into the 1-2GHz range and minimal capacitance. (I've got a footprint with a W.FL coax connector and resistor so I can build permanent test points into the PCB as well)

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  • potatohead wrote: »
    We only have four test PCB's. I'll order more if people want them for their own Prop123-A9's.

    Please do. No rush.

    I just ordered 20 more PCB's. Should be here next week.
  • jmgjmg Posts: 14,019
    cgracey wrote: »
    jmg wrote: »
    Can the Test Chip do Cap-Sense type Touch buttons ?

    ie using a combination of Smart-Pin modes, and current-sources or ADC feedback loops ?

    eg for a 0.5ms reading time, and a 80MHz SysClk, you can resolve to one part in 40k, or 25ppm, or detect 1fF in 40pF

    Single-pin Schmitt relaxation oscillators can be made from bare smart pins. Their frequency is inversely proportional to capacitance. You'd use a resistive drive mode.

    Sounds good - can the test chip do the oscillator side of that ? I guess that gives a triangle waveform on the pin ?

    That leaves Freqency counting ? - I suppose a std Freq Counter, or a P1 with a ~1ms sample time could do a reciprocal counter to test the LSB ?

  • cgracey wrote: »
    Tubular wrote: »
    Thats a big relief about the fuses, Chip.

    Did you put current sources into that test chip? Were they 100uA?

    I'll need to see, through a 10-ohm resistor, what the blow current is. I think it will be several to ten mA. Too bad SPICE models can't be used. We probably have 10x the current available over what is needed.

    Yes but weren't there a couple of selectable current sources on the high and low side, selectable like the pullup/pulldown resistors? Or was that just in an old version?
  • Tubular wrote: »
    cgracey wrote: »
    Tubular wrote: »
    Thats a big relief about the fuses, Chip.

    Did you put current sources into that test chip? Were they 100uA?

    I'll need to see, through a 10-ohm resistor, what the blow current is. I think it will be several to ten mA. Too bad SPICE models can't be used. We probably have 10x the current available over what is needed.

    Yes but weren't there a couple of selectable current sources on the high and low side, selectable like the pullup/pulldown resistors? Or was that just in an old version?

    The I/O pins have selectable high and low drive types. If we are talking about the internal fuses though, they each have a big 3.3 volt PMOS switch.
  • jmgjmg Posts: 14,019
    cgracey wrote: »
    The I/O pins have selectable high and low drive types.

    How many steps of drive level - just 2 ?
    I think Tubular is talking about pin-drive current sources, with light-levels (100uA ?) suitable for Transistor base drive, and RC loads etc.


  • cgraceycgracey Posts: 11,753
    edited 2016-11-10 - 03:41:10
    jmg wrote: »
    cgracey wrote: »
    The I/O pins have selectable high and low drive types.

    How many steps of drive level - just 2 ?
    I think Tubular is talking about pin-drive current sources, with light-levels (100uA ?) suitable for Transistor base drive, and RC loads etc.


    I'll get some pictures up tonight. We have three resistive drive levels, three current levels, float, and normal digital drive, separately selectabe for high and low states.

    Then, there is a programmable DAC level for 1 and $00 level for 0. There are 4 impedance settings for DACs: 1k, 600, 120, and 75 ohms.
  • cgraceycgracey Posts: 11,753
    edited 2016-11-10 - 09:36:58
    I've been slowly sweeping the DAC in 16-bit mode and doing concurrent ADC (mode %00010). It seems that there is a solid 11-bit-quality result from the ADC. This is what I remember from simulations. It's amazing how accurate the SPICE simulations were. Anyway, I've even oversampled 256x and then divided by 256 and I only get another ~2 bits of resolution. Down the road, I want to discover what I can do to improve this, but I think it's quite sufficient for the 1st chip. I'm pretty pleased with the ADC and the DACs. I've output NTSC over a single-pin DAC and it works perfectly. So far, I've probably tested 80% of the pin and everything is exactly as expected. I don't see any problems. I'd like to get this testing done in one more big push and call it done.

    So, to date, I don't see any problem with any part of the test chip. It's all looking A-okay.

    I was going to put up some pictures tonight, but my smart phone that I use to take them is out of juice.
  • Happy days! Well done Chip! :) :cool:
    Melbourne, Australia
  • Excellent news Chip!
    Time to get the compiler/tools/etc. going/done.
  • Is it possible to create a special Verilog image that makes the two test pins act real to code?

    It might be interesting if they could be made to act to assembly code as if they were internally connected. I guess this means taking control of most of the I/O pins...
    Prop Info and Apps: http://www.rayslogic.com/
  • jmgjmg Posts: 14,019
    cgracey wrote: »
    I've been slowly sweeping the DAC in 16-bit mode and doing concurrent ADC (mode %00010). It seems that there is a solid 11-bit-quality result from the ADC. This is what I remember from simulations. It's amazing how accurate the SPICE simulations were. Anyway, I've even oversampled 256x and then divided by 256 and I only get another ~2 bits of resolution. Down the road, I want to discover what I can do to improve this, but I think it's quite sufficient for the 1st chip.

    11b maps to ~ 1.5mV of threshold noise floor, which will also vary with what else the digital sections are doing.
    The simplest CMOS inverter ADC modes have very poor PSRR, so I'd expect to need a shift to 2-pin modes to push the resolution up.

    There are isolated SDM ADCs with either ClkOut + DataOut, or ClkIn + DataOut, and I've seen high precision ADCs made using discrete FF, VRef, and opamp integration.
    That circuit block results in ClkIn + DataOut

    A variant on this might pull the FF into the P2, and use an external analog switch for VRef, but the package count is the same, and the external FF makes for fully digital interface signals, so gives a common design base.

    Another solution point to keep in mind, is small MCUs with better ADCs.
    The EFM8LB1 comes ~89c for 14b ADC and ~95c for 14b ADC and 12b DAC (ie less than you can find a 14b ADC for )
  • cgraceycgracey Posts: 11,753
    edited 2016-11-11 - 11:03:39
    Today I tested the internal 8-bit R-2R DAC which is used with the comparator for level sensing. R-2R DACs are very susceptible to resistor mismatch, causing non-monotonic steps, or ascending values periodically resulting in negative voltage steps, instead of positive ones. The weakest point of an R-2R is the step at the half-way point. In the case of an 8-bit R-2R DAC, that is $7F transitioning to $80, as all of the input bits change states. That's where you are going to have the greatest error in step size across the DAC's whole range.

    In our R-2R DAC, R=146k ohms. So, 2R=292k ohms. These resistors must match closely and the 2R drivers' impedance must be low enough to not contribute to any prominent amount of error, themselves.

    Here's our schematic. Note the single unitized resistor size and the common-centroid layout which ensures good matching under process and temperature gradients:

    DAC_R_2R.png

    Here's the driver (DRV symbol) detail:

    DAC_R_2R_DRIVER.png

    Here's a 3D rendering of the layout:

    THICK_DAC_SLOW.png

    And here's the best part. This is a slow triangle sweep of DAC input values $7C..$83:

    CMP_DAC8.jpg

    That mid-point step is well in bounds. You can see the adjacent step sizes are greater, but we're not suffering the disaster of having a negative step from $7F to $80, which would be the first place one would show up. We have a monotonic R-2R DAC!

    I wasn't sure how I was going to test the internal R-2R DAC, but then I remembered that we have a mode where the pin can output the opposite of the internal DAC comparison state through a 1.5k resistor. By putting a 0.1uF cap to GND on the pin to act as a filter, and slowly stepping the comparison DAC value, this negative feedback mode will cause the pin voltage to center on the internal DAC voltage. Then, we can just look at the scope to see the internal DAC voltage.

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  • cgraceycgracey Posts: 11,753
    edited 2016-11-11 - 08:14:37
    .
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  • cgraceycgracey Posts: 11,753
    edited 2016-11-11 - 08:28:56
    Here are the pin modes, mentioned as %PPPPPPPPPPPPP in the Google Doc:

    Pin_Modes.png

    To do the R-2R DAC testing, I set the pin mode to %1101_0xxxxxxxx, where xxxxxxxx was the DAC level.

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