Prop2 Analog Test Chip Arrived!

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Comments

  • Love the progress!!!
  • jmg wrote: »
    cgracey wrote: »
    The VCO runs at 1.8V and the power is filtered on the die. The PLL looks looks very jittery in some cases, and not others. I don't understand what the issue is, yet.

    Do you have access to the VCO voltage control node, to sweep it externally ?
    Maybe also add a series R to the OscOutput, to reduce the ringing currents, and so reduce Vcc ripple.
    cgracey wrote: »
    I'm using the ADC to digitize an incoming analog signal from my function generator and then those samples are going to the other analog pin in DAC mode.
    Can you add notes to those around what the expected DAC resolution is for each, and what DAC mode is being tested.
    DAC results seem to be always coarse ?
    (IIRC DAC has Fast and slower modes ?)

    Have you tested the DAC(s) using a slow triangle digital sweep ?

    I don't have access to the VCO control voltage node. The thing was designed for 20MHz crystals. I need to get ahold of one and try it. I only have 5.00MHz and 6.25MHz on hand.

    About the DAC, here are some pictures of the slow triangle sweep, including top and bottom. I used scope averaging to get rid of system noise:


    DAC_tri_full.jpgDAC_tri_top.jpgDAC_tri_bot.jpg
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  • Tubular wrote: »
    Nice going, Chip!

    The sine wave input appears to dip down below zero - is that to deliberately test slightly beyond the rails? If so looks like its working well. Being able to pick up that 20mv 20khz signal in a 100x mode is really quite impressive

    Not sure whether the dithering is working quite right though, unless its some CRO artefact

    Yes, it can digitize beyond the rails, since GIO = ~1/8th duty and VIO = ~7/8th duty. The limiters are the duty range 0..1 and the clamping diodes on the I/O pins, which start conducting around 400mV.
  • jmg wrote: »
    Rayman wrote: »
    Glad to hear it's working.
    A lot of other chip's I've seen need external capacitors and sometimes a resistor around the crystal. Maybe this one does too?
    I'm not sure Chip is testing the Crystal Analog side yet ?
    Common is to have a bias resistor internally, which needs to be quite high if targeting 32kHz modes.
    The P1 has a choice a few CAP values, maybe P2 is the same ?
    (but with lower Caps, to match the higher targeted crystals)

    Another detail worth checking on the Xtal Amplifier, is the AC coupled Sine Amplitude threshold (will vary a little with MHz)
    The Clipped Sine Oscillator modules usually spec > 0.8V p-p into 10K//10pF, with a source impedance < 470 Ohms

    Here is a picture of the crystal oscillator running with internal 15pF loading caps and a 5MHz crystal. The top trace is XO (crystal oscillator output from the Prop2) and the bottom is XI (crystal/clock input to the Prop2). These signals connect directly to the legs of the crystal. The crystal is the only external component. I connected the scope right to the crystal's legs, which added an additional 5pF of loading. It looks to me that the sine wave coming out of the crystal (bottom trace) is quite healthy. You can see the drive (top trace) is less sinusoidal, as it's actively driving. I realized a while back that the best way to drive a crystal is with a single-stage inverter. That keeps the gain in check and inhibits harmonic overdrive.

    xtal_5MHz.jpg
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  • cgraceycgracey Posts: 13,079
    edited 2016-11-08 - 11:34:42
    jmg wrote: »
    Cool, so that is showing us a 256b DAC, being fed LSB steps, at ~ 10us rate, and seems to be rail-rail, with reasonable DNL.
    One detail that puzzles a little, is the steps do not quite line up, increment and decrement - is that a scope/measurement artifact, or in the test chip itself ?

    I was noticing that, too. I don't know what's causing it. I'm wondering if maybe self-heating of the internal DAC resistors could be the issue. The DAC is made up of 64 unit resistors that are turned on in groups of 4 (16 groups), plus a group of 2, a single, two in series, and four in series. They are all interleaved and common-centroid in the layout to keep them process-matched and temperature-matched. I can run that test again, much faster, and see if the difference gets smaller.

    ...Okay. I just tried it again with a 1us step rate. Same thing going on. Not sure why.

    ...Even at a 250ns step rate, it does the same thing. Hmmmm...
  • Was just looking at Digikey and appears that 8 pF and 18 pF are the closest popular options for 20 MHz crystal. Doesn't have to be exact, right? Does ESR matter?
  • jmgjmg Posts: 14,495
    cgracey wrote: »
    jmg wrote: »
    Have you tested the DAC(s) using a slow triangle digital sweep ?
    About the DAC, here are some pictures of the slow triangle sweep, including top and bottom. I used scope averaging to get rid of system noise:

    Cool, so that is showing us a 256b DAC, being fed LSB steps, at ~ 10us rate, and seems to be rail-rail, with reasonable DNL.
    One detail that puzzles a little, is the steps do not quite line up, increment and decrement - is that a scope/measurement artifact, or in the test chip itself ?

    cgracey wrote: »
    I don't have access to the VCO control voltage node. The thing was designed for 20MHz crystals. I need to get ahold of one and try it. I only have 5.00MHz and 6.25MHz on hand.
    If you do not have crystals, you could test with an RF signal generator, AC coupled, and with a local termination pad like 50 ohms//220pF
    Or, there is the highly flexible Si5351A (Adafruit have a sub $10 PCB) but that needs an i2c config load step.
    cgracey wrote: »
    Here is a picture of the crystal oscillator running with internal 15pF loading caps and a 5MHz crystal. The top trace is XO (crystal oscillator output from the Prop2) and the bottom is XI (crystal/clock input to the Prop2). These signals connect directly to the legs of the crystal. The crystal is the only external component. I connected the scope right to the crystal's legs, which added an additional 5pF of loading. It looks to me that the sine wave coming out of the crystal (bottom trace) is quite healthy. You can see the drive (top trace) is less sinusoidal, as it's actively driving.
    Good to see life there, but 20MHz+ would be even better to see.

    Do you have a target hysteresis value for the internal post-osc Buffer stage ?

    A good crystal series to qualify would be this new range from Murata

    XRCGB24M000F0L00R0 Murata 24.0000MHZ 6PF SMD Stk 11,398 $0.13605/3000 24MHz ±50ppm ±100ppm 6pF 150 Ohm Fundamental -30°C ~ 85°C 4-SMD, 2.00mm x 1.60mm

    XRCGB32M000F2P10R0 Murata 32.0000MHZ $0.20412/1000 32MHz ±20ppm ±20ppm 6pF 70 Ohm Fundamental -30°C ~ 85°C
    4-SMD, No Lead (DFN, LCC) 2.00mm x 1.60mm

    These are small and low cost, but a side effect of the modern drive to small is the lowest MHz is bumped to 24MHz and the Series R is a largish 150 ohms. They also have a low 6pF target load C.
    The XRCGB does 24MHz thru 48MHz (13 values) , but your crystal oscillator may not reach to 48MHz.
    Most are 6pF, but I see they have one 27MHz variant spec'd for 12pF.

    Compare that with a more ancient
    ABLS-24.000MHZ-D2-T Abracon 24.0000MHZ 18PF SMD HC49/US $0.12300/3000 24MHz ±50ppm ±20ppm 18pF 40 Ohm Fundamental -40°C ~ 85°C Surface Mount HC49/US 11.40mm x 4.70mm x 4.20mm
    cgracey wrote: »
    I realized a while back that the best way to drive a crystal is with a single-stage inverter. That keeps the gain in check and inhibits harmonic overdrive.
    Yes, the 'unbuffered inverter' is the most predictable, tho there is a trend away from the older 74HCU04 style buffer, to using a N-MOSFET with a P-Fet current source. Still a linear Class-A amplifier, but this has lower swings, and is more immune to supply variations.
    You do need to derive a current-source, but once that is done, you can more easily vary the current level, to cover a wider useful range.

    Not all vendors manage this in a painless way - Atmel have moved to the newer Oscillator in some AVR, but managed to break 20MHz operation and now limit those parts to <= 16MHz Crystals.
  • OzPropDev posted some P8x32A code for the Si5351 at an frequency, if that's useful
  • I read recently of a mems process oscillator that looks like it will replace xtals. Don't really know if this is real or marketing hype.

    Anyway I love the 1.6x2.0mm SMT xtals. So small compared to HC49U/S.
  • jmgjmg Posts: 14,495
    Cluso99 wrote: »
    I read recently of a mems process oscillator that looks like it will replace xtals. Don't really know if this is real or marketing hype.

    MEMS have been around a while, and certainly have made some impact, but they struggle to meet the specs, as the Crystal vendors bring out new products.

    This recent MEMS is in SOT23-5,
    SIT9201AC-S3-25E-24.000000G SiTIME OSC MEMS 24.000MHZ H/LV-CMOS 0.55100 @ 3000
    HCMOS, LVCMOS 2.5V ±50ppm -20°C ~ 70°C 4.5mA
    Surface Mount 0.114" L x 0.110" W (2.90mm x 2.80mm) 0.057" (1.45mm) SC-74A, SOT-753

    and this one needs 16mA
    ASDMB-24.000MHZ-LC-T Abracon LLC OSC MEMS 24.000MHZ CMOS SMD 0.63800 @ 3000
    LVCMOS 1.8 V ~ 3.3 V ±50ppm -40°C ~ 85°C 16mA 2.50mm x 2.00mm

    and looking at the newest TCXO from Epson...

    TG2016SBN 25.0000M-TCGNNA3 EPSON OSC TCXO 25.0000MHZ $0.62350 @ 3000 Sine Wave 1.8 V ~ 3.3 V ±500ppb -40°C ~ 85°C 1.4mA 2.00mm x 1.60mm

    TG2016SBN 26.0000M-TCGNBM3 EPSON OSC VCTCXO 26.0000MHZ $0.62350
    @ 3000 Sine Wave 1.8 V ~ 3.3 V ±500ppb -40°C ~ 85°C 1.4mA
    2.00mm x 1.60mm ( same price for VCTCXO )

    Note the Lower Icc, much better PPM and smaller package.

    This is why I am encouraging MCU vendors to qualify their MCU Xtal amplifiers with these new clipped sine offerings.

  • Chip,

    As far as the dithering that has been hinted about and the strange 60/40 duty cycle issue, double check the size of the fringe "dummy fingers" on the resistors as well as any capacitors and transistors. The 60/40 duty cycle could also be caused by the drive differences between Nmos and Pmos transistors, but I'm willing to bet that fringe effects are to blame here more than drive strength characteristics. To really dial that in you need empirical testing where the components are scaled by factors of 2. When I was at NSC a test chip was always made with the kind of empirical testing I describe... even at NSC we wouldn't completely rely on the spice simulation models to predict the outcome. The TSMC processes that were used ranged from 360nm to 45nm, and every single one of the designs had a test chip of this nature prior to the production chip. ... Just double check the layout, not only for East and West, but North and South structure characteristics.
  • cgraceycgracey Posts: 13,079
    edited 2016-11-08 - 02:48:43
    Chip,

    As far as the dithering that has been hinted about and the strange 60/40 duty cycle issue, double check the size of the fringe "dummy fingers" on the resistors as well as any capacitors and transistors. The 60/40 duty cycle could also be caused by the drive differences between Nmos and Pmos transistors, but I'm willing to bet that fringe effects are to blame here more than drive strength characteristics. To really dial that in you need empirical testing where the components are scaled by factors of 2. When I was at NSC a test chip was always made with the kind of empirical testing I describe... even at NSC we wouldn't completely rely on the spice simulation models to predict the outcome. The TSMC processes that were used ranged from 360nm to 45nm, and every single one of the designs had a test chip of this nature prior to the production chip. ... Just double check the layout, not only for East and West, but North and South structure characteristics.

    This is nutty, but I think all those PLL problems I was having were due to connecting to the wrong pin on the test board. I was seeing things through capacitive coupling, but didn't realize it (as I probably had the scope gained turned up high). Today, I've been using the correct pin and it's a much better picture.

    The PLL is working much better now and I'm not seeing that duty skew, anymore. Some of my problems still have to do with my active probe hookup for the 1.5GHz Infiniium scope. My measurements have all kinds of distortions due to ringing. Maybe someone knows how to hook up a 2.5GHz active probe properly. At ~200MHz just two inches of wire makes a mess of things. I've tried various termination resistors at the probe, but no silver bullet found. Maybe I need one at the test chip pin, too.

    Anyway, I'm feeding 20MHz into XI from the FPGA and the PLL is multiplying it 8x to 160MHz, which is the design target frequency. Here is a colored histogram at 1ms out from trigger. The waveform looks distorted, but we can see that the cumulative jitter is not bad:

    PLL_160MHz.jpg
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  • jmgjmg Posts: 14,495
    cgracey wrote: »
    Anyway, I'm feeding 20MHz into XI from the FPGA and the PLL is multiplying it 8x to 160MHz, which is the design target frequency. Here is a colored histogram at 1ms out from trigger. The waveform looks distorted, but we can see that the cumulative jitter is not bad:

    How does that compare with a P1 PLL operating at a binary multiple ?
    What about 20,00MHz measured under the same conditions ?
    It's not easy here to separate Scope and sampling effects from real jitter.

    What is the lowest XI MHz you can set, and still get to 160MHz ?

  • The PLL has a 4-bit control field:

    0000 = off
    0001 = 2x
    0010 = 3x
    0011 = 4x
    0100 = 5x
    ...
    1101 = 14x
    1110 = 15x
    1111 = 16x


    So, 10MHz is the lowest XI frequency that will get you to 160MHz.
  • jmgjmg Posts: 14,495
    cgracey wrote: »
    The PLL has a 4-bit control field:

    0000 = off
    0001 = 2x
    0010 = 3x
    0011 = 4x
    0100 = 5x
    ...
    1101 = 14x
    1110 = 15x
    1111 = 16x


    So, 10MHz is the lowest XI frequency that will get you to 160MHz.

    Now you have the right connections, how does that jitter plot vary, as the PLL control field is varies, and when does the VCO/PLL hit the stops ?
  • cgraceycgracey Posts: 13,079
    edited 2016-11-08 - 07:29:44
    jmg wrote: »
    cgracey wrote: »
    The PLL has a 4-bit control field:

    0000 = off
    0001 = 2x
    0010 = 3x
    0011 = 4x
    0100 = 5x
    ...
    1101 = 14x
    1110 = 15x
    1111 = 16x


    So, 10MHz is the lowest XI frequency that will get you to 160MHz.

    Now you have the right connections, how does that jitter plot vary, as the PLL control field is varies, and when does the VCO/PLL hit the stops ?

    The jitter seems to be about the same, though it tightens up slightly at high speed. It's within +/-1ns. The VCO tops out at 360MHz, which is plenty above the needed 160MHz.

    Here's a nicer of picture of it going 200MHz at 2ms out from trigger:

    PLL_200MHz.jpg

    I've tried all kinds of terminator arrangements to reduce distortion on the signal and this works the best. It's a wire connected to the GND of the probe that wraps around the tip of the probe. There is no direct GND connection to the Prop2 setup! This just adds some capacitance between the active scope probe tip and its own GND. The tip, otherwise, has only 0.6pF of intrinsic capacitance. I believe it just goes to the gate of a FET whose source drives a 50-ohm transmission line that is the probe cable. The probe gets quite warm.

    active_probe_setup.jpg
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  • cgraceycgracey Posts: 13,079
    edited 2016-11-08 - 11:07:51
    I think the PLL is fine. It looks like it will run optimally with 16MHz crystals.

    I was having some strange behavior at extremes of low input frequency and high multiplier, as well as at high input frequency and low multiplier. I looked at the schematic and remembered that to cover a 2x..16x range, I had put in a two-speed bias drive. When you go from 2x..4x (low range) to 5x..16x (high range), the drive current into the bias cap becomes over 4x higher. Something like this was needed to help stabilize the PLL at high VCO frequencies, while at low VCO frequencies, weaker feedback is needed to keep the PLL locked.

    I found that at below 4MHz input, when going into high range, things got erratic, as the VCO correction current was too aggressive, since the feedback pulses were long.

    At over 32MHz input, when going into low range, the VCO correction current was too weak, since the correction pulses were so short.

    Probably something like 12MHz would be most conservative, but I think we can use 16MHz. A PLL parameter of %1001 would multiply that by 10 to get 160MHz.

    Here is the top-level schematic of the VCO. You can see the 'FAST' signal in the bias drive circuit enabling that smaller resistor ('ns' = number of unit resistors in series). Those resistors determine how much current is available in the bias charge pump. That current gets digitally switched to the Pbias cap via those UP and DN switches. The Pbias gets made into a complementary Nbias through the dummy differential inverter and the amplifier made from M7..M11. The biases are used to set the speed of the four differential inverters which are looped to form an oscillator. The higher the biases, the faster it goes. At very low voltages, it's extremely sensitive to change; hence, the low and high ranges for the bias drive.

    VCO_sch.png
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  • Very nice progress Chip, Congrats! :)
  • RaymanRayman Posts: 11,364
    edited 2016-11-08 - 11:51:19
    Very glad to hear the PLL is working.

    That is a very strange probe connection though.
    I think you have to have the ground lead connected to the board to get a good signal.

    Maybe there's a problem with XI and XO being so far apart and having a lot of traces between them.
    Usually XI and XO are right next to each other and you don't want any other traces near them...

  • cgraceycgracey Posts: 13,079
    edited 2016-11-08 - 12:21:10
    Rayman wrote: »
    Very glad to hear the PLL is working.

    That is a very strange probe connection though.
    I think you have to have the ground lead connected to the board to get a good signal.

    Maybe there's a problem with XI and XO being so far apart and having a lot of traces between them.
    Usually XI and XO are right next to each other and you don't want any other traces near them...

    This fast scope has always been like that. It's good for seeing accurate timing, useless for accurate voltages. I'd describe it as rather "swishy", like a watery lens that is always metamorphosing. My older scope is much better for precision work.
  • cgraceycgracey Posts: 13,079
    edited 2016-11-08 - 12:12:30
    ozpropdev wrote: »
    Very nice progress Chip, Congrats! :)

    Thanks. I'll get back on that assembler problem soon.
  • ErNaErNa Posts: 1,444
    edited 2016-11-08 - 15:50:30
    active_probe_setup.jpg
    It think, there should be a very short connection off gnd between probe and board. Here you have inductively coupled the signal to ground and you never know, how the other components are forming a filter network.
  • jmgjmg Posts: 14,495
    edited 2016-11-08 - 19:49:22
    cgracey wrote: »
    I think the PLL is fine. It looks like it will run optimally with 16MHz crystals.

    Just how narrow is the 'optimal' band ?
    There are multiple issues at work - the PFD likes to operate above some minimum speed, which imposes one limit.
    Next, it sounds like you have a Step-gear change 2x..4x (low range) to 5x..16x (high range)
    (<= 4x is only needed for >= 40MHz -> 160MHz ?)
    Then, lowest VCO Fosc has the most sensitivity to Bias ripple.

    Can you do a table of suggested VCO limits, and PFD limits, for each band (low range/high range) ?


    16MHz misses those small, low cost crystals I linked above, which come only > 24MHz.
    ( you can get 1.6 x 2mm 16MHz, but at higher prices )

    Another choice, that comes down to 12MHz, is the cute shrink-package CSM-3X series.
    ECS-160-20-3X-TR ECS Inc. CRYSTAL 16.0000MHZ 20PF SMD Stk 39,000 $0.17250 @ 3000


    VCTCXO's also tend to start ~ 19.2MHz for stocking volumes, but I do see the new Epson series does come down to 16MHz.
    TG2016SBN 16.0000M-TCGNBM3 EPSON OSC VCTCXO 16.0000MHZ SNWV $0.62350 @ 3000 SPQ 250

    Note that 16MHz is somewhat uncommon, and I see Future have part codes for only the mainstream TCXO targets of 19.2MHz, 26MHz, 38.4MHz

    Mouser do show one 16MHz & 19.2MHz variant on order
    TG2016SBN 16.0000M-MCGNEM3 Epson Timing VCXO Oscillators 16.0000MHz +/-.5ppm 2.8-3.3V -40C +85C 250 On Order

    No idea how/why they missed the same price, wider Vcc spec model ? (Maybe a recent addition?)
    TG2016SBN 16.0000M-TCGNBM3 VCXO Oscillators 16.0000MHz +/-.5ppm 1.8-3.3V -40C +85C

    cgracey wrote: »
    I was having some strange behavior at extremes of low input frequency and high multiplier, as well as at high input frequency and low multiplier. I looked at the schematic and remembered that to cover a 2x..16x range, I had put in a two-speed bias drive. When you go from 2x..4x (low range) to 5x..16x (high range), the drive current into the bias cap becomes over 4x higher. Something like this was needed to help stabilize the PLL at high VCO frequencies, while at low VCO frequencies, weaker feedback is needed to keep the PLL locked.

    I found that at below 4MHz input, when going into high range, things got erratic, as the VCO correction current was too aggressive, since the feedback pulses were long.

    At over 32MHz input, when going into low range, the VCO correction current was too weak, since the correction pulses were so short.
    hmmm... Starting to sound like some gaps and caveats...

    These sorts of issues are why vendors commonly offer more digital choices(Xi/M=VCO/N), to cover a wider range of XI-MHz and still give control of PFD-MHz. Some also add fSys = VCO/K, to avoid pushing the VCO to extremes.

    cgracey wrote: »
    I found that at below 4MHz input, when going into high range, things got erratic, as the VCO correction current was too aggressive, since the feedback pulses were long.
    Did I read that right ? - do you mean 4MHz and low range was ok ? that infers a VCO under 16MHz, which is quite some sweep range ?

  • jmgjmg Posts: 14,495
    cgracey wrote: »
    The jitter seems to be about the same, though it tightens up slightly at high speed. It's within +/-1ns. The VCO tops out at 360MHz, which is plenty above the needed 160MHz.
    Hehe, I can see some overclocking being done in the future...
    cgracey wrote: »
    Here's a nicer of picture of it going 200MHz at 2ms out from trigger:
    Can you get two traces on the scope that zoomed mode, to show both the Xin and fVCO ?

    Another idea for jitter testing / verification, would be to run one of these Test Chips into a 74AUP1G80, (SOT23 /2) and then drive a P1 running VGA code, from the P2 VCO (now /2 to 80MHz)

    That would allow a direct comparison with known operation on P1.
  • The fuse(s?) seem to work, but there is a strange problem. I blew one and they all blew. I'm going to look at the test chip layout to see if somehow some wires got shorted. This shouldn't be able to happen, but I can't think of any other reason why it would. That 3D viewer program has a feature where you can click on a piece of metal and the whole net gets highlighted.
  • jmgjmg Posts: 14,495
    cgracey wrote: »
    The fuse(s?) seem to work, but there is a strange problem. I blew one and they all blew. I'm going to look at the test chip layout to see if somehow some wires got shorted. This shouldn't be able to happen, but I can't think of any other reason why it would. That 3D viewer program has a feature where you can click on a piece of metal and the whole net gets highlighted.
    Is that even possible ?
    Do these blow-short or blow-open ? - what current profile is used during blow ?
    Failing a layout short, another mechanism could be over-voltage-fusing, from current flyback ?

  • Good thing you have more chips!
  • Rayman wrote: »
    Good thing you have more chips!

    Yes, but now we need more PCB's.
  • jmg wrote: »
    cgracey wrote: »
    The fuse(s?) seem to work, but there is a strange problem. I blew one and they all blew. I'm going to look at the test chip layout to see if somehow some wires got shorted. This shouldn't be able to happen, but I can't think of any other reason why it would. That 3D viewer program has a feature where you can click on a piece of metal and the whole net gets highlighted.
    Is that even possible ?
    Do these blow-short or blow-open ? - what current profile is used during blow ?
    Failing a layout short, another mechanism could be over-voltage-fusing, from current flyback ?

    They blow open. I will put a schematic up in a little while.
  • ErNa wrote: »
    Chip, you definitely deserve better scope! Congrates!
    But I learned: You can't always get what you want. But if you try sometime you find: You get what you need
    So, to be more precise: you need a better scope. And I believe, the americans deserved a better scope!

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