We got the test chip boards built today.
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Here's the 20MHz internal RC oscillator (mode $00):
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Here's the 20KHZ internal RC oscillator (mode $01):
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These were designed so that fixed capacitors and resistors dominate the RC period. They both have low temperature coefficients. You can see how close they are in frequency to the design goal.
Cool, a pulse !! - nice and close to targets too..
How does this vary with temperature & time & Vcc ? - ie the Can of freeze and a soldering iron quick test -> > 70'C ?
Can you leave one running, and log the frequency over a few days - normally, you get a lazy temperature tracking drifts.
However you ended up soldering such a fine pitch, you rocked it.
At Parallax there are big magnifiers and fine-tipped soldering irons that make it really easy. Water soluble flux in needle bottles helps, too. With those kinds of tools, you could solder even much smaller things. It's amazing what's possible with good tools. Tyrell and I soldered those. He did most of the work, just because he's so much faster, doing those things every day.
By the way, I went to sleep last night because I was too tired, after all the driving. So, I'm back to work now.
I was trying to work out the headers, I'm guessing you have some kind of long male headers that both let you plug into a P123-A9 and probe the signal at top as well?
I was trying to work out the headers, I'm guessing you have some kind of long male headers that both let you plug into a P123-A9 and probe the signal at top as well?
That's right. It's a header with long pins out the top and bottom. It solders from the underside.
Here's the RESn pin responding to pulses. It was designed to ignore 100ns or smaller pulses and trigger on 200ns or larger pulses. You can see the trip point is at ~150ns:
So far, everything is checking out, though the PLL seems a little over-reactive. I'll need to simulate that some more and try to figure out what's wrong. It's certainly something in the loop filter, which is just a resistor and a cap. There's a strange 60/40 duty cycle issue, as well. Perhaps the layout is not friendly to the intended circuit.
The analog pins seem to work perfectly, so far. I've tried out the DAC modes and they all work great. I need to do some ADC testing, as well.
So far, everything is checking out, though the PLL seems a little over-reactive. I'll need to simulate that some more and try to figure out what's wrong. It's certainly something in the loop filter, which is just a resistor and a cap. There's a strange 60/40 duty cycle issue, as well. Perhaps the layout is not friendly to the intended circuit.
The analog pins seem to work perfectly, so far. I've tried out the DAC modes and they all work great. I need to do some ADC testing, as well.
Sounds like great progress
What is the PFD range, on this PLL design ?
What exactly does "a little over-reactive" mean ?
Is it over-reactive on a NCO generated signal, vs a clean signal (crystal oscillator, or NCO binary setting) ?
As I've mentioned before, it's common for PLLs to run a VCO at 2x the required output, and use a local fast /2 to give exactly 50% outputs.
That's usually hidden in the docs a little, as that /2 is fixed and invisible to the equations.
If you do need to re-spin the PLL/PFD, I'd suggest extending the /M/N ranges ( & Xtal amplifier spec) to support the VCTCXOs (Clipped Sine).
I see these continue to fall in price, NEW at Digikey is this family.. common values are 19.2/26/27MHz etc
So far, everything is checking out, though the PLL seems a little over-reactive.
I wonder how sensitive this is to Vcc decoupling & Vcc ?
Can you easily vary Vcc over a range ? Is the PLL Vcc locally generated ?
The VCO runs at 1.8V and the power is filtered on the die. The PLL looks looks very jittery in some cases, and not others. I don't understand what the issue is, yet.
I've been testing the pin ADC and it seems to be working quite well. I'm using the ADC to digitize an incoming analog signal from my function generator and then those samples are going to the other analog pin in DAC mode. In the pictures, the top signal is the function generator and the bottom signal is the ADC sample going out the DAC in the adjacent pin.
Here is an analog-to-digital-to-analog conversion at 4 bits (16 clocks) per sample (5 MSPS):
Here is 8 bits (256 clocks, 312.5kSPS):
And here is 12 bits (4,096 clocks, 39kSPS), which the scope can't do justice to:
Here are the programs:
' 4-bit analog to digital to analog, 5M samples/second
dat org
dirh #5 'dac enable
wrpin ##%100011<<15,#4 'adc on
wrpin ##%0001<<28+%01100_0,#3 'count adc highs
wxpin #16,#3 '16 clocks per sample
dirh #3 'enable counter
setse1 #%01<<6+3 'se1 triggers on adc sample
loop waitse1 'wait adc sample
rdpin y,#3 'get adc sample
setnib x,y,#3 'set nib in dac mode
wrpin x,#5 'set dac
jmp #loop 'loop
x long %10100<<16 'dac mode
y long 0 'sample buffer
' 8-bit analog to digital to analog, 312.5k samples/second
dat org
dirh #5 'dac enable
wrpin ##%100011<<15,#4 'adc on
wrpin ##%0001<<28+%01100_0,#3 'count adc highs
wxpin #256,#3 '256 clocks per sample
dirh #3 'enable counter
setse1 #%01<<6+3 'se1 triggers on adc sample
loop waitse1 'wait adc sample
rdpin y,#3 'get adc sample
setbyte x,y,#1 'set nib in dac mode
wrpin x,#5 'set dac
jmp #loop 'loop
x long %10100<<16 'dac mode
y long 0 'sample buffer
' 12-bit analog to digital to analog, 19.5k samples/second
dat org
wrpin ##%101<<18+%01_00011_0,#5 '12-bit pwm dithered dac
wxpin ##4096,#5 '4,096 clocks per sample
dirh #5 'enable dac
wrpin ##%100011<<15,#4 'adc on
wrpin ##%0001<<28+%01100_0,#3 'count adc highs
wxpin ##4096,#3 '4,096 clocks per sample
dirh #3 'enable counter
setse1 #%01<<6+3 'se1 triggers on adc sample
loop waitse1 'wait adc sample
rdpin x,#3 'get adc sample
shl x,#4 'shift it up
wypin x,#5 'set dac
jmp #loop 'loop
x res 1 'sample buffer
Here's what I've been looking forward to trying...
The ADC has 1x, 10x, 25x, 50x, and 100x modes. At 100x, 33mV is full scale. You can capacitively couple a signal into the pin and it will bias it at center. The AC of the signal can then be digitized.
Here is a 20mV peak-to-peak sawtooth wave being digitized to 8 bits by the ADC at 100x and then played back through the DAC:
I turned on 'averaging' on the scope, because there was too much noise on the input (and, hence, the output) to make out much, otherwise. You can see, though, that the 20mV signal (top) is being digitized and output (bottom).
' 8-bit analog to digital to analog, 312.5k samples/second
dat org
dirh #5 'dac enable
wrpin ##%100111<<15,#4 'adc on
wrpin ##%0001<<28+%01100_0,#3 'count adc highs
wxpin #256,#3 '256 clocks per sample
dirh #3 'enable counter
setse1 #%01<<6+3 'se1 triggers on adc sample
loop waitse1 'wait adc sample
rdpin y,#3 'get adc sample
setbyte x,y,#1 'set byte in dac mode
wrpin x,#5 'set dac
jmp #loop 'loop
x long %10100<<16 'dac mode
y long 0 'sample buffer
Glad to hear it's working.
A lot of other chip's I've seen need external capacitors and sometimes a resistor around the crystal. Maybe this one does too?
The VCO runs at 1.8V and the power is filtered on the die. The PLL looks looks very jittery in some cases, and not others. I don't understand what the issue is, yet.
Do you have access to the VCO voltage control node, to sweep it externally ?
Maybe also add a series R to the OscOutput, to reduce the ringing currents, and so reduce Vcc ripple.
I'm using the ADC to digitize an incoming analog signal from my function generator and then those samples are going to the other analog pin in DAC mode.
Can you add notes to those around what the expected DAC resolution is for each, and what DAC mode is being tested.
DAC results seem to be always coarse ?
(IIRC DAC has Fast and slower modes ?)
Have you tested the DAC(s) using a slow triangle digital sweep ?
Glad to hear it's working.
A lot of other chip's I've seen need external capacitors and sometimes a resistor around the crystal. Maybe this one does too?
I'm not sure Chip is testing the Crystal Analog side yet ?
Common is to have a bias resistor internally, which needs to be quite high if targeting 32kHz modes.
The P1 has a choice a few CAP values, maybe P2 is the same ?
(but with lower Caps, to match the higher targeted crystals)
Another detail worth checking on the Xtal Amplifier, is the AC coupled Sine Amplitude threshold (will vary a little with MHz)
The Clipped Sine Oscillator modules usually spec > 0.8V p-p into 10K//10pF, with a source impedance < 470 Ohms
The sine wave input appears to dip down below zero - is that to deliberately test slightly beyond the rails? If so looks like its working well. Being able to pick up that 20mv 20khz signal in a 100x mode is really quite impressive
Not sure whether the dithering is working quite right though, unless its some CRO artefact
Glad to hear it's working.
A lot of other chip's I've seen need external capacitors and sometimes a resistor around the crystal. Maybe this one does too?
Like the Prop1, this has built-in loading caps. You can select between 15p and 30pf per leg. Effectively in series, that means 7.5pf and 15pf overall loading. There is only one level of drive strength and a fixed feedback resistance of ~1M ohms.
Comments
I'm really hoping the delta-sigma ADC works well.
How does this vary with temperature & time & Vcc ? - ie the Can of freeze and a soldering iron quick test -> > 70'C ?
Can you leave one running, and log the frequency over a few days - normally, you get a lazy temperature tracking drifts.
At Parallax there are big magnifiers and fine-tipped soldering irons that make it really easy. Water soluble flux in needle bottles helps, too. With those kinds of tools, you could solder even much smaller things. It's amazing what's possible with good tools. Tyrell and I soldered those. He did most of the work, just because he's so much faster, doing those things every day.
By the way, I went to sleep last night because I was too tired, after all the driving. So, I'm back to work now.
I was trying to work out the headers, I'm guessing you have some kind of long male headers that both let you plug into a P123-A9 and probe the signal at top as well?
That's right. It's a header with long pins out the top and bottom. It solders from the underside.
I think this was one of Jmg's suggestions.
The analog pins seem to work perfectly, so far. I've tried out the DAC modes and they all work great. I need to do some ADC testing, as well.
Sounds like great progress
What is the PFD range, on this PLL design ?
What exactly does "a little over-reactive" mean ?
Is it over-reactive on a NCO generated signal, vs a clean signal (crystal oscillator, or NCO binary setting) ?
As I've mentioned before, it's common for PLLs to run a VCO at 2x the required output, and use a local fast /2 to give exactly 50% outputs.
That's usually hidden in the docs a little, as that /2 is fixed and invisible to the equations.
If you do need to re-spin the PLL/PFD, I'd suggest extending the /M/N ranges ( & Xtal amplifier spec) to support the VCTCXOs (Clipped Sine).
I see these continue to fall in price, NEW at Digikey is this family.. common values are 19.2/26/27MHz etc
TG2016SBN 19.2000M-TCGNBM0 EPSON VCTCXO 19.2000MHZ $0.64500/1000 Clipped Sine, 500ppb 1.4mA (2.00mm x 1.60mm)
Can you easily vary Vcc over a range ? Is the PLL Vcc locally generated ?
The VCO runs at 1.8V and the power is filtered on the die. The PLL looks looks very jittery in some cases, and not others. I don't understand what the issue is, yet.
Here is an analog-to-digital-to-analog conversion at 4 bits (16 clocks) per sample (5 MSPS):
Here is 8 bits (256 clocks, 312.5kSPS):
And here is 12 bits (4,096 clocks, 39kSPS), which the scope can't do justice to:
Here are the programs:
Things are looking up! Exciting!
The ADC has 1x, 10x, 25x, 50x, and 100x modes. At 100x, 33mV is full scale. You can capacitively couple a signal into the pin and it will bias it at center. The AC of the signal can then be digitized.
Here is a 20mV peak-to-peak sawtooth wave being digitized to 8 bits by the ADC at 100x and then played back through the DAC:
I turned on 'averaging' on the scope, because there was too much noise on the input (and, hence, the output) to make out much, otherwise. You can see, though, that the 20mV signal (top) is being digitized and output (bottom).
If this proves out, we are ready for the full enchilada.
A lot of other chip's I've seen need external capacitors and sometimes a resistor around the crystal. Maybe this one does too?
Do you have access to the VCO voltage control node, to sweep it externally ?
Maybe also add a series R to the OscOutput, to reduce the ringing currents, and so reduce Vcc ripple.
Can you add notes to those around what the expected DAC resolution is for each, and what DAC mode is being tested.
DAC results seem to be always coarse ?
(IIRC DAC has Fast and slower modes ?)
Have you tested the DAC(s) using a slow triangle digital sweep ?
Common is to have a bias resistor internally, which needs to be quite high if targeting 32kHz modes.
The P1 has a choice a few CAP values, maybe P2 is the same ?
(but with lower Caps, to match the higher targeted crystals)
Another detail worth checking on the Xtal Amplifier, is the AC coupled Sine Amplitude threshold (will vary a little with MHz)
The Clipped Sine Oscillator modules usually spec > 0.8V p-p into 10K//10pF, with a source impedance < 470 Ohms
The sine wave input appears to dip down below zero - is that to deliberately test slightly beyond the rails? If so looks like its working well. Being able to pick up that 20mv 20khz signal in a 100x mode is really quite impressive
Not sure whether the dithering is working quite right though, unless its some CRO artefact
Very nice! I'm happy to see that the P2 project is progressing rapidly.
Kind regards, Samuel Lourenço
Like the Prop1, this has built-in loading caps. You can select between 15p and 30pf per leg. Effectively in series, that means 7.5pf and 15pf overall loading. There is only one level of drive strength and a fixed feedback resistance of ~1M ohms.