Finally, I figured that the internal 1.8V supply, on average, is a good reference, but it needs to be heavily filtered. So, I made this passive VDD filter that slows the voltage WAY down. It can take 400mV steps at 10KHz and reduce them to a gentle 5mV ripple:

.... Here it is with a simulation of it taking a 500mV-stepped VIO and a 250mV-stepped VDD, and regulating a nice, clean 1.8V power supply that is delivering 2.5mA. You can see the regulated 1.8V in red (VDDQ), along with the crazy stepped VDD and VIO supplies that feed the regulator. In reality, VIO will never transition so abruptly (500mV in 10ns), and those 50ns/25mV VDDQ spikes will be much lower:

Does this have the same Load-C that the chip will present ?

What PSRR does that give with a sine/triangle on the VIO ?

Does the P2 have an operating mode of 1.8V on both core and IO ?
If that is planned, then maybe this reference should be made 90-95% of 1.8V, to allow a small drop-out margin ?

The Load-C is the same. The VCO now just runs off the new supply, directly. There are no more caps within the VCO for filtering VDD. Those 100 caps in the regulator are all that is needed.

The PSRR would be very low with a sine or triangle wave on VIO. I gave it the torture test with a square wave and that step you see in the output is due mainly to charge injection into the WOTA's input PMOS gates. As VIO slams up or down, the source-gate charge transfer actually causes a net voltage change on F6's m=20 cap.

Only the I/O pins' interfacing runs at 1.8V. The PLL and the OSC are entirely 1.8V ciruits, though.

Maybe I'm not understanding, but the regulated quiet VDD supply will, on average, be the same as the internal VDD. The interfaces between those realms is pure digital, so I don't think there should be any trouble.

The PLL includes the PFD and the VCO, though only the VCO will need to run off the quiet supply.

Maybe I'm not understanding, but the regulated quiet VDD supply will, on average, be the same as the internal VDD. The interfaces between those realms is pure digital, so I don't think there should be any trouble.

Yes, I was just thinking of a possible case where VIO was 1.8V, when the result is no headroom for the regulator.
If VIO is always >> 1.8V, (2.5 or 3.3v) then there is enough headroom.

The PLL includes the PFD and the VCO, though only the VCO will need to run off the quiet supply.

OK. The PFD integrator caps need to use the Quiet supply, and the charge pumps should also use quiet, but the pure-digital elements of PFD are less important.

Maybe I'm not understanding, but the regulated quiet VDD supply will, on average, be the same as the internal VDD. The interfaces between those realms is pure digital, so I don't think there should be any trouble.

Yes, I was just thinking of a possible case where VIO was 1.8V, when the result is no headroom for the regulator.
If VIO is always >> 1.8V, (2.5 or 3.3v) then there is enough headroom.

The PLL includes the PFD and the VCO, though only the VCO will need to run off the quiet supply.

OK. The PFD integrator caps need to use the Quiet supply, and the charge pumps should also use quiet, but the pure-digital elements of PFD are less important.

VIO must always be 3.3V, so there is always headroom over VDD (1.8V).

Right about the purely digital stuff in the PLL being run from the main VDD, not the quiet VDD.

I have a question that you'll probably know the answer to:

In these OnSemi models, Monte Carlo simulation is controlled by two variables, which are each either 0 or 1: var_ms_mis and var_mc_proc. Var_mc_mis is for device-to-device mismatch and var_mc_proc is for process variation. They are used as follows throughout the models:

abs_variation: Largest deviation from nominal_val that can be obtained from a uniform or limit distribution, or the standard deviation multiplied by sigma for a Gaussian distribution.

sigma: Sigma-level at which the absolute or relative variation is specified
for a Gaussian distribution. For example, if sigma=3, the standard
deviation is abs_variation/3.

multiplier: Number of times the distribution function is evaluated. The largest
deviation from the nominal value of all evaluations is the one that is
used as the result. The resulting distribution is bimodal. (Default: 1.)

So, in their libraries, they set these var_mc_mis/var_mc_proc parameters to either 0 or 1, to disable or enable variation. But I see that you can use 2, 3, etc., as well, and get wilder variations.

I wonder... if I use the 'typical' libraries and set the var_mc_proc parameter to something greater than 1, can I get into the corner cases and not have to run so many simulations?

I wonder... if I use the 'typical' libraries and set the var_mc_proc parameter to something greater than 1, can I get into the corner cases and not have to run so many simulations?

abs_variation: Largest deviation from nominal_val that can be obtained from a uniform or limit distribution, or the standard deviation multiplied by sigma for a Gaussian distribution.

sigma: Sigma-level at which the absolute or relative variation is specified
for a Gaussian distribution. For example, if sigma=3, the standard
deviation is abs_variation/3.

It seems that abs_variation is not the one-sigma value, but the sigma given specifies what spread the abs_variation value applies to.
That makes it less clear what they actually test to, for their corner cases ?

I wonder... if I use the 'typical' libraries and set the var_mc_proc parameter to something greater than 1, can I get into the corner cases and not have to run so many simulations?

abs_variation: Largest deviation from nominal_val that can be obtained from a uniform or limit distribution, or the standard deviation multiplied by sigma for a Gaussian distribution.

sigma: Sigma-level at which the absolute or relative variation is specified
for a Gaussian distribution. For example, if sigma=3, the standard
deviation is abs_variation/3.

It seems that abs_variation is not the one-sigma value, but the sigma given specifies what spread the abs_variation value applies to.
That makes it less clear what they actually test to, for their corner cases ?

Yeah, I don't get it, either. That they use 1 or 0 implies that 1 will cover everything possible.

Sounds like you are just specifying the standard deviation for the Gaussian random distribution that you are sampling from. The two parameters seem redundant as the standard deviation is one divided by the other... Maybe it's just a fast way to make changes...

Anyway, any truly Gaussian distribution can give values over a large range...
But, I imagine they limit the result to be within 4 sigma or something...

Sounds like you are just specifying the standard deviation for the Gaussian random distribution that you are sampling from. The two parameters seem redundant as the standard deviation is one divided by the other... Maybe it's just a fast way to make changes...

Anyway, any truly Gaussian distribution can give values over a large range...
But, I imagine they limit the result to be within 4 sigma or something...

I just can't figure why they use only 0 or 1, per their libraries. Those values imply on/off, only.

The first parameter says the bell curve is centered on zero. So, zero is the expected value of the random variable. The last parameter seems not really needed, probably why just left 1...

Wait, I see you are talking about the second parameter being 0 or 1...
Guess 0 means no variation and the value is just 0.
1 would mean most results are somewhere between -1 and 1...

Guess I don't know why "1" makes sense for that...

Not the XI - The XOsc stage itself (XI to XO) is an unbuffereed P/N pair, but it should drive into a Schmitt buffer internally, to square up the sine wave, for the SysCLK ?
It is when the XO drops below that internal schmitt buffer threshold, that the clock effectively dies.
Usually that's roughly where XI-XO has unity gain, or a little less. ( Depends on the Hysteresis wrt 0.8v, and how threshold matched it is)

Ah, there is no Schmitt inside, just 4 series inverters (A connects to the XI pin):

Thinking some more about the lack of a Schmitt buffer after the Xtal buffer...
Having no schmitt is unusual, and this could cause out of spec clock signals while the Oscillator is building.

The problem is, 4-series inverters will give 'something out' even on millivolt-signals in, and the chances of that being a valid clock are poor.
A schmitt buffer acts like a natural amplitude-gate : ie until the swing is above a certain level, there are no clock edges.

Not the XI - The XOsc stage itself (XI to XO) is an unbuffereed P/N pair, but it should drive into a Schmitt buffer internally, to square up the sine wave, for the SysCLK ?
It is when the XO drops below that internal schmitt buffer threshold, that the clock effectively dies.
Usually that's roughly where XI-XO has unity gain, or a little less. ( Depends on the Hysteresis wrt 0.8v, and how threshold matched it is)

Ah, there is no Schmitt inside, just 4 series inverters (A connects to the XI pin):

Thinking some more about the lack of a Schmitt buffer after the Xtal buffer...
Having no schmitt is unusual, and this could cause out of spec clock signals while the Oscillator is building.

The problem is, 4-series inverters will give 'something out' even on millivolt-signals in, and the chances of that being a valid clock are poor.
A schmitt buffer acts like a natural amplitude-gate : ie until the swing is above a certain level, there are no clock edges.

I did it this way because I figured there'd be the least amount of phase shift from power supply fluctuations. This source is not even used until it's been given several milliseconds to stabilize. I could just put a Schmitt in, instead. What do you think?

Not the XI - The XOsc stage itself (XI to XO) is an unbuffereed P/N pair, but it should drive into a Schmitt buffer internally, to square up the sine wave, for the SysCLK ?
It is when the XO drops below that internal schmitt buffer threshold, that the clock effectively dies.
Usually that's roughly where XI-XO has unity gain, or a little less. ( Depends on the Hysteresis wrt 0.8v, and how threshold matched it is)

Ah, there is no Schmitt inside, just 4 series inverters (A connects to the XI pin):

Thinking some more about the lack of a Schmitt buffer after the Xtal buffer...
Having no schmitt is unusual, and this could cause out of spec clock signals while the Oscillator is building.

The problem is, 4-series inverters will give 'something out' even on millivolt-signals in, and the chances of that being a valid clock are poor.
A schmitt buffer acts like a natural amplitude-gate : ie until the swing is above a certain level, there are no clock edges.

I did it this way because I figured there'd be the least amount of phase shift from power supply fluctuations. This source is not even used until it's been given several milliseconds to stabilize. I could just put a Schmitt in, instead. What do you think?

I'd suggest a schmitt, but at the more modest Hyst end. ie Target 200~300mV of Hyst Band, which is well above any supply noise levels, but low enough to work comfortably with TCXO Clipped Sine signals.
Matching the P-N geometry ratios should have the hyst symmetic about the natural DC bias point of the Buffer/Oscillator.

This allows you to specify a minimum signal level, and the issue with "several milliseconds to stabilize" is crystals have wide variations. Larger, older ones have low RS, but newer, smaller SMD ones can be 3-4x that.

This would AC couple (100pF~1nF) into a standard Crystal Amplifier, with smallest CL selected.
Lower CL will help here.

There will be some limit MHz, where the Gain of the Xtal Buffer is not enough to exceed the schmitt buffer threshold, when driven this way.

Lowest Vcc and Highest Temp will be the worst corner.

The XI input is not Schmitt, just logic level. It sounds like you're thinking it's a Schmitt input.
..
Ah, there is no Schmitt inside, just 4 series inverters (A connects to the XI pin):
..
I think we would just capacitively couple the clipped sine osc into the XI pin, right?

Bumping this, I see Digikey now has stocks of the VCTCXOs, at 81c/250, ±500ppb -40°C ~ 85°C 1.5mA
these are impressive references.
They cover 16MHz~32MHz, with a few choices
TG2016SBN 32.0000M-TCGNBM3
TG2016SBN 26.0000M-TCGNBM3
TG2016SBN 16.3680M-PCGNDM3

To test, AC couple the clipped sine out, into the XI pin, and check XO level, or clock out.
A series R between Clipped sine , or a shunt R on the Clipped Sine pin, to lower the swing & check for margin.
(something an intern could do ?)

Clipped Sine Osc I tested, had about 200 ohms equiv Z-out.

It may be that 16MHz & 26MHz is fine, but 32MHz is more marginal.

## Comments

14,318That's looking good.

Does this have the same Load-C that the chip will present ?

What PSRR does that give with a sine/triangle on the VIO ?

Does the P2 have an operating mode of 1.8V on both core and IO ?

If that is planned, then maybe this reference should be made 90-95% of 1.8V, to allow a small drop-out margin ?

Does PLL here mean VCO and Phase Comparator sections ?

12,793The PSRR would be very low with a sine or triangle wave on VIO. I gave it the torture test with a square wave and that step you see in the output is due mainly to charge injection into the WOTA's input PMOS gates. As VIO slams up or down, the source-gate charge transfer actually causes a net voltage change on F6's m=20 cap.

Only the I/O pins' interfacing runs at 1.8V. The PLL and the OSC are entirely 1.8V ciruits, though.

Maybe I'm not understanding, but the regulated quiet VDD supply will, on average, be the same as the internal VDD. The interfaces between those realms is pure digital, so I don't think there should be any trouble.

The PLL includes the PFD and the VCO, though only the VCO will need to run off the quiet supply.

14,318So there are no plans to allow 1.8V VIO, that has to always be 3.3V (or 2.5v) ?

Yes, I was just thinking of a possible case where VIO was 1.8V, when the result is no headroom for the regulator.

If VIO is always >> 1.8V, (2.5 or 3.3v) then there is enough headroom.

OK. The PFD integrator caps need to use the Quiet supply, and the charge pumps should also use quiet, but the pure-digital elements of PFD are less important.

12,793VIO must always be 3.3V, so there is always headroom over VDD (1.8V).

Right about the purely digital stuff in the PLL being run from the main VDD, not the quiet VDD.

I have a question that you'll probably know the answer to:

In these OnSemi models, Monte Carlo simulation is controlled by two variables, which are each either 0 or 1: var_ms_mis and var_mc_proc. Var_mc_mis is for device-to-device mismatch and var_mc_proc is for process variation. They are used as follows throughout the models:

.param var_??? = agauss(0,var_mc_mis,1)

.param var_??? = agauss(0,var_mc_proc,1)

Here is the agauss function:

nominal_val: Nominal value for the parameter.

abs_variation: Largest deviation from nominal_val that can be obtained from a uniform or limit distribution, or the standard deviation multiplied by sigma for a Gaussian distribution.

sigma: Sigma-level at which the absolute or relative variation is specified

for a Gaussian distribution. For example, if sigma=3, the standard

deviation is abs_variation/3.

multiplier: Number of times the distribution function is evaluated. The largest

deviation from the nominal value of all evaluations is the one that is

used as the result. The resulting distribution is bimodal. (Default: 1.)

So, in their libraries, they set these var_mc_mis/var_mc_proc parameters to either 0 or 1, to disable or enable variation. But I see that you can use 2, 3, etc., as well, and get wilder variations.

I wonder... if I use the 'typical' libraries and set the var_mc_proc parameter to something greater than 1, can I get into the corner cases and not have to run so many simulations?

14,318Usually, yes, you can move out the curves like this

https://en.wikipedia.org/wiki/Standard_deviation

but this wording has me confused.... It seems that abs_variation is not the one-sigma value, but the sigma given specifies what spread the abs_variation value applies to.

That makes it less clear what they actually test to, for their corner cases ?

12,793Yeah, I don't get it, either. That they use 1 or 0 implies that 1 will cover everything possible.

10,878Anyway, any truly Gaussian distribution can give values over a large range...

But, I imagine they limit the result to be within 4 sigma or something...

12,793I just can't figure why they use only 0 or 1, per their libraries. Those values imply on/off, only.

10,878Wait, I see you are talking about the second parameter being 0 or 1...

Guess 0 means no variation and the value is just 0.

1 would mean most results are somewhere between -1 and 1...

Guess I don't know why "1" makes sense for that...

14,318Thinking some more about the lack of a Schmitt buffer after the Xtal buffer...

Having no schmitt is unusual, and this could cause out of spec clock signals while the Oscillator is building.

The problem is, 4-series inverters will give 'something out' even on millivolt-signals in, and the chances of that being a valid clock are poor.

A schmitt buffer acts like a natural amplitude-gate : ie until the swing is above a certain level, there are no clock edges.

12,793I did it this way because I figured there'd be the least amount of phase shift from power supply fluctuations. This source is not even used until it's been given several milliseconds to stabilize. I could just put a Schmitt in, instead. What do you think?

14,318I'd suggest a schmitt, but at the more modest Hyst end. ie

Target 200~300mV of Hyst Band, which is well above any supply noise levels, but low enough to work comfortably with TCXO Clipped Sine signals.Matching the P-N geometry ratios should have the hyst symmetic about the natural DC bias point of the Buffer/Oscillator.

This allows you to specify a minimum signal level, and the issue with "several milliseconds to stabilize" is crystals have wide variations. Larger, older ones have low RS, but newer, smaller SMD ones can be 3-4x that.

14,318Bumping this, I see Digikey now has stocks of the VCTCXOs, at

81c/250, ±500ppb -40°C ~ 85°C 1.5mAthese are impressive references.

They cover 16MHz~32MHz, with a few choices

TG2016SBN 32.0000M-TCGNBM3

TG2016SBN 26.0000M-TCGNBM3

TG2016SBN 16.3680M-PCGNDM3

To test, AC couple the clipped sine out, into the XI pin, and check XO level, or clock out.

A series R between Clipped sine , or a shunt R on the Clipped Sine pin, to lower the swing & check for margin.

(something an intern could do ?)

Clipped Sine Osc I tested, had about 200 ohms equiv Z-out.

It may be that 16MHz & 26MHz is fine, but 32MHz is more marginal.