@cgracey said:
There is a sense inverter on XI that feeds the PLL.
That's what I was expecting. And in the docs it says this of the XI source select:
CC != %00, allow 5ms for crystal to stabilize before switching to XI
It seems there is at least the desire to also have XI as a clock input other than crystal feedback.
However, I've now soldered wires onto the XI input and GND on an Eval Board and tested HUBSET #%00_10 with a 1 MHz square wave inputted but, sadly, no action from the Prop2. The 1 MHz to XI looks good on the scope. By commenting out said HUBSET, the Prop2 under test comes back to life - running from RCFAST. So I haven't killed the chip yet.
PS: Here's the DUT source code:
dat org
hubset #%00_10 'XI input from external clock gen
rep @.rend, #0
drvnot #56 'toggle pin P56
waitx ##1_000_000
.rend
@evanh said:
I think the docs need changed too. There is too much hinting at %00 having a function.
It does have a function
It powers everything down, ie both the XI-XO Osc amplifier and the XI buffer amplifier so the Icc does not care what level those pins have.
The Xtal buffer draws significant current in the linear region.
There are two buffers in any Xtal oscillator.
One between XI-XO that activates the crystal, but there is another buffer, often overlooked, that has to take the sine wave, and square it up.
That buffer needs to also be disabled, if you want low power from the pins (or you need to drive XI to a known digital level)
I guess Chip could have added a light pulldown to XI, and kept the XI buffer enabled, as an alternate power saving approach, but that was not done.
When mode %00 is selected, the inverter and feedback resistor are turned off and XI is disconnected from the sense inverter (which should have been a Schmitt trigger).
Comments
Chip,
Exactly where does the internal clock circuits tap into the crystal oscillator loop?
There is a sense inverter on XI that feeds the PLL. Should have put a Schmitt in like JMG said to.
Meh. Cut yourself some slack, Chip. So much of the P2 was done darned near perfectly. Besides, there is always the P3! Encore?
That's what I was expecting. And in the docs it says this of the XI source select:
It seems there is at least the desire to also have XI as a clock input other than crystal feedback.
However, I've now soldered wires onto the XI input and GND on an Eval Board and tested
The 1 MHz to XI looks good on the scope. By commenting out said HUBSET, the Prop2 under test comes back to life - running from RCFAST. So I haven't killed the chip yet. 
HUBSET #%00_10with a 1 MHz square wave inputted but, sadly, no action from the Prop2.PS: Here's the DUT source code:
dat org hubset #%00_10 'XI input from external clock gen rep @.rend, #0 drvnot #56 'toggle pin P56 waitx ##1_000_000 .rendbut CC=%00 disables the Xtal amplifier and it disables the XI buffer,
Docs state : %00 XI ignored
Your comment XI input from external clock gen is wishful thinking, not what actually happens in HW
so you need anything above %00 to activate XI
I think the docs need changed too. There is too much hinting at %00 having a function, when it has none at all.
It does have a function
It powers everything down, ie both the XI-XO Osc amplifier and the XI buffer amplifier so the Icc does not care what level those pins have.
The Xtal buffer draws significant current in the linear region.
That's XO, not XI.
There are two buffers in any Xtal oscillator.
One between XI-XO that activates the crystal, but there is another buffer, often overlooked, that has to take the sine wave, and square it up.
That buffer needs to also be disabled, if you want low power from the pins (or you need to drive XI to a known digital level)
I guess Chip could have added a light pulldown to XI, and kept the XI buffer enabled, as an alternate power saving approach, but that was not done.
Something to clarified in the docs.
When mode %00 is selected, the inverter and feedback resistor are turned off and XI is disconnected from the sense inverter (which should have been a Schmitt trigger).
Thanks. I've added a small comment to the silicon doc saying that %CC = %01 is required with an external clock source.