I put a 1 pF cap with radial leads across XI and XO and got a similar messing up of VGA screen as with Eval board.
But, it could be my fingers added to that capacitance...
No Chip. I thought I made that pretty clear. While the VGA connector is still connected to the p27-p28-31 pins, I connected another VGA connector (and my monitor) on pins P0-4 and the software uses base pin 0 for the code I posted above.
Originally I used Rogers binary with the Mario pic to test both my board and the p2eval. Without the source this obviously has the vga on p0-4 and the kill sequence on p28-31.
Reduce the parasitic capacitance between XTALIN and XTALOUT pins by routing them as far apart
as possible
This and my limited knowledge on the subject makes me think the traces are too close together.
I'm tempted to cut one of the traces and use a jumper instead.
Don't want to mess up my Eval board though
Yes, there definitely should be a ground trace separating the two xtal tracks.
But don’t cut your tracks. This is the effect, not the cause, although it certainly wouldn’t be helping.
I did a better test with a ceramic capacitor selection and found you need 43 pF between XI and XO to reproduce the shaky video on my board.
4 pF more and no video, 4 pF less and it's fine.
Hard to image the PCB traces adding more than about 1 pF though...
This is a puzzle... The only other things I'm seeing are what looks like vias that connect top and bottom planes right next to the crystal.
Maybe there's coupling there somehow?
Actually, it looks like these vias connect top, bottom, and Inner1 layers. Is this the only place where all these layers are connected?
I'm not seeing ground between the traces. But, I don't have ground between my I/O pin traces either...
What I'd like to test is cutting the traces to the SMT crystal and then adding in a thru hole crystal to the pads there.
Not going to do that though...
I think it has to be those vias that tie the three layers together...
@Rayman said:
I did a better test with a ceramic capacitor selection and found you need 43 pF between XI and XO to reproduce the shaky video on my board.
4 pF more and no video, 4 pF less and it's fine.
Hard to image the PCB traces adding more than about 1 pF though...
Nice test.
Yes, I'd not expect anywhere near 43pF - just single digit C added by that less than ideal trace routing.
C coupling directly across between XI and XO does lower the amplifier gain, so it is unwanted.
Addit: Looking at the P2 Xtal Osc+Buffer SCH, the buffer take off is XI pin, the XO is purely Osc only. (this allows high MHz drive into XI, without worrying about gain rolloff)
On the package the XI pin is separated by XO pin from the aggressor logic pins, with power on the other side of XI.
That also means the P2 Eval PCB cross-C effect may give an extra unwanted path for Capacitive coupling of aggressor pin across onto XI ?
If the effect is parasitic L on the power/gnds, then the larger CL of the P2-Eval tracks, may be enough to account for some of that ?
One CL test would be to check PLL on a P2-Edge unplugged vs plugged in ? That's sure to have different Xtal and Pin loading numbers.
Von Sarvas and I took lots of measurements today and towards the end (2am for him), he thought he'd try lifting up the XI and XO pins and hooking up the crystal off the board. It looks like it solved the problem.
Here are XI (coupled through a cap) and P31 on the stock P2 Eval board. You can see the coupling. This was taken at an 8GHz sampling rate.
We will make future boards with simple traces on the top of the board to connect the crystal. Going down into inner layers and getting near sharp edges is not good. Cluso and Peter did it right on their RetroBlade and P2D2 boards.
Here is the program used:
_clkfreq = 297_000_000
pins = 28 addpins 3
DAT org
asmclk 'set clock mode
coginit #1,#@pgm2 'launch cog to monitor jitter on P0
wrpin ##%01_00110_0,#pins 'set NCO on smart pins
wxpin #1,#pins 'time base = 1 clock
wypin ##$8000_0000>>2,#pins 'set max frequency
drvl #pins 'smart pins
jmp #$ 'loop while smart pins run
org
pgm2 drvnot #0 'output sysclk/100 on P0
waitx #50-2-2-4
jmp #pgm2
Chip, that's good that you found the problem. Looking though at the second scope picture I am wondering why you would squash the noise down using a 1V/div setting? At first I thought it looked quiet but then I noticed the 1V/div and then Vp-p figures of up to 376mV. But I will go and measure that on my boards too just for comparison. An FFT of the noise is more useful though. I had noticed that those 4.7uF caps had low ESR at 1MHz but the P2 is operating at 200MHz plus. The 0.1uF caps on our boards have much lower ESR at higher frequencies plus they are paralleled for even lower ESR and high capacitance although there are also the bulk caps too.
@cgracey said:
Von Sarvas and I took lots of measurements today and towards the end (2am for him), he thought he'd try lifting up the XI and XO pins and hooking up the crystal off the board. It looks like it solved the problem.
Here are XI (coupled through a cap) and P31 on the stock P2 Eval board. You can see the coupling. This was taken at an 8GHz sampling rate.
We will make future boards with simple traces on the top of the board to connect the crystal. Going down into inner layers and getting near sharp edges is not good. Cluso and Peter did it right on their RetroBlade and P2D2 boards.
Sounds good.
That also suggests a clipped sine, cap-coupled to XI, may also be ok, if care is taken over the aggressor shielding of XI ?
Allowing for a Oscillator options, allows for better ppm alternatives.
XO is definitely close to P31 and it looks like these sharp noise spikes on XO are coupling through the crystal into XI, where extra transitions are registered in the PLL.
I had noticed that those 4.7uF caps had low ESR at 1MHz but the P2 is operating at 200MHz plus. The 0.1uF caps on our boards have much lower ESR at higher frequencies plus they are paralleled for even lower ESR and high capacitance although there are also the bulk caps too.
For reference, here's the "ESR vs. Freq." data on the 4.7uF (C1005X5R0J475) we are using, and also the 0.1uF (CGA2B1X7R1C104) in the same package.
@cgracey said:
XO is definitely close to P31 and it looks like these sharp noise spikes on XO are coupling through the crystal into XI, where extra transitions are registered in the PLL.
P31 is certainly not required for the instabilities to occur. I can set it driven low and then toggle the other three, P28-P30. The amount of instability is hardly changed. It's actually noisier than I'd guessed it should be given that one of the four pins isn't toggling.
I'd say the noise path is definitely from bounce on the power rails as earlier speculated, and now shown on the scope ... but, instead of that going deeper into the oscillator circuit, it is transposed onto XO by its own drive circuit. From there crosstalk puts it on XI ... and subsequently gets amplified.
Moving the xtal up to the pins was a little fiddly-fine too, but it just made it!
Thanks for the corner GND "tabs" that very slightly protrude from the P2 chip corners, it made for a convenient install. The loop wire was to aid soldering, as heating one end of the wire would detach it from the other end too quickly otherwise. An extra pair of micro-hands for holding a jumper wire directly would have been handy, and of course not available in the moment!
@VonSzarvas said:
Moving the xtal up to the pins was a little fiddly-fine too, but it just made it!
Thanks for the corner GND "tabs" that very slightly protrude from the P2 chip corners, it made for a convenient install. The loop wire was to aid soldering, as heating one end of the wire would detach it from the other end too quickly otherwise. An extra pair of micro-hands for holding a jumper wire directly would have been handy, and of course not available in the moment!
Ok, so then you have replicated the jitter output issue also on the current P2 Edge as well. To now I had imagined it was only happening on P2-EVAL as I had not tried the P2 Edge board here yet and I had assumed most of the discussion has been talking about P2-EVAL.
Yes. The via/plane routing appears to have an inductive impact for both boards.
Current thinking is that both boards will have the clock routing moved to the top layer (no vias) on the next rev's.
For the EVAL the XI/XO through-hole hookup point should be removed, and hopefully replaced with an U.FL footprint or socket.
If it really is those vias causing the trouble, you should be able to cut the traces, just past the through-hole hookup.
Then, solder the crystal to the through-holes.
I'm thinking you don't actually have to connect the ground on the crystal case. That's probably just for EMI...
I'm thinking you don't actually have to connect the ground on the crystal case. That's probably just for EMI...
With 2520 Xtals, you can usefully connect pin 2 and GND, and take pin 4 to a separate PAD. (only 1 gnd is needed)
If Pin 3 is then routed to XI, that covers a few choices
Standard XTAL Pin 1 = XO Pin 2 = GND Pin 3=XI Pin 4 = NU (spare gnd)
Thermistor Xtal Pin 1 = XO Pin 2 = GND Pin 3=XI Pin 4 = NTC, SB or Wire to P2 ADC Pin
Osc or TCXO Pin 1 = CUT Pin 2 = GND Pin 3=XI Pin 4 = VCC, SB or Wire to 3v3
Osc.ClippedSW Pin 1 = CUT Pin 2 = GND Pin 3=XI via series C Pin 4 = VCC, Wire to 3v3 or 1v8
@Rayman said:
Is it better to only ground one of the crystal case connections? I'm not sure...
Probably about the same with one or both grounded I'd imagine...
The Xtal data usually says both 2 & 4 connect to the metal lid, except for NTC Xtals, where pin 4 is NTC. On Oscillators, pin 4 is Vdd, so that is useful to not hard-gnd connect.
It is certainly useful to gnd the metal lid, as that is a shield over the analog crystal area, but only a single pin can do that.
Comments
I put a 1 pF cap with radial leads across XI and XO and got a similar messing up of VGA screen as with Eval board.
But, it could be my fingers added to that capacitance...
Cluso, I looked at your schematic. Are you running VGA on P28..P31 when you run the killpll() method that toggles the OUT bits of P28..P31?
Here is your schematic:
No Chip. I thought I made that pretty clear. While the VGA connector is still connected to the p27-p28-31 pins, I connected another VGA connector (and my monitor) on pins P0-4 and the software uses base pin 0 for the code I posted above.
Originally I used Rogers binary with the Mario pic to test both my board and the p2eval. Without the source this obviously has the vga on p0-4 and the kill sequence on p28-31.
Yes, there definitely should be a ground trace separating the two xtal tracks.
But don’t cut your tracks. This is the effect, not the cause, although it certainly wouldn’t be helping.
I did a better test with a ceramic capacitor selection and found you need 43 pF between XI and XO to reproduce the shaky video on my board.
4 pF more and no video, 4 pF less and it's fine.
Hard to image the PCB traces adding more than about 1 pF though...
This is a puzzle... The only other things I'm seeing are what looks like vias that connect top and bottom planes right next to the crystal.
Maybe there's coupling there somehow?
Actually, it looks like these vias connect top, bottom, and Inner1 layers. Is this the only place where all these layers are connected?
I'm don't know Diptrace, so maybe I'm seeing it wrong... But are these plated vias just about touching the P2 I/O pin traces?
Nevermind. I see now that these are blind vias only on the top two layers
There might also be unterminated transmission line effects happening on those fast toggling i/o pins.
Also, I thought there were interposing grounds between those buried P2 signal traces?
I'm not seeing ground between the traces. But, I don't have ground between my I/O pin traces either...
What I'd like to test is cutting the traces to the SMT crystal and then adding in a thru hole crystal to the pads there.
Not going to do that though...
I think it has to be those vias that tie the three layers together...
This MEGA style P2 board is also unaffected by the PLL killer.
Had to make some jumpers to test it out...
Is that test with SI5351, or a P2.Xtal option ?
Nice test.
Yes, I'd not expect anywhere near 43pF - just single digit C added by that less than ideal trace routing.
C coupling directly across between XI and XO does lower the amplifier gain, so it is unwanted.
Addit: Looking at the P2 Xtal Osc+Buffer SCH, the buffer take off is XI pin, the XO is purely Osc only. (this allows high MHz drive into XI, without worrying about gain rolloff)
On the package the XI pin is separated by XO pin from the aggressor logic pins, with power on the other side of XI.
That also means the P2 Eval PCB cross-C effect may give an extra unwanted path for Capacitive coupling of aggressor pin across onto XI ?
If the effect is parasitic L on the power/gnds, then the larger CL of the P2-Eval tracks, may be enough to account for some of that ?
One CL test would be to check PLL on a P2-Edge unplugged vs plugged in ? That's sure to have different Xtal and Pin loading numbers.
Von Sarvas and I took lots of measurements today and towards the end (2am for him), he thought he'd try lifting up the XI and XO pins and hooking up the crystal off the board. It looks like it solved the problem.
Here are XI (coupled through a cap) and P31 on the stock P2 Eval board. You can see the coupling. This was taken at an 8GHz sampling rate.
We will make future boards with simple traces on the top of the board to connect the crystal. Going down into inner layers and getting near sharp edges is not good. Cluso and Peter did it right on their RetroBlade and P2D2 boards.
Here is the program used:
_clkfreq = 297_000_000 pins = 28 addpins 3 DAT org asmclk 'set clock mode coginit #1,#@pgm2 'launch cog to monitor jitter on P0 wrpin ##%01_00110_0,#pins 'set NCO on smart pins wxpin #1,#pins 'time base = 1 clock wypin ##$8000_0000>>2,#pins 'set max frequency drvl #pins 'smart pins jmp #$ 'loop while smart pins run org pgm2 drvnot #0 'output sysclk/100 on P0 waitx #50-2-2-4 jmp #pgm2Here is GND and V2831 across the local 4.7uF cap, with all four pins toggling every 10ns. This is on the P2 Eval board.
Chip, that's good that you found the problem. Looking though at the second scope picture I am wondering why you would squash the noise down using a 1V/div setting? At first I thought it looked quiet but then I noticed the 1V/div and then Vp-p figures of up to 376mV. But I will go and measure that on my boards too just for comparison. An FFT of the noise is more useful though. I had noticed that those 4.7uF caps had low ESR at 1MHz but the P2 is operating at 200MHz plus. The 0.1uF caps on our boards have much lower ESR at higher frequencies plus they are paralleled for even lower ESR and high capacitance although there are also the bulk caps too.
I'm still curious as to what exactly the issue was... Is it the vias next to the xtal? i think it must be...
Sounds good.
That also suggests a clipped sine, cap-coupled to XI, may also be ok, if care is taken over the aggressor shielding of XI ?
Allowing for a Oscillator options, allows for better ppm alternatives.
XO is definitely close to P31 and it looks like these sharp noise spikes on XO are coupling through the crystal into XI, where extra transitions are registered in the PLL.
I had noticed that those 4.7uF caps had low ESR at 1MHz but the P2 is operating at 200MHz plus. The 0.1uF caps on our boards have much lower ESR at higher frequencies plus they are paralleled for even lower ESR and high capacitance although there are also the bulk caps too.
For reference, here's the "ESR vs. Freq." data on the 4.7uF (C1005X5R0J475) we are using, and also the 0.1uF (CGA2B1X7R1C104) in the same package.
^^^^ At 1 GHz, the 4.7uF and the 0.1uF have about the same ESR.
P31 is certainly not required for the instabilities to occur. I can set it driven low and then toggle the other three, P28-P30. The amount of instability is hardly changed. It's actually noisier than I'd guessed it should be given that one of the four pins isn't toggling.
I'd say the noise path is definitely from bounce on the power rails as earlier speculated, and now shown on the scope ... but, instead of that going deeper into the oscillator circuit, it is transposed onto XO by its own drive circuit. From there crosstalk puts it on XI ... and subsequently gets amplified.
Solution is still improved routing of XI/XO.
I suppose P31 can still be noisy even with it driven steady. I'm not keen on trying to solder it to GND. Just too fine for me.
Moving the xtal up to the pins was a little fiddly-fine too, but it just made it!
Thanks for the corner GND "tabs" that very slightly protrude from the P2 chip corners, it made for a convenient install. The loop wire was to aid soldering, as heating one end of the wire would detach it from the other end too quickly otherwise. An extra pair of micro-hands for holding a jumper wire directly would have been handy, and of course not available in the moment!
No way! Is that really three solder joints!?
Ok, so then you have replicated the jitter output issue also on the current P2 Edge as well. To now I had imagined it was only happening on P2-EVAL as I had not tried the P2 Edge board here yet and I had assumed most of the discussion has been talking about P2-EVAL.
Yes. The via/plane routing appears to have an inductive impact for both boards.
Current thinking is that both boards will have the clock routing moved to the top layer (no vias) on the next rev's.
For the EVAL the XI/XO through-hole hookup point should be removed, and hopefully replaced with an U.FL footprint or socket.
If it really is those vias causing the trouble, you should be able to cut the traces, just past the through-hole hookup.
Then, solder the crystal to the through-holes.
I'm thinking you don't actually have to connect the ground on the crystal case. That's probably just for EMI...
With 2520 Xtals, you can usefully connect pin 2 and GND, and take pin 4 to a separate PAD. (only 1 gnd is needed)
If Pin 3 is then routed to XI, that covers a few choices
Is it better to only ground one of the crystal case connections? I'm not sure...
Probably about the same with one or both grounded I'd imagine...
The Xtal data usually says both 2 & 4 connect to the metal lid, except for NTC Xtals, where pin 4 is NTC. On Oscillators, pin 4 is Vdd, so that is useful to not hard-gnd connect.
It is certainly useful to gnd the metal lid, as that is a shield over the analog crystal area, but only a single pin can do that.