Now you've asked the question, I think that'll be okay. It'll presuambly load the signal a little compared to no crystal. HUBSET #%00_10 should do the job. Docs say XO is floating.
In order to configure XI as an input, the way the %CC-bits works will simultaneouslly turn on XO, so the crystal can't be "effectivelly removed" or "partly floated" from the XI/XO circuitry, keeping it in series, "compressed" between these two pins.
The "least-collateral-damage" consequence would be an annoying beat (too much construtive/destructive interference), between the external oscillator frequency, and the one that is characteristic to the crystal. This would mess everything timing-related, within P2 internal circuitry, as soon as XI input is enabled.
The "worst" would be destructing the crystal, due to excess power dissipation, or the external oscillator, or both, and praying to don't also affect XO's output-buffer, at all.
That can't be right. In the %SS == %10 clock source of XI it explicitly refers to %CC != %00 needing a crystal stabilising time. Implying there is also a valid use of %CC == %00.
The docs need fixed to say XI is always an input.
Sorry, but I'm interpreting doc's statement "CC != %00" as "anything, but zero", meaning either of the other three options are valid, except CC = %00. That "fpga-jargon" is too much painfull, sometimes...
@rogloh said:
I'm trying to get it to work so I can use P28-P31 for a data bus at high speed without messing up the P2 clock frequency. Is such a solution now known to fully remedy the problem?
Hehe, I didn't read past the first sentence. PLL will work with that too of course. so HUBSET ##%...._00_11 should work just as well as #%00_10 will.
Sorry, but I'm interpreting doc's statement "CC != %00" as "anything, but zero", meaning either of the other three options are valid, except CC = %00. That "fpga-jargon" is too much painfull, sometimes...
You're absolutely right. I feel the docs are wrong though. It only makes sense for %CC=%00 to be an input on XI. That mode would be useless if XI not an input.
Put it this way. The other three options are all for directly driving a crystal. It makes sense to have the fourth option for an alternative external oscillator source.
During one of the former meetings, Chip did said that activating XI also enables XO output buffer, but it would stay inactive when CC = %00, so I understood it as an acknowledgement of the correctness of %CC function table.
That was the reason of my suggestion of using the activation of XO as a way to craft a suitable control over the (active-high) INH-pin of the 20 MHz Kyocera clock oscillator that was innitially intended to be used, so as to spare 3.3V regulator from feeding as much power to the external oscillator, targetting a energy-conscious design.
Sorry, but I'm interpreting doc's statement "CC != %00" as "anything, but zero", meaning either of the other three options are valid, except CC = %00. That "fpga-jargon" is too much painfull, sometimes...
You're absolutely right. I feel the docs are wrong though. It only makes sense for %CC=%00 to be an input on XI. That mode would be useless if XI not an input.
My reading is that the %00 case disables the feedback resistor Rf and disables the XI-XO buffer, so that the Amplifier and buffer are put to sleep.
The external Oscillator mode, is %01 which has added CL=0pf, but that modes does enable Rf and the XI-XO buffer.
@Yanomani said:
During one of the former meetings, Chip did said that activating XI also enables XO output buffer, but it would stay inactive when CC = %00, so I understood it as an acknowledgement of the correctness of %CC function table.
That was the reason of my suggestion of using the activation of XO as a way to craft a suitable control over the (active-high) INH-pin of the 20 MHz Kyocera clock oscillator that was innitially intended to be used, so as to spare 3.3V regulator from feeding as much power to the external oscillator, targetting a energy-conscious design.
Has anyone tried such stealth connection of XO as a Osc enable ?
It's not completely clear what XO pin does when disabled at %00, my guess is it floats, and becomes ~50% Vcc when enabled (from the !XI signal).
Most OSC need Pin 1 < 0.3Vcc to disable them, and > 0.7Vcc or floating to enable which makes XO-disable backwards.
A RET (100k?) PNP transistor between XO and Pin1 might give enough flip and filter to use that stealth XO as an enable, for deep power down uses.
The better newer oscillators are way better than the older ones, I've measured ~1.5mA at 48MHz and low CL, so the power saving are possible, but not many mA.
Checking a Yangxing lcsc.C669070 YSO110TR, 47k or 100k pulldown shuts down
Yeah, XO floats when %CC = %00, so a high-ohmic value resistor (~100 kOhm) pulling the pin to V2831 would be enough to ensure it'll stay quiet, until enabled by the execution of a suitable hubset instruction.
Another resistor of about the same value, now pulling XI to the same Vio, will ensure XO being forced Low, as soon as any other mode, different from %00, is programmed at %CC by a hubset instruction.
I'm an "old school-addicted", thus I suggested the use of a SN74LVC1G123 monostable multivibrator, in this case, with both !A and B triggers connected to XO, while !CLR can be pulled high to the Vio node, thru a ~50 kOhm resistor.
This way, when XO does innitially falls-down, and subsequently, at any other transition on that pin, the Q output of the 123 will be issuing a continuous High level, suitable to drive the INH pin into a High state, keeping the oscillator enabled, untill any of the following events does occur:
a power off event;
P2 reset, or;
%CC being returned to %00, disabling the external oscillator, since XO will stop re-triggering the monostable, leaving the LVC1G123's output at a Low level, after the timing-out of the last High pulse.
The proposed IC package can be as small as ~2 x 1 mm, and priced in the range of US$ 0.20, in 1k quantities; the other sixeight components (fourfive resistors and twothree ceramic capacitors) would be cheap too, and the small area occupyed at the pcb will not be much of a concern, at all.
The proposed IC package can be as small as ~2 x 1 mm, and priced in the range of US$ 0.20, in 1k quantities; the other six components (4 resistors and two ceramic capacitors) would be cheap too, and the small area occupyed at the pcb will not be much of a concern, at all.
That's a large BOM and too many parts for Edge.
I think you can do it with just one component, eg PUMD12 or MUN5313DW1 or == RET (47k or 100k bias R1==R2, or maybe PUMD16^ R1 = 22 k, R2 = 47 k ?)
^ Spice suggests the slightly lower threshold of PUMD16 gives better margin, and the lower Rb is still ok with 20MHz, still plenty of LPF action.
The PNP-B is connected to XO and the NPN-B connects to PNP-C and pull down Osc.Pin1. (NPN-C is unused, that part is just a zero-BOM resistor..)
XO floats means PNP is off and NPN-B pulls down disabling (tri-state) OSC, and XO active, means PNP is ON, pulling Pin1 HI enables OSC.
Higher base resistors mean lower power, and slow things down as you want the AC part of XO ignored. ie higher Rb is better.
For the enable to work, XO needs to be 50% or 0% of Vcc, so the TS/Enable pin needs to either float, or force hi & the ones I've checked do work that way.
@rogloh said:
Is it safe to feed a 20MHz oscillator output directly to the XI pin on the revB P2-EVAL board with the crystal still fitted?
I did that when testing Clipped Sine (AC Coupled into XI, Xtal not removed) and that was fine for 26MHz and 38.4MHz tests.
Great, an answer. I'm hoping not to need to rework the P2-EVAL board or damage the crystal or P2. I was imagining that as that XI pad was fitted then this should be possible and Parallax would likely not have expected us to need to remove the crystal.
I am planning to use a Si5351 clock generator breakout which appears to have a 3.3V direct buffered output with 50 ohm output impedance. I will set it to 20MHz and feed one of its 3 outputs into the XI pin.
Silicon labs has a msop10 variant that allows two sources (crystal + external clock in). This allows to use clock sources from external modules (like USB ft232h synchronous 60MHz clock for 48MB/s data transfers). -> Si5350C-B-GT
Could be a good compromise between small space footprint, number of input sources, hand solderability. There are other far more capable (like stratum 3 or better) but they are high pin count in QFN package.
@Ramon said:
Silicon labs has a msop10 variant that allows two sources (crystal + external clock in). This allows to use clock sources from external modules (like USB ft232h synchronous 60MHz clock for 48MB/s data transfers). -> Si5350C-B-GT
I don't think the MSOP version of the Si5350C, includes i2c support, which makes it less generally useful.
You can feed an external clock into Si5351A.MSOP10 with a series element.
In my case I only need something simple, so will probably get this https://learn.adafruit.com/adafruit-si5351-clock-generator-breakout/pinouts
and mate it to the smaller P2-EVAL proto board for plugging into P56-P63 on the P2-EVAL That's a useful place for it because these 2 pins (56,57) are otherwise wasted (unless you need them for LEDs, or you wanted to plug in the wireless board on the revC). A bonus with that Adafruit board is that it has a regulator that can be powered with 5V or 3.3V so I can flip the breakout 180 degrees to face inwards and keep the clock wire short or flip it back to face outwards and access SMA clock outputs for other purposes.
If this approach works there's probably scope for someone to create a more versatile I2C controlled clock board for people to experiment with different timing applications or options with the P2. A clock input could be good then.
@rogloh said:
In my case I only need something simple, so will probably get this https://learn.adafruit.com/adafruit-si5351-clock-generator-breakout/pinouts
and mate it to the smaller P2-EVAL proto board for plugging into P56-P63 on the P2-EVAL That's a useful place for it because these 2 pins (56,57) are otherwise wasted (unless you need them for LEDs, or you wanted to plug in the wireless board on the revC). A bonus with that Adafruit board is that it has a regulator that can be powered with 5V or 3.3V so I can flip the breakout 180 degrees to face inwards and keep the clock wire short or flip it back to face outwards and access SMA clock outputs for other purposes.
If this approach works there's probably scope for someone to create a more versatile I2C controlled clock board for people to experiment with different timing applications or options with the P2. A clock input could be good then.
That Adafruit board is nice.
P2D2 uses the Si5351A, and you can AC couple a clipped sine oscillator into the XA pin.
SiLabs have released a QFN16 option but that is not showing stocked anywhere yet. (the MSOP package has worse jitter on paper than the QFN packages)
I think you can do it with just one component, eg PUMD12 or MUN5313DW1 or == RET (47k or 100k bias R1==R2, or maybe PUMD16^ R1 = 22 k, R2 = 47 k ?)
^ Spice suggests the slightly lower threshold of PUMD16 gives better margin, and the lower Rb is still ok with 20MHz, still plenty of LPF action.
The PNP-B is connected to XO and the NPN-B connects to PNP-C and pull down Osc.Pin1. (NPN-C is unused, that part is just a zero-BOM resistor..)
XO floats means PNP is off and NPN-B pulls down disabling OSC, and XO active, means PNP is ON, pulling PIn1 HI enables OSC.
Higher base resistors mean lower power, and slow things down as you want the AC part of XO ignored. ie higher Rb is better.
Hope I got it all, correctly...
Never used Spice, but, sure, will rely on your experience.
@rogloh said:
Is it safe to feed a 20MHz oscillator output directly to the XI pin on the revB P2-EVAL board with the crystal still fitted?
I did that when testing Clipped Sine (AC Coupled into XI, Xtal not removed) and that was fine for 26MHz and 38.4MHz tests.
Great, an answer. I'm hoping not to need to rework the P2-EVAL board or damage the crystal or P2. I was imagining that as that XI pad was fitted then this should be possible and Parallax would likely not have expected us to need to remove the crystal.
I am planning to use a Si5351 clock generator breakout which appears to have a 3.3V direct buffered output with 50 ohm output impedance. I will set it to 20MHz and feed one of its 3 outputs into the XI pin.
We have those if you want them Roger. OzProp has working code for them too, it may be P1 or P1V code but wouldn't take long to convert. There's a but of stuffing around to go from a target frequency to getting the right data to load in the registers
Never used Spice, but, sure, will rely on your experience.
I just ran Spice to check the 20MHz really did not make it thru to the Tri-state ENABLE pin, in any significant way.
It says rise time is about 900ns, as those large base resistors make things nice and slow. 20MHz is at ripple levels.
@Tubular , Thanks yeah it could be useful to try out in the short term to prove the whole approach works with the crystal in parallel with the Si531 output. I'll probably also order one in the meantime anyway.
All this is because I hope to build a breakout with high speed SRAM fitted just to test my memory driver at rated speed. LOL. I'll make it connect to P24-P31 for data, P32-P55 for address & control, and sit inside the P2-EVAL footprint instead of outside it to keep the trace lengths short. But I need high speed P28-P31 activity to not mess up the PLL. Hence this clock oscillator.
I'll probably layout a 8x10cm double sided board in two halves. Half designed for some high speed SRAM and half for a SDRAM footprint (for potential future use). We can flip the board around to attach the other memory type or cut it in two. It'll be a simple board with just direct traces to the header pins and a few bypass caps on the power lines. I might add a second clamshell footprint on the reverse side to test dual device banking too with a second CS pin or something. I think these TSSOP based memories are pinned out for doing that.
I just ran Spice to check the 20MHz really did not make it thru to the Tri-state ENABLE pin, in any significant way.
It says rise time is about 900ns, as those large base resistors make things nice and slow. 20MHz is at ripple levels.
Much thanks for today's "new lesson learned" opportunity!
@rogloh said:
Is it safe to feed a 20MHz oscillator output directly to the XI pin on the revB P2-EVAL board with the crystal still fitted?
I did that when testing Clipped Sine (AC Coupled into XI, Xtal not removed) and that was fine for 26MHz and 38.4MHz tests.
Was that with CC=%00, or some other option?
CC= %01, as the %00 mode shuts down everything and XI and buffer is disabled too.
%01 enables Rf, & amplifier and buffer, but uses minimal CL, which does not load the Clipped Sine much.
I guess having XO enabled with the XI as an external clock (CC=%01) is handy if you wanted to probe the frequency on that pin without loading the input.
Comments
Now you've asked the question, I think that'll be okay. It'll presuambly load the signal a little compared to no crystal.
HUBSET #%00_10should do the job. Docs say XO is floating.P2 docs V35 states that XI will be ignored, when %CC = %00, thus it'll not work this way.
In order to configure XI as an input, the way the %CC-bits works will simultaneouslly turn on XO, so the crystal can't be "effectivelly removed" or "partly floated" from the XI/XO circuitry, keeping it in series, "compressed" between these two pins.
The "least-collateral-damage" consequence would be an annoying beat (too much construtive/destructive interference), between the external oscillator frequency, and the one that is characteristic to the crystal. This would mess everything timing-related, within P2 internal circuitry, as soon as XI input is enabled.
The "worst" would be destructing the crystal, due to excess power dissipation, or the external oscillator, or both, and praying to don't also affect XO's output-buffer, at all.
That can't be right. In the %SS == %10 clock source of XI it explicitly refers to %CC != %00 needing a crystal stabilising time. Implying there is also a valid use of %CC == %00.
The docs need fixed to say XI is always an input.
Sorry, but I'm interpreting doc's statement "CC != %00" as "anything, but zero", meaning either of the other three options are valid, except CC = %00. That "fpga-jargon" is too much painfull, sometimes...
Hehe, I didn't read past the first sentence. PLL will work with that too of course. so
HUBSET ##%...._00_11should work just as well as#%00_10will.You're absolutely right. I feel the docs are wrong though. It only makes sense for %CC=%00 to be an input on XI. That mode would be useless if XI not an input.
Put it this way. The other three options are all for directly driving a crystal. It makes sense to have the fourth option for an alternative external oscillator source.
During one of the former meetings, Chip did said that activating XI also enables XO output buffer, but it would stay inactive when CC = %00, so I understood it as an acknowledgement of the correctness of %CC function table.
That was the reason of my suggestion of using the activation of XO as a way to craft a suitable control over the (active-high) INH-pin of the 20 MHz Kyocera clock oscillator that was innitially intended to be used, so as to spare 3.3V regulator from feeding as much power to the external oscillator, targetting a energy-conscious design.
Perhaps, there lies the reason of any confusion.
I wouldn't call it a confusion. It needs proven. Simple as that.
My reading is that the %00 case disables the feedback resistor Rf and disables the XI-XO buffer, so that the Amplifier and buffer are put to sleep.
The external Oscillator mode, is %01 which has added CL=0pf, but that modes does enable Rf and the XI-XO buffer.
Has anyone tried such stealth connection of XO as a Osc enable ?
It's not completely clear what XO pin does when disabled at %00, my guess is it floats, and becomes ~50% Vcc when enabled (from the !XI signal).
Most OSC need Pin 1 < 0.3Vcc to disable them, and > 0.7Vcc or floating to enable which makes XO-disable backwards.
A RET (100k?) PNP transistor between XO and Pin1 might give enough flip and filter to use that stealth XO as an enable, for deep power down uses.
The better newer oscillators are way better than the older ones, I've measured ~1.5mA at 48MHz and low CL, so the power saving are possible, but not many mA.
Checking a Yangxing lcsc.C669070 YSO110TR, 47k or 100k pulldown shuts down
I did that when testing Clipped Sine (AC Coupled into XI, Xtal not removed) and that was fine for 26MHz and 38.4MHz tests.
Yeah, XO floats when %CC = %00, so a high-ohmic value resistor (~100 kOhm) pulling the pin to V2831 would be enough to ensure it'll stay quiet, until enabled by the execution of a suitable hubset instruction.
Another resistor of about the same value, now pulling XI to the same Vio, will ensure XO being forced Low, as soon as any other mode, different from %00, is programmed at %CC by a hubset instruction.
I'm an "old school-addicted", thus I suggested the use of a SN74LVC1G123 monostable multivibrator, in this case, with both !A and B triggers connected to XO, while !CLR can be pulled high to the Vio node, thru a ~50 kOhm resistor.
This way, when XO does innitially falls-down, and subsequently, at any other transition on that pin, the Q output of the 123 will be issuing a continuous High level, suitable to drive the INH pin into a High state, keeping the oscillator enabled, untill any of the following events does occur:
The proposed IC package can be as small as ~2 x 1 mm, and priced in the range of US$ 0.20, in 1k quantities; the other six eight components (four five resistors and two three ceramic capacitors) would be cheap too, and the small area occupyed at the pcb will not be much of a concern, at all.
Addendum: 1 image = 1k words...
That's a large BOM and too many parts for Edge.
I think you can do it with just one component, eg PUMD12 or MUN5313DW1 or == RET (47k or 100k bias R1==R2, or maybe PUMD16^ R1 = 22 k, R2 = 47 k ?)
^ Spice suggests the slightly lower threshold of PUMD16 gives better margin, and the lower Rb is still ok with 20MHz, still plenty of LPF action.
The PNP-B is connected to XO and the NPN-B connects to PNP-C and pull down Osc.Pin1. (NPN-C is unused, that part is just a zero-BOM resistor..)
XO floats means PNP is off and NPN-B pulls down disabling (tri-state) OSC, and XO active, means PNP is ON, pulling Pin1 HI enables OSC.
Higher base resistors mean lower power, and slow things down as you want the AC part of XO ignored. ie higher Rb is better.
For the enable to work, XO needs to be 50% or 0% of Vcc, so the TS/Enable pin needs to either float, or force hi & the ones I've checked do work that way.
Great, an answer.
I'm hoping not to need to rework the P2-EVAL board or damage the crystal or P2. I was imagining that as that XI pad was fitted then this should be possible and Parallax would likely not have expected us to need to remove the crystal.
I am planning to use a Si5351 clock generator breakout which appears to have a 3.3V direct buffered output with 50 ohm output impedance. I will set it to 20MHz and feed one of its 3 outputs into the XI pin.
Silicon labs has a msop10 variant that allows two sources (crystal + external clock in). This allows to use clock sources from external modules (like USB ft232h synchronous 60MHz clock for 48MB/s data transfers). -> Si5350C-B-GT
Could be a good compromise between small space footprint, number of input sources, hand solderability. There are other far more capable (like stratum 3 or better) but they are high pin count in QFN package.
I don't think the MSOP version of the Si5350C, includes i2c support, which makes it less generally useful.
You can feed an external clock into Si5351A.MSOP10 with a series element.
In my case I only need something simple, so will probably get this
https://learn.adafruit.com/adafruit-si5351-clock-generator-breakout/pinouts
and mate it to the smaller P2-EVAL proto board for plugging into P56-P63 on the P2-EVAL That's a useful place for it because these 2 pins (56,57) are otherwise wasted (unless you need them for LEDs, or you wanted to plug in the wireless board on the revC). A bonus with that Adafruit board is that it has a regulator that can be powered with 5V or 3.3V so I can flip the breakout 180 degrees to face inwards and keep the clock wire short or flip it back to face outwards and access SMA clock outputs for other purposes.
If this approach works there's probably scope for someone to create a more versatile I2C controlled clock board for people to experiment with different timing applications or options with the P2. A clock input could be good then.
That Adafruit board is nice.
P2D2 uses the Si5351A, and you can AC couple a clipped sine oscillator into the XA pin.
SiLabs have released a QFN16 option but that is not showing stocked anywhere yet. (the MSOP package has worse jitter on paper than the QFN packages)
Hope I got it all, correctly...
Never used Spice, but, sure, will rely on your experience.
We have those if you want them Roger. OzProp has working code for them too, it may be P1 or P1V code but wouldn't take long to convert. There's a but of stuffing around to go from a target frequency to getting the right data to load in the registers
Yup, 100% correct.
I just ran Spice to check the 20MHz really did not make it thru to the Tri-state ENABLE pin, in any significant way.
It says rise time is about 900ns, as those large base resistors make things nice and slow. 20MHz is at ripple levels.
@Tubular , Thanks yeah it could be useful to try out in the short term to prove the whole approach works with the crystal in parallel with the Si531 output. I'll probably also order one in the meantime anyway.
All this is because I hope to build a breakout with high speed SRAM fitted just to test my memory driver at rated speed. LOL. I'll make it connect to P24-P31 for data, P32-P55 for address & control, and sit inside the P2-EVAL footprint instead of outside it to keep the trace lengths short. But I need high speed P28-P31 activity to not mess up the PLL. Hence this clock oscillator.
I'll probably layout a 8x10cm double sided board in two halves. Half designed for some high speed SRAM and half for a SDRAM footprint (for potential future use). We can flip the board around to attach the other memory type or cut it in two. It'll be a simple board with just direct traces to the header pins and a few bypass caps on the power lines. I might add a second clamshell footprint on the reverse side to test dual device banking too with a second CS pin or something. I think these TSSOP based memories are pinned out for doing that.
Much thanks for today's "new lesson learned" opportunity!
Was that with CC=%00, or some other option?
CC= %01, as the %00 mode shuts down everything and XI and buffer is disabled too.
%01 enables Rf, & amplifier and buffer, but uses minimal CL, which does not load the Clipped Sine much.
I guess having XO enabled with the XI as an external clock (CC=%01) is handy if you wanted to probe the frequency on that pin without loading the input.
Jmg, thanks!!
This is a perfect solution to the problem we have. Keeps quiescent current lows during reset and provides a super-sharp edge for XI.