How to kill a P2 video driver (and probably USB etc)...
rogloh
Posts: 5,158
...in one easy step. Call this from a COG with some video driver already running:
PUB killpll() | pllpins
pllpins := 28 addpins 3
org
rep #1, #0
drvrnd pllpins
end
It works by generating lots of transitions on P28-31 that triggers massive P2 PLL jitter when the PLL is not setup as simple multiples of 10, 20MHz etc, some rates are better than others. If you are running video you will see a lot of distortion in your output or the monitor may not even sync.
Kills video when operating at 252MHz, 297MHz, 325MHz etc on a few P2-EVAL boards I tried. No permanent damage I've seen, it just affects the output during these noisy high speed transitions. When these stop the system recovers.
I found other operating P2 frequencies of 20, 40,..., 200MHz and 240MHz etc were immune from the problem. The PLL seems less sensitive there for some of these simpler multipliers. It would be good to identify all the "safe" frequencies. You can also monitor for jitter and observe it directly with a pin in NCO output mode hooked to a scope too. The signal jumps all over the place once it is triggered.
This problem was discovered yesterday when I was putting together a PSRAM memory driver using these pins and observed video distortion, then today Tubular, ozpropdev and I got together and finally narrowed it down to high frequencies on these pins triggering noise into the PLL of the chip because it shares the same VIO supply pin for this nibble. So it's best to avoid using these particular pins for high frequencies if you want a stable PLL.
Comments
Suck. Presume the edges are the killer. Lower drive strength should help.
Yeah I think it is probably HF sharp edges, I also ran DAC random noise mode on these pins at 3.3V swing but it didn't happen. Needed to drive hard transitions.
By the way it was actually high speed PSRAM read data input coming into the chip that caused this, but P2 output can do it too. That's how I finally proved it definitively in isolation. So avoid using these pins for high speed data. Simple things like a chip select is okay - the HyperRAM breakout board is okay fitted on P16-P31 because the high speed data is not on these upper pins, but the PSRAM board used them. A stronger or more bypass caps fitted on VIO_28_31 may possibly help.
Did you observe this too evanh?
I don't imagine its a good idea to drive video out these pins either, will go check the DVI board fitted there. Thankfully the A/V doesn't put video on these pins...just audio data.
Update: DVI board on these P24-31 pins seems okay, at 252MHz anyway.
No, I hadn't pick up on this specifically. It just made a lot of sense the moment I read your post. I've been wary of using these pins externally ever since killing a prop2 so easily on them.
The DAC outputs should be fine. They're a much smoother power draw. And aren't the DVI pins using the 1500 ohm drive strength?
Yeah DVI is using a custom pin setting here...
Less swing.
So it looks like most the Parallax breakouts that exist today seem to be okay on these pins. Didn't try Goetzel on it though - in case that gets driven at HF on its top common bit. I've not played with that one.
Anyone making a their own network interface breakout board like RMII might be best to steer clear of these particular pins for data/clocks as well as for any high speed SD card use in SD mode perhaps. Just use the bottom half of the byte for data (that is good for the streamer too).
Inside the chip, there is a lot of filtering for the PLL power. I am suspecting that the Jitter is originating on the XI pin, and not from within the PLL. I will do a test today to see if this is true.
Driving 20MHz directly into XI, as opposed to using the crystal and the inverter, might overcome this problem.
Just tried PLL at 100 MHz with fast drive and got large jitter.
RCFAST is clean and no change between fast drive and no drive.
XTAL direct without the PLL is clean and no change between fast drive and no drive.
And guess what? 20 MHz PLL is also clean and no change between fast drive and no drive.
The big difference between the 100 MHz and the 20 MHz is the %PPPP setting. So when I then use 200 / 2 MHz, voila! it's all clean at 100 MHz too.
Err, no, Roger's got it right. 190 / 2 fails as well.
RCFAST does have a little jitter but that's normal. It's the same amount with or without the pins driven.
Could it be that VIO needs a bigger cap or more power?
I've been checking this and it has to do with phase noise and/or multiple threshold crossings on XI, not the PLL.
If you feed an external 20MHz into XI, the problem goes away.
The PLL actually runs off an internally-regulated 1.8V power supply that is derived from V2831. It is heavily filtered.
Anyway, this jitter is coming in from the XI pin as phase noise and maybe even multiple crossings, as the slow crystal inverter slews past the logic transition threshold. If enough pins in the P28..P31 block are toggling fast at full strength, it can trigger this problem.
Von Sarvas and I have been going over this for the last few hours and we've decided to just start using an oscillator, instead of a crystal. If you can keep multiple aggressive signals out of that 4-pin P28..P31 group, your design will have no problem, but this is a strange thing to have to warn people about, so we will start using 20MHz oscillators on the P2 Edge.
We are planning to use this oscillator from Kyocera: MC2520Z20.0000C19XSH
https://www.digikey.com/en/products/detail/kyocera-international-inc-electronic-components/MC2520Z20-0000C19XSH/11610203?s=N4IgTCBcDaILIGEwFYwAYBa6B0a9oQEYBOADQGUAJEAXQF8g
There was talk about using a schmitt buffer in the Xtal chain, back when P2 was being designed....
That's not really cheap, nor low power, nor low ppm ?
Digging, here are my Osc test results for some lcsc part codes, measured Icc and measured Oscillator startup.
As you can see, there is quite some variation in Icc and startup, on 'standard oscillators', with the better ones having lower Icc and faster startup.
~~~~~~~~~~~~~~~ test results 48MHz Std CMOS Oscillators below ~~~~~~~~~~~~~~~~~~~~ LCSC Price Ctr.MHz I@CL=0 Icc@8pF Ctr.Err Spec? Tsu Ctr CAL CHECK: 1pps is 1.0000031/27/44 or reads ~+3.1/2.7/4.4ppm high EPSON C256002 43c/100 48.00048 1.5mA 2.32mA +10 ppm ±50 ppm 220us clean startup Yangxing C669070 34c/100 47.99998 1.5mA 2.13mA -0.4ppm ±10 ppm 100us YSO110TR new - nice low Icc, very clean startup. <<< confirmed as preferred OSC part JGHC C437146 32c/100 48.00014 1.9mA 2.65mA +2.9ppm ±25 ppm 150us not quite clean on leading edge Yangxing C382495 34c/100 48.00013 5.4mA 6.07mA +2.9ppm ±20 ppm 1.4ms YSO680PR 40ps jitter - appears to have higher MHz before 1.4ms lock ? SJK C668747 80c/100 48.00008 4.25mA 4.76mA +1.6ppm ±10 ppm 3.88ms clean delayThe 20MHz family version of the 48MHz Yangxing YSO110TR family, are these (2520 and 2016 package versions)
C669067 Yangxing Tech OT252020MJBA4SL 20MHz ±10ppm 1.8V~3.3V 4mA SMD-2520-4P 100+$0.3805 488 InstockC669079 Yangxing Tech OT201620MJBA4SL 20MHz ±10ppm 1.8V~3.3V 4mA SMD-2016-4P 100+$0.4959 584 Instockand if you are allowing a OSC, these are useful user alternatives.
The clipped sine ones have best ppm, but need a series C option on the PCB.
( It may be OK to always fit the C, and use the P2 clamp diodes to 'centre' the CMOS square wave ? That allows any-osc )
You could explore two order codes, one fitted with lowest-cost-oscillator like C669067, and another part code for the TCXO ±2.5ppm CMOS output ?
It would be worthwhile to get some C669067 & ECS-TXO-2520-33-200 and run them side by side.
Octopart suggests ECS-TXO-2520 is a tad lower in price, and more stocked than ASTX-H12. I've seen good comments on the ASTX-H12 on the net, re smooth correction, whilst the ECS-TXO-2520 is a bit newer
Also showing is ECS-TXO-2016-33-200, bit lower price but not well stocked. I usually make a PCB OSC footprint to accept both 2520 and 2016 parts.
Chip: If you decide to change this part, is there any chance you could make the footprint of whatever osc you use also support a precision, very-low PPM, higher $$$ part? Or maybe have a staggered (dual) footprint? I have hit a couple of situations where I’d happily pay the extra money for a higher spec oscillator (and even risk the potential reflow mischief) if the board had supported it.
Btw: if you are going to do a board revision anyway, howzabout adding a RTC chip?
What ppm do you need ?
In #16 above, I list CMOS osc to ±2.5ppm, and clipped sine ones to ±500ppb, and it looks like you can get to ±10 ppm as a low cost starting point.
If you need better than ±500ppb, usually the package needs to get larger than 2520.
@jmg In retrospect “need” may be a too-strong word. “Want” is probably more accurate. Anything 2 ppm or better would make me pretty happy, but honestly, if I could plop a 500 ppb chip in there for the price of some paste, flux and sweat and a credit card to Mouser, I’d do it and be done with it. “Uggggg! My timebase is too accurate!” (said nobody ever. Lol)
Hi JRoark
Here's your beloved baby:
https://abracon.com/Oscillators/AST3TQ-28.pdf
Bigger than expected, but specs are fine... If it could satisfy your needs, it rests convincig Chip and Von Szarvas to let a bigger footprint at the rev. board.
If you must buy from Mouser, you'll be wasting about 10 bucks of your money, as compared to the same part, sold by Digikey. Your money, your decision...
https://mouser.com/ProductDetail/ABRACON/AST3TQ-T-20000MHz-28?qs=YAvGbpKWXiT%2Fet4yAa0FcQ%3D%3D
https://digikey.com/en/products/detail/abracon-llc/AST3TQ-T-20-000MHZ-28/5017690
The TG2520SMN 20.0000M-MCGNNM3 part above would get you to ±500ppb, provided the PCB has a series coupling cap.
Keep in mind that the crosstalk issues in #15 might be worse with a clipped sine part, as the amplitude/slew rate is even lower than a crystal osc.
On the plus side, it is locally powered, and Zo on those parts is ~180 ohms, so would be interesting to compare clipped sine / Xtal / CMOS osc, for this pin crosstalk issue.
There is a PL133-27 which is the smallest part I've located for clipped sine to CMOS (no series cap needed!), but that is not an easy 'option-fit' part.
Jmg, thanks for these part pointers.
Yes, a Schmitt trigger would have helped this - not in the XI/XO feedback loop, but as an internal sensor. Now I understand where it needed to be.
@Yanomani Ok. I’m officially in love. Or perhaps its a serious case of lust. Either way its all good. Now to convince Chip (or I can roll my own, because I havent had a really good migraine in months!)
What matters is that the input signal to XI slews quickly across the logic threshold region, which is at ~3.3V/2.
The crystal only slews 100mV/ns. We need something about 10x faster than that. So, if you use a clipped-sine oscillator, you should run it through a Schmitt or a few series'd inverters to sharpen it up and get it full-scale before plugging it into XI.
JRoark, we are not going to have the space on the P2 Edge to support a largish oscillator. We are not opposed to using one if the price is right and it fits, though.
Just curious... Do the large, P1 type, crystals behave the same way? I.e., does crystal size matter?
The oscillator looked to add $0.50 to the BOM, if I saw it right. Not a big deal, as I see it...
Yes, inverter crystal oscillators like P2, have rail-rail sines on Xi and XO, and the xtal size does not affect that limiting amplitude.
Smaller Xtals may have a bit higher ESR and so take a bit longer to startup.
Spot on!
The 125C automotive level temperature rating is important too.
5x7 is massive these days, there are smaller ±280ppb oscillators.
eg the TX235A-D3-0.28-20.000-3-TR comes in 5032 package, as does the VCTCXO TWEAKLJANF-20.000000. Murata also have 5032 ones, but their longevity is ?
Whilst I'm not seriously advocating for any specific package, perhaps it's wise to think about using the bottom side of the board (assuming its still almost free of components), in order to provide alternative land patterns for differing sized oscillators.
Sure, a short stub will exist at the XI net, because of the via(s) connecting the two sides, but the frequency region of 20.000 MHz turns it (them) into less of a concern, when it comes to signal integrity.
Those land patterns would also need to be surrounded by GND area fills, solidy-connected to the inner GND plane by vias, in order to simullate a coaxial arrangement. That kind of GND-stitching, turning sensible inter-plane connections into "islands", is often used in several designs, at the HF-range.
Good idea. I've done designs with 2520 on top, and 5032 and 3225 on rear, and some allow for pads to connect a trimmer to the VC pin, should a VCTCXO be fitted.
That means you can correct for the reflow offsets, and have just the temperature and aging effects.
In the same path, I'm a big fan of having alternative land patterns, when it comes for any "product" that still has available/free pcb areas.
In my humble POV, one of the most important, and easier to have, is previewing means of having external oscillators connected, such as miniature SMD coaxial connectors, like the following:
https://hirose.com/en/product/document?clcode=CL0331-0472-2-01&productname=U.FL-R-SMT-1(01)&series=U.FL&documenttype=Catalog&lang=en&documentid=D31697_en
Land patterns are (almost) free, even when using ENIG finish.