Where did you see that the ARM is a separate die? It's described as an SoC.
It doesn't seem uncommon for manufacturers to use SoC and SiP interchangeably, as they often refer to the package and everything in it as a "chip". Lots of parts with "integrated" FLASH just used a separate FLASH die wire bonded to another die.
@Heater
I actually think it's a decent idea. Sure, it's a bit more complicated and involved than having a single die in a package, but it's a well-established practice and not all that uncommon. For relatively low production parts, it would appear to be cheaper all around (for the manufacturer and in turn, the customer) than investing in all the necessary R&D time and expenses as well as the production of a whole new die. Honestly, I think this method is something Parallax could benefit from. Consider this example: a P1 with no hub ram, but instead has bonding points on the die for the data and address lines. This allows bonding to various capacity SRAM die in the package which is a lot cheaper than producing a P1 with various ram capacities on-die (which might not even be possible given the node used and the already large die size of the existing chip). Since the P1 isn't particularly cheap anyway, and is often used in low-volume high margin products, the increased cost is unlikely to be a deal breaker and in fact might help grab a bit more market where its 32K ram is too small (and SPI SRAM too slow/inconvenient). While you're at it, you can also throw in some FLASH
Perhaps it not such a bad idea. It's just that my idea of an ARM and a XMOS is an ARM and an XMOS. Something that will run a full up Linux OS. What would be really cool is if the ARM SoC supported native XMOS XLINK connections. Just a few wires needed to add all that real-time goodness to your ARM boards.
Perhaps it not such a bad idea. It's just that my idea of an ARM and a XMOS is an ARM and an XMOS. Something that will run a full up Linux OS. What would be really cool is if the ARM SoC supported native XMOS XLINK connections. Just a few wires needed to add all that real-time goodness to your ARM boards.
Linking to higher-hosts is an interst8ng question, not just for XMOS but also P2.
I doubt a large MPU vendor is going to include a niche link, but there are signs of interesting standards/ choices.
TI has a parallel DDR bus they call uPP which sounds similar to Spansion's Hyperbus, but not focused on Memory. TI intends for FPGA and ADC connections.
TI's uPP also comes on their OMAP-L138, which is a ARM9 MPU with DSP Co-processor.
That could pair well with a P2 ?
If you want an extremely high-bandwidth link to an applications processor, wouldn't you pretty much be limited to something that communicates over the said CPU's memory bus (not unlike the microcomputer designs of yore)? So basically an interface that appears as ram to the CPU. Perhaps a little bit of dual port hub ram which the interface can R/W to.
So has anybody heard anything about the P2 release date and price? Any news about the 1-2-3 FPGA board? How is the FPGA work going? How about the P2 layout work being done by OnSemi? Parallax has been extremely quite these days. Can someone that lives near the Parallax headquarters please drive over there to see if the lights are still on?
Can someone that lives near the Parallax headquarters please drive over there to see if the lights are still on?
@Dave: I'm guessing that they're burning the midnight oil over at Parallax. One might not be able to see it by looking in the windows, though, as most of the work happens down in the dungeon.
But I think I've discovered why there hasn't been an update this week: I believe it's because you never posted a final text-based count-down calendar over on Chip's main thread. Without your post, they probably were working so hard that they didn't notice that summer has come.
@Dave: I'm guessing that they're burning the midnight oil over at Parallax. One might not be able to see it by looking in the windows, though, as most of the work happens down in the dungeon.
But I think I've discovered why there hasn't been an update this week: I believe it's because you never posted a final text-based count-down calendar over on Chip's main thread. Without your post, they probably were working so hard that they didn't notice that summer has come.
Maybe they meant that it would be ready by the end of spring in the southern hemisphere. Isn't that still 6 months off? :-)
...But I think I've discovered why there hasn't been an update this week: I believe it's because you never posted a final text-based count-down calendar over on Chip's main thread. Without your post, they probably were working so hard that they didn't notice that summer has come.
I was so busy on Sunday I never got around to posting a P2 watch message. Sunday was also Father's day, and my kids made me breakfast and took me to a snake farm and a car museum. The snake farm was a place that I've passed on the highway many times, and I always joked that I would like to see it. It was actually quite interesting. I also liked the car museum. It had many nicely restored cars from the early 1900's to the 1950's.
If Parallax ain't saying nothing about a release date or giving a status update, you can bet money Chip either hit a nasty snag of some sort or he vastly under estimated how much time it would take. If it wasn't the case, there would be posting indicating success.
Do people not realise Ken is out and about touting Parallax wares and he's probably left Chip locked in the cellar working until he gets back to release him.
Sunday was also Father's day, and my kids made me breakfast and took me to a snake farm and a car museum.
Snake farm and car museum with the kids vs. dinking around here on the forum with us: that was a tough call but I believe that you made the right choice.
Maybe they meant that it would be ready by the end of spring in the southern hemisphere. Isn't that still 6 months off? :-)
Yeah, I never felt that the end-of-spring was a firm deadline (though I hoped). On the other hand, I doubt that Ken intends for those 1-2-3 boards to sit around gathering dust for 6 months.
In the old days, everything was memory mapped, but today the OMAP above, and RPi level MPUs have DDR memory on the main memory bus - and that is not easy to tap into, and consumes a lot of pins.
Hence the drive for additional lower-pin-cost interfaces, that use techniques like Double edge clocking borrowed from SDRAM.
It would be a big challenge. The timings associated modern ram is so tight and places very tough constraints on board layout, sure, but this is true of any high-speed interface. The one thing I'd like to point out is that a full-width interface via a dram bus wouldn't be necessary, at least not on the address lines, and possibly not on the data lines either, so pin requirements could be reduced.
Keep in mind that on these app processors, part of the addressing is for ram CS. The biggest drawback is on the app processor side where the device would need to replace one of the potentially addressable memory chips. For processors which could address 4 chips, max ram capacity would be reduced by 25%, and processors which can only address 2, max ram is reduced by 50%.
Now, I'm not saying this is the ideal interface as it's sort of a kludge, but it is one that all these chips have, and it is FAST and well established. A big problem is longevity, though, especially for a device that intends to have a long production run. DDR2 is still common.... for now. However, high-end parts are already using DDR3 and it's probably just a matter of time before that trickles down to lower parts, and that will just continue. But we can assume any other high performance bus will be deprecated with time, if any will even gain traction.
Now that I think of it, maybe it would be possible to interface with an eMMC bus instead. It's a 10 signal DDR bus for NAND memory with integrated controller which more and more app processors use (including some of the intel Atom SoCs used on really low-end laptops). Naturally, it's slower than ram, but in our case that's quite a good thing. Even so, it's still quite fast: 8-bit wide bus @ up to 52MHz DDR for 832Mbit/sec throughput. At the very least, this can probably be implemented in software, and the clock rate can actually be lower than 52MHz. There is a slight snag, however: only one addressable slave allowed on the bus. The possible workaround is based on the fact that the clock to a slave can be disabled to reduce power consumption when not in use, so there may be the potential to mux the clock between the eMMC chip and the Prop, acting as a quasi chip select (this is all assuming the eMMC dat lines go hi-z - haven't looked into it).
My message has raised concerns from Parallax. My criticism is being
seen as an attack on the company and not as constructive, so I'm retracting the entire message in addition to all of my recent
posts.<br><br><span style="text-decoration: line-through;">Crazy thought: Release the FPGA code for the Prop2 as free for personal use and license it for commercial / educational usage. You could bypass the current pain of one man desperately trying to keep up with changing technology in the chip design, forgo the costs involved and get the project to market now before the whole concept becomes too dated to be relevant. Parallax has a good hold in the educational market with all of the supporting materials, etc that they currently create. Releasing the project in FPGA as free for personal use allows Parallax to regain user support and code which has dropped off as well as license the product for commercial use. Make the license something that has to be registered for and embed the license holder's information in the code. Parallax will be able to just start into new boards and products that take advantage of this new design now. (well at least eight months from now, given Parallax's development history.)
Otherwise, we'll be looking at at least two more years until the product has enough traction to do what the Propeller can now. In my thinking, that will be too late.
Parallax (noun) : the effect whereby the position or direction of an object appears to differ when viewed from different positions.
I'd suggest that it might be time to consider another alternative to pressing the design into silicon. Crazy thought: Release the FPGA code for the Prop2....
??
That already is the plan, the FPGA testing is certainly going to be done before "pressing the design into silicon"
The $149 FPGA board can host P2, and Altera have expanded the WEB Software support - so as well as the already designed Parallax 1-2-3 FPGA board, there are other alternatives that can run P2 builds.
It may make sense to offer both Parallax 1-2-3, and an adapter board on the BeMicro-CV-A9.
Has anyone emailed Ken directly, asking about progress on the P2? It would seem to be the logical thing to do, although he must have read the comments here.
The P1 took us completely by surprise, and it was a pleasant one, to say the least. Instead of getting your collective knickers in a twist waiting for the second coming, why not just chill? The expectation anxiety rampant here is sheer idiocy! The P2 will come when -- and if -- it comes. Get a life!
Comments
It doesn't seem uncommon for manufacturers to use SoC and SiP interchangeably, as they often refer to the package and everything in it as a "chip". Lots of parts with "integrated" FLASH just used a separate FLASH die wire bonded to another die.
@Heater
I actually think it's a decent idea. Sure, it's a bit more complicated and involved than having a single die in a package, but it's a well-established practice and not all that uncommon. For relatively low production parts, it would appear to be cheaper all around (for the manufacturer and in turn, the customer) than investing in all the necessary R&D time and expenses as well as the production of a whole new die. Honestly, I think this method is something Parallax could benefit from. Consider this example: a P1 with no hub ram, but instead has bonding points on the die for the data and address lines. This allows bonding to various capacity SRAM die in the package which is a lot cheaper than producing a P1 with various ram capacities on-die (which might not even be possible given the node used and the already large die size of the existing chip). Since the P1 isn't particularly cheap anyway, and is often used in low-volume high margin products, the increased cost is unlikely to be a deal breaker and in fact might help grab a bit more market where its 32K ram is too small (and SPI SRAM too slow/inconvenient). While you're at it, you can also throw in some FLASH
An Analog Devices part I linked to a couple of days back, used three die stacked !
I wonder if XMOS do sell them. Digikey does not list an XA parts even if they do have the xCORE-XA dev board.
Linking to higher-hosts is an interst8ng question, not just for XMOS but also P2.
I doubt a large MPU vendor is going to include a niche link, but there are signs of interesting standards/ choices.
TI has a parallel DDR bus they call uPP which sounds similar to Spansion's Hyperbus, but not focused on Memory. TI intends for FPGA and ADC connections.
TI's uPP also comes on their OMAP-L138, which is a ARM9 MPU with DSP Co-processor.
That could pair well with a P2 ?
@Dave: I'm guessing that they're burning the midnight oil over at Parallax. One might not be able to see it by looking in the windows, though, as most of the work happens down in the dungeon.
But I think I've discovered why there hasn't been an update this week: I believe it's because you never posted a final text-based count-down calendar over on Chip's main thread. Without your post, they probably were working so hard that they didn't notice that summer has come.
-Phil
Too MUCH water and it will be a rough hoe to row!
.
Snake farm and car museum with the kids vs. dinking around here on the forum with us: that was a tough call but I believe that you made the right choice.
Yeah, I never felt that the end-of-spring was a firm deadline (though I hoped). On the other hand, I doubt that Ken intends for those 1-2-3 boards to sit around gathering dust for 6 months.
It would be a big challenge. The timings associated modern ram is so tight and places very tough constraints on board layout, sure, but this is true of any high-speed interface. The one thing I'd like to point out is that a full-width interface via a dram bus wouldn't be necessary, at least not on the address lines, and possibly not on the data lines either, so pin requirements could be reduced.
Keep in mind that on these app processors, part of the addressing is for ram CS. The biggest drawback is on the app processor side where the device would need to replace one of the potentially addressable memory chips. For processors which could address 4 chips, max ram capacity would be reduced by 25%, and processors which can only address 2, max ram is reduced by 50%.
Now, I'm not saying this is the ideal interface as it's sort of a kludge, but it is one that all these chips have, and it is FAST and well established. A big problem is longevity, though, especially for a device that intends to have a long production run. DDR2 is still common.... for now. However, high-end parts are already using DDR3 and it's probably just a matter of time before that trickles down to lower parts, and that will just continue. But we can assume any other high performance bus will be deprecated with time, if any will even gain traction.
Now that I think of it, maybe it would be possible to interface with an eMMC bus instead. It's a 10 signal DDR bus for NAND memory with integrated controller which more and more app processors use (including some of the intel Atom SoCs used on really low-end laptops). Naturally, it's slower than ram, but in our case that's quite a good thing. Even so, it's still quite fast: 8-bit wide bus @ up to 52MHz DDR for 832Mbit/sec throughput. At the very least, this can probably be implemented in software, and the clock rate can actually be lower than 52MHz. There is a slight snag, however: only one addressable slave allowed on the bus. The possible workaround is based on the fact that the clock to a slave can be disabled to reduce power consumption when not in use, so there may be the potential to mux the clock between the eMMC chip and the Prop, acting as a quasi chip select (this is all assuming the eMMC dat lines go hi-z - haven't looked into it).
Just some thoughts
seen as an attack on the company and not as constructive, so I'm retracting the entire message in addition to all of my recent
posts.<br><br><span style="text-decoration: line-through;">Crazy thought: Release the FPGA code for the Prop2 as free for personal use and license it for commercial / educational usage. You could bypass the current pain of one man desperately trying to keep up with changing technology in the chip design, forgo the costs involved and get the project to market now before the whole concept becomes too dated to be relevant. Parallax has a good hold in the educational market with all of the supporting materials, etc that they currently create. Releasing the project in FPGA as free for personal use allows Parallax to regain user support and code which has dropped off as well as license the product for commercial use. Make the license something that has to be registered for and embed the license holder's information in the code. Parallax will be able to just start into new boards and products that take advantage of this new design now. (well at least eight months from now, given Parallax's development history.)
Otherwise, we'll be looking at at least two more years until the product has enough traction to do what the Propeller can now. In my thinking, that will be too late.
Parallax (noun) : the effect whereby the position or direction of an object appears to differ when viewed from different positions.
It's past time.</span>
Did my mind wonder from the P2 for a minute?
??
That already is the plan, the FPGA testing is certainly going to be done before "pressing the design into silicon"
See also this thread
http://forums.parallax.com/showthread.php/157782-BeMicro-CV-A9-301.000K-LE
The $149 FPGA board can host P2, and Altera have expanded the WEB Software support - so as well as the already designed Parallax 1-2-3 FPGA board, there are other alternatives that can run P2 builds.
It may make sense to offer both Parallax 1-2-3, and an adapter board on the BeMicro-CV-A9.
The P1 took us completely by surprise, and it was a pleasant one, to say the least. Instead of getting your collective knickers in a twist waiting for the second coming, why not just chill? The expectation anxiety rampant here is sheer idiocy! The P2 will come when -- and if -- it comes. Get a life!
-Phil