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Prop-2 Release Date and Price

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  • Dave HeinDave Hein Posts: 6,347
    edited 2015-06-22 15:00
    I didn't say anything about attracting a much larger customer base. My numbers assume that Parallax would have no growth, and continue with their current revenue and number of employees. From what I can tell Parallax has had about the same number of employees for the past 5 years, which implies that they have not grown in the past few years. Since they are a private company there's know way for us to know whether their revenue is staying the same, or possibly shrinking over the past few years. However, I think that without the P2 their future doesn't look good. That's why I think they need the P2 ASAP just to keep from contracting.
  • David BetzDavid Betz Posts: 14,487
    edited 2015-06-22 15:22
    Dave Hein wrote: »
    I didn't say anything about attracting a much larger customer base. My numbers assume that Parallax would have no growth, and continue with their current revenue and number of employees. From what I can tell Parallax has had about the same number of employees for the past 5 years, which implies that they have not grown in the past few years. Since they are a private company there's know way for us to know whether their revenue is staying the same, or possibly shrinking over the past few years. However, I think that without the P2 their future doesn't look good. That's why I think they need the P2 ASAP just to keep from contracting.
    Could be true. It's all guess work at this point. I wish them well and don't pretend to know what advice to give them to increase the chances that will come about. I'm as curious as anyone about what Chip will come up with. I just hope it isn't bogged down too much by attempts to implement any of my hair-brained ideas.
  • Heater.Heater. Posts: 21,230
    edited 2015-06-22 16:17
    The annual MCU market seems to stand at around 18 billion dollars just now. http://electronicspurchasingstrategies.com/2014/08/14/microcontroller-market-rebounds-2014/
    And about 23 billion units shipped.

    The scary thing about that is the average revenue per device. About 80 cents! The 32 bit devices seem to go for a bit more than a dollar each.

    So, yeah, my 0.00001% would only be about 2000 devices which does not sound so good. But hey, it was just a figure of speech anyway.

    Make your own guesstimates as to how much of that Pie they can get.
  • potatoheadpotatohead Posts: 10,242
    edited 2015-06-22 17:43
    It is both how many and what people will pay.
  • David BetzDavid Betz Posts: 14,487
    edited 2015-06-22 17:46
    potatohead wrote: »
    It is both how many and what people will pay.
    It will certainly be a unique device so people may be willing to pay more for it than they would a run-of-the-mill ARM chip.
  • bruceebrucee Posts: 238
    edited 2015-06-22 18:27
    Now we get into the marketing Ouija board stuff. The trend in the industry among the major vendors is to come out with a replacement part a year later that has some more features and costs a bit less. The trick then in to not eat too much into the original business, but often that is not an issue as no one redoes an old product just to save a few cents. They will look at the new part for a next generation product. Some companies do a good job of maintaining code compatibility between versions, then others seem to care less.

    How does the P2 fit here? My guess would be if it comes out more expensive than the P1 it won't sell as many as the P1, but with the die size I seem to remember being mentioned I don't see how it would be cheaper.

    I have to rank among the unbelievers as I don't see any scenario where Parallax gets its investment back, that was 4M according to Ken a year or more ago. The real answer would be, who were the major users of the P1 and what do they want.
  • jmgjmg Posts: 14,979
    edited 2015-06-22 18:50
    brucee wrote: »
    How does the P2 fit here?

    On a Generic silicon yardstick, the P2 will never rank highly, but that misses the point.

    The question comes down to Applications, and where a P2 can solve a problem that would have used a MCU and a FPGA, (or some highly niche MCU).

    There are quite a lot of control and instrumentation and factory automation type apps where a P2 can sit quite comfortably.
    The P2 may even hit a higher volume niche in Motor Control, as it would seem quite well suited to that.
    Programmable Logic Control may be another potential area - volumes are good at the mass end, but the P2 Price may push it one tier up from that.

    There seems to be enough volumes in even small niche areas, as I see companies making custom 4~20mA ICs and HART drivers. In both cases the volumes must be only modest, but the prices are not low, so clearly customers will pay for convenience.
    brucee wrote: »
    My guess would be if it comes out more expensive than the P1 it won't sell as many as the P1, but with the die size I seem to remember being mentioned I don't see how it would be cheaper.
    ? The P2 can do a lot more than P1, so it does not need to cost less.
    Given the die area and testing costs, R&D & recovery costs, it is unlikely to be even close to P1 in price.

    Many vendors release quite expensive silicon, so they clearly expect enough customers willing to pay that level.

    Here is another niche example
    http://www.analog.com/en/products/processors-dsp/analog-microcontrollers/arm-cortex-m3-processor/aducm310.html#product-overview

    At first glance, this looks nothing special, but the price is certainly high @ $32.53 /1000+ (!)
    More reading shows this is a stacked die part with 3 die, and some impressive analog support sections..
  • jmgjmg Posts: 14,979
    edited 2015-06-22 22:04
    ARM boards are not quite the right comparison points, so here is a topical example that is perhaps more P2 relevant

    ["Today, on the fifth anniversary of its first LaunchPad development kit, Texas Instruments (TI) (NASDAQ: TXN) announced the low-cost C2000™ Delfino™ F28377S microcontroller (MCU) LaunchPad development kit, the first LaunchPad for the Delfino line of MCU. Based on TI's C2000 Delfino F28377S MCU, the LaunchPad offers 200 MHz of 32-bit floating-point performance, newly integrated accelerators, as well as high-integrity analog and control peripherals for $29.99."]
    http://www.ti.com/tool/LAUNCHXL-F28377S

    ["The LaunchPad is based on the Delfino TMS320F28377S MCU which provides 400MIPS of total system performance between a 200MHz C28x CPU and a 200MHz real-time control co-processor (CLA). This powerful microcontroller contains [B]1MB of on-board flash[/B] and includes highly differentiated peripherals such as 12bit ADCs, comparators, DACs, delta-sigma sinc filters, HRPWMs, eCAPs, eQEPs, CANs, and more."]

    TI indicated the Chip alone is from $14.02 @ 1ku for the 'relaxed' -40'C to 105'C spec
    ( will the P2 get below this ? - where can it out-spec this ? )

    $29.99 is a good price for a EVB with isolated Debug included.

    The block diagram
    http://www.ti.com/general/docs/datasheetdiagram.tsp?genericPartNumber=TMS320F28377S&diagramId=SPRS881A
    includes USB not in their peripheral list above.

    Also mentioned is "12-Pin 3.3 V-Compatible Universal Parallel Port (uPP) Interface"
    http://processors.wiki.ti.com/index.php/Introduction_to_uPP
    which sounds similar to the Hyperbus but designed for peripherals rather than memory.
  • potatoheadpotatohead Posts: 10,242
    edited 2015-06-22 23:20
    Good posts jmg.

    I have thoughts along similar lines. The P2, as we know it right now, is going to be highly differentiated. That's generally worth some $$$, but only to those who see value in the features / workflows associated with the device.

    This is worth some additional comment:
    Sometimes customers will pay for convenience.

    Yes, indeed. A whole lot of us jumped on P1 for that exact reason. Yes, it's a playground of sorts, but really the core features actually do matter and actually are worth something. The whole no interrupts thing is controversial, but the reality is being able to mix 'n match code is generally easy, and that can be worth a lot to people. As for margins, BOM cost, and so on, it's really important to not get into other people's pockets.

    What I mean by that is it's very important to ask for ALL the value on the table. That's not going to be the best, cheap no brainer deal at first, if ever. But it's up to the buyer to make it work on their end, and if they see the value, they will make it work. This is not to say it's important to rip people off, or overcharge. That's crappy. But pricing well to capture value in the product makes a lot of sense, and when it's done right early on, that margin funds the savings for everyone later on, and the next product too. Great ecosystems happen this way. In a very real sense, we do get what we pay for, and that means pricing warrants a lot of planning and attention and value education early on or it might just be all left on the table, potential never actualized.

    I just heard an interview with the Parallelea CEO / Founder on "The Amp Hour" podcast today. It was on Stitcher, and it just played in the car on the drive home. I think it's this one: http://www.theamphour.com/254-an-interview-with-andreas-olofsson-adatevas-ampliative-abacus/
    (highly recommended, and Heater mentioned it here with the Chuck Peddle interview. Great program.)

    They made this exact mistake. They targeted $99, and really they needed $150 - $200 to make it all more sustainable. They didn't ask for all the value, or they launched with not quite enough value, or some combination of the two. I'll have to listen again, but it seemed to be both. On the podcast, you can hear that dialog, and it's very interesting. Of course, this is easy in hindsight, as they all discussed, but it's instructive too. Doing that early work well pays as much as developing the device itself potentially can, at least over the first 5 years of life-cycle. Clearly, a longer term proposition like Propellers are means that won't be true, but you get the idea.

    Here, comparisons to devices that cost pennies, and are not always comparable, nor are their use cases, paint a picture of gloom and doom that really isn't warranted just yet. That's what I mean by not getting into other people's pockets.

    (our pockets always enjoy cheaper, better faster, and that's as it should be, but that really does not always map to the device and it's market dynamics as we think it might)

    Just the other day, I replaced some little ethernet to serial device with a buffer in it for CNC machines. This is often used as a "drip feeder" or DNC type device and it's use case is for machining complex parts that have G-code representations much larger than the controller memory can handle. So, the part gets streamed from another computer, a few lines at a time, over this serial link, as if a machine were sitting right there. Early on, pre-ethernet, a shop PC would do this task via direct serial, and floppy type storage would be used to move programs...

    They paid something like $300 for this thing! It's got maybe three chips tops on a board I'm pretty sure would pack into the free EAGLE package too! The BOM on it is probably $5, maybe a bit more due to the nice sheet metal case, and the feature set is modest, just enough to get this transfer done and not a lot else. Now, these things are largely transparent. I like 'em, and I like 'em, because I never see or hear about them, until they die, and they usually die a slow death due to cutting oil and other messy things found in machining centers, or a power spike of some sort. Typically, they run for years. So the "I could make one of these" part of me just screams at the $300, but the operations manager part of me doesn't even think twice. If I need one, I buy it, no questions asked, because I have no hassles once it arrives and even one little hassle costs more than that $300 in the typical manufacturing scenario. Plug and play man. Worth every penny.

    (Notably, for that sum, I could drop a PC out there and get away with a smaller initial spend. But a PC comes with hassles, and those hassles cost more as mentioned. A big part of the value of that $300 is just the limited, well targeted and robust function. Really don't care what it costs as much as I care about it doing that thing I need done hassle free. I see some of these devices land in the $100-$200 range. Plastic box, coupla LED's, connectors, CPU, etc...)

    So somebody did the hard software work, and it's good work, because the devices just do what they are supposed to do and we never think about them.

    There are tons of niches like this. P2 is a much more capable device, or will be dammit! That bigger scope of possible tasks is going to drop it right into these sorts of scenarios, and having bullet proof, "it just works" type performance will be worth a lot to people who need it and who don't want to think so much about it all.

    ...and a whole lot of those are opening up in tandem with the US buildup of industrial robots too. A small "PLC" gets dropped in to many "cell" type scenarios, or anyplace where the robot needs to make decisions, or be augmented in some basic way. I'll tell you right now a simple, robust, flexible P2 based product set that can tackle a variety of inputs, perhaps display basic things, and interact with robots is going to be a high margin thing, just one of many. All it's going to take is somebody to target what is being done, add the up and coming use case features and go sell hard to a few robot integrators and it's game over. Money machine for 10-20 years.

    This is the kind of thing I see P2 doing very well, and the margins in that stuff are huge. They need to be. Downtime, implementation time, and any kind of time is brutal. People are expensive, machines are expensive, floor space is expensive. Get it done, get it done right, and get it done quick trump cheap every single time in that space.

    However it's initially priced, it just needs to be where Parallax stands a great chance at moving forward in a business sustainable way. As that gets done, and economies of scale begin to apply, it will drop just like P1 did. No worries.

    Early adopters will pay great margins to capture great value early. Niche players will continue to pay great margins because they get great margins too. Doesn't have to be a coupla bucks to make it. It just needs to nail a few sweet use cases, IMHO. And as we've seen P2 develop, there seems to be quite a few potentials there. I personally am not worried over any of that.

    Just need to see the dang thing! Go Chip go! Maybe I'll send him some good "flow music" on vinyl to keep the creative juices flowing! :)
  • LeonLeon Posts: 7,620
    edited 2015-06-23 01:24
    It's going to find it very difficult competing with the new XMOS xCORE-200 devices:

    http://www.xmos.com/products/silicon/xcore-200

    Up to 32 logical cores and 4000 MIPS. They start at $6.20 for eight cores and 1000 MIPS.

    They have shipped a limited quantity of these eXplorerKIT boards:

    http://www.xmos.com/products/boards#explorerkit-200

    but the devices are not yet in full production.

    They have cornered the market in high-end audio with their earlier devices, BTW.
  • MicksterMickster Posts: 2,304
    edited 2015-06-23 01:40
    Leon wrote: »
    It's going to find it very difficult competing with the new XMOS xCORE-200 devices:

    http://www.xmos.com/products/silicon/xcore-200

    Up to 32 logical cores and 4000 MIPS. They start at $6.20 for eight cores and 1000 MIPS.

    They have shipped a limited quantity of these eXplorerKIT boards:

    http://www.xmos.com/products/boards#explorerkit-200

    but the devices are not yet in full production.

    No kidding! Wow!
  • jmgjmg Posts: 14,979
    edited 2015-06-23 01:53
    Leon wrote: »
    It's going to find it very difficult competing with the new XMOS xCORE-200 devices:

    Interesting parts, but I notice they have quietly lifted the lowest-price point on this family.
    Similar to how some FPGA vendors newest families can often drop a lowest-price point along the way..

    Still, they are in the Prize Zone P2 expects to inhabit so that will invite comparisons.
    The extra RAM and connectivity add appeal.
  • Heater.Heater. Posts: 21,230
    edited 2015-06-23 02:36
    Oh, I have to say it again:

    I love XMOS devices it's a brilliant architecture. And I love the XC language, a tweaked version of C that makes it dead easy to setup parallel threads and communicate between them, even on totally different chips! And being a Brit have to wave the flag for them.

    However...I wish XMOS would stop it with that "logical core" nonsense. 32 "logical cores" is actually 4 actual cores (I think they are calling them "tiles" no a days) each of which supports up to 8 instruction by instruction hardware time sliced threads (Similar to what was implemented in the PII in one iteration of the design)

    That 4000MIPS is then 1000MIPS per core/tile or 125MIPS per thread. Mind you if you restrict yourself to 4 threads on a core they will all run at 256MIPS due to the way the four stage pipeline works, if I remember correctly.

    That explorekit is frikken expensive, and not it is only the 2 tile 16 thread device. Confusingly it's hard to tell from the intro blurb what combination of gyro and/or accelerometer and/or magnetometer it has on there. Turns out to be all of them:
    Bosch BMG160 ultra-small, digital 3-axis angular rate sensor.
    Freescale FXOS8700CQ 6-axis sensor, accelerometer and magnetometer.

    Somehow it only has 53 GPIO from one of it's cores, what happened to all the IO on the other core? (N.B. Each core has it's own I/O pins, you cannot use any pin from any core like the Propeller.

    Why are their dev boards so ugly? Green with big, ugly, clunky looking connectors on them. Their original dev boards were small, red and sexy.

    Anyway, my order is going in ...
  • jmgjmg Posts: 14,979
    edited 2015-06-23 02:38
    Heater. wrote: »
    Why are their dev boards so ugly? Green with big, ugly, clunky looking connectors on them.
    .. really ?
  • evanhevanh Posts: 13,849
    edited 2015-06-23 02:46
    Heater. wrote: »
    However...I wish XMOS would stop it with that "logical core" nonsense. 32 "logical cores" is actually 4 actual cores (I think they are calling them "tiles" no a days) each of which supports up to 8 instruction by instruction hardware time sliced threads (Similar to what was implemented in the PII in one iteration of the design)

    That 4000MIPS is then 1000MIPS per core/tile or 125MIPS per thread. Mind you if you restrict yourself to 4 threads on a core they will all run at 256MIPS due to the way the four stage pipeline works, if I remember correctly.

    Yeah, I remember looking over that datasheet last time it was linked here. The cores are actually threads. And, if I'm not mistaken they've changed the pipeline (for lack of a better name) a little from earlier incarnations to be 5 stages now, so the max MIPS per thread is 200 MIPS.


    EDIT: Not that 200MIPS is bad, just that they should list it as part of the quick specs.
  • LeonLeon Posts: 7,620
    edited 2015-06-23 02:49
    I can't see any "big, ugly, clunky looking connectors" on them.
  • LeonLeon Posts: 7,620
    edited 2015-06-23 02:50
    evanh wrote: »
    Yeah, I remember looking over that datasheet last time it was linked here. The cores are actually threads. And, if I'm not mistaken they've changed the pipeline (for lack of a better name) a little from earlier incarnations to be 5 stages now so the max MIPS per thread is 200 MIPS.

    Didn't Heater show that they were equivalent to Propeller cores, a long time ago? IIRC, time-sliced threads are the same as servicing Propeller cores in a round-robin fashion.
  • evanhevanh Posts: 13,849
    edited 2015-06-23 02:55
    Leon wrote: »
    Didn't Heater show that they were equivalent to Propeller cores, a long time ago? IIRC, time-sliced threads are the same as servicing Propeller cores in a round-robin fashion.

    I wasn't comparing to the Prop. The Prop is even weirder because it depends on whether you are talking about a Hub view or a Cog view.
  • evanhevanh Posts: 13,849
    edited 2015-06-23 03:11
    evanh wrote: »
    And, if I'm not mistaken they've changed the pipeline (for lack of a better name) a little from earlier incarnations to be 5 stages now, so the max MIPS per thread is 200 MIPS.

    That's right, I think it's normally only 100 MIPS per thread because the system clock is really 500MHz. The 200 MIPS potential requires a special dual fetch mode and it seemed as though that wasn't always guaranteed.
  • Heater.Heater. Posts: 21,230
    edited 2015-06-23 03:47
    Leon,
    Didn't Heater show that they were equivalent to Propeller cores, a long time ago? IIRC, time-sliced threads are the same as servicing Propeller cores in a round-robin fashion.
    I can't quite remember how I argued it at the time but my thesis is that if your processor is fast enough it can simulate any number of cores/time sliced threads you like. As long as it looks the same from the outside, from the point of view of it's inputs and outputs, who cares if it has multiple cores, instruction sliced threads, interrupts, or is not a CPU at all but just a sea of logic gates performing the same task.

    The give away of course is speed. You aren't going to be able to achieve the same time performance as multiple cores on a single core unless it is a lot faster, which is not practical of course.

    And that is what is misleading about the XMOS marketing. That 1000MIPS core with 8 "logical cores" cannot do 1000MIPS on each thread. Only 250 or 200 or whatever it is now. It also hides the fact that after 4 threads on a core the per thread MIPS starts to fall off.
    I can't see any "big, ugly, clunky looking connectors" on them.
    What is that big ugly black thing at the top right of this picture: https://www.xmos.com/files/images/explorerkit-200.jpg
  • David BetzDavid Betz Posts: 14,487
    edited 2015-06-23 04:13
    Heater. wrote: »
    Leon,

    I can't quite remember how I argued it at the time but my thesis is that if your processor is fast enough it can simulate any number of cores/time sliced threads you like. As long as it looks the same from the outside, from the point of view of it's inputs and outputs, who cares if it has multiple cores, instruction sliced threads, interrupts, or is not a CPU at all but just a sea of logic gates performing the same task.

    The give away of course is speed. You aren't going to be able to achieve the same time performance as multiple cores on a single core unless it is a lot faster, which is not practical of course.

    And that is what is misleading about the XMOS marketing. That 1000MIPS core with 8 "logical cores" cannot do 1000MIPS on each thread. Only 250 or 200 or whatever it is now. It also hides the fact that after 4 threads on a core the per thread MIPS starts to fall off.

    What is that big ugly black thing at the top right of this picture: https://www.xmos.com/files/images/explorerkit-200.jpg
    It seems to me that I've heard the Propeller described as a 160 MIPS processor and it certainly can't do 160 MIPS on a single COG.
  • LeonLeon Posts: 7,620
    edited 2015-06-23 04:45
    Heater. wrote: »
    Leon,

    What is that big ugly black thing at the top right of this picture: https://www.xmos.com/files/images/explorerkit-200.jpg

    It's the standard xSYS/xTAG debug connector.
  • bruceebrucee Posts: 238
    edited 2015-06-23 06:21
    I could throw out my next shot, but really my point of posting here is the topic forum is P2 release date and price.

    I still think the price is too high (though just guessing about what that might be), but it is apparent now that the release date is into mid 2016 at the earliest.

    So my suggestion is rather than keep the P2 in the critical path, maybe it is time for Parallax to look around for a BS2, P1 enhancement from off the shelf. It would just be another entry into their family and I remember seeing some rumblings about a new unified IDE in the works. Maybe the release of that was to kick off the P2, so maybe that should be sooner with something else.
  • Heater.Heater. Posts: 21,230
    edited 2015-06-23 12:12
    @Leon,

    Yes, it's the xSYS connector. And it's big and ugly and it's sticking out clumsily at the side there. Blech.

    @brucee,

    As far as I can gather you are suggesting Parallax resell someone else's chip with a BASIC or whatever language on it.

    I think I have said before, in my opinion selling another guys chip is not a money maker. A closed source BASIC, or whatever, will not fly now a days. Those times have gone. I mean, why would one not use this http://www.espruino.com/ or this https://micropython.org/store/#/store or this https://tessel.io/ or this http://www.instructables.com/id/Getting-Started-with-the-ESP8266-ESP-12/ or this https://www.particle.io/prototype the various incarnations of the Arduino?
  • bruceebrucee Posts: 238
    edited 2015-06-23 14:44
    Yes Heater, I am suggesting they sell other peoples chips.

    Look at the product list at Parallax, a lot of other peoples stuff. And the BASIC Stamp is a custom programmed Microchip part. It is not a business I would want to be in, but a large part of it is the one stop shop nature for educators and hobbyists. And the history of excellent support, educational programs...

    I don't know what their sales are, but it seems to me most of their revenue comes from things other than the P1. I am not suggesting they stop P2 development tomorrow, and if they want to make it Chip's life's work they can do that as long as the other products support it.
  • jmgjmg Posts: 14,979
    edited 2015-06-23 15:22
    brucee wrote: »
    So my suggestion is rather than keep the P2 in the critical path, maybe it is time for Parallax to look around for a BS2, P1 enhancement from off the shelf. It would just be another entry into their family and I remember seeing some rumblings about a new unified IDE in the works. Maybe the release of that was to kick off the P2, so maybe that should be sooner with something else.
    ? P2 is not in the critical path ?
    There has been a lot of work on C, and IDEs and programmers, and PropBASIC is even being pulled into the IDE fold, and those are all P1 focused.
    They are not waiting on P2

    Better flow support for PropBASIC makes a New-BS2 an easier transition, should someone want to use P1
    ( My belief is any "New-BS2" should be 5V capable & there are many choices there..., but if I was Parallax I might try to use P1 and level shifters )

    For the same reason, I see 3V-variant Arduinos stuttering and failing.
  • markmark Posts: 252
    edited 2015-06-23 16:17
    Speaking of XMOS (wait, are we still talking about it?), I just noticed they have a part with an integrated ARM M3. Judging by the datasheet's description, it seems to be a separate die in the package which is wire bonded to the XMOS die.
  • LeonLeon Posts: 7,620
    edited 2015-06-23 17:38
    Where did you see that the ARM is a separate die? It's described as an SoC.
  • jmgjmg Posts: 14,979
    edited 2015-06-23 18:18
    Leon wrote: »
    Where did you see that the ARM is a separate die? It's described as an SoC.
    hehe, do not take too literally, anything XMOS says.

    I have always taken the M3 to be a 2 die solution, and sure enough, google finds this :

    ["XA products are two die solutions: one integrates the M3 and hard peripherals; the other has the xCOREs and hardware response ports. The combination of the two dice is claimed to bring high computing performance with low power consumption. -"]

    Turns out that M3 die comes from Energy Micro (now SiLabs)
  • Heater.Heater. Posts: 21,230
    edited 2015-06-23 19:08
    So that XMOS ARM is a SoC. But on it's own separate die. Crazy, complicated, expensive, stupid idea. Probably dreamt up by the same marketing wonk who though "logical cores" was a good idea after seeing that high end FPGAs have ARMs in them.
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