Damn! I thought you may see the shuttle chips mid April. Nevermind though - we have the DE0 & DE2 emulations and they are keeping us busy with exciting bits Chip keeps releasing as he gets time. Wow this chip is just going to fly
"I thought you may see the shuttle chips mid April." - I did too! ... The FAB's automated scheduler for shuttle runs did not account for the Chinese New year and claimed to have a shuttle run on February 20th that in actuality did not even exist other than on paper ... Even worse, It's a Taiwan (TSMC) process being FABed out of India ... So who's confused now? <- I am read on
They are being fabricated in Taiwan at TSMC. We've been dealing with the Bangalore branch of Open-Silicon lately to get the wafer order finalized, so that's probably why Beau is supposing the chips are made in India.
They are being fabricated in Taiwan at TSMC. We've been dealing with the Bangalore branch of Open-Silicon lately to get the wafer order finalized, so that's probably why Beau is supposing the chips are made in India.
Open-Silicon? Does that mean that the design for the P2 is going to be open? :-)
That video is VERY analogous to the e-mail traffic that has been going back-and-forth lately :-)
In an earlier post... Yes Chip is correct, my assumption on the location of where the chips are being FABed was erroneously based on who and where we communicate with.
Open-Silicon? Does that mean that the design for the P2 is going to be open? :-)
You jest of course
While I think it would be absolutely fantastic to see the VHDL code, be able to modify it, and to play with this in the emulators, can you imagine every man and his dog making variant chips from this?
Imagine 100's of variants of P2 - what a nightmare - all of the reasons the P1 is so loved would go out the door!
While I think it would be absolutely fantastic to see the VHDL code, be able to modify it, and to play with this in the emulators, can you imagine every man and his dog making variant chips from this?
Imagine 100's of variants of P2 - what a nightmare - all of the reasons the P1 is so loved would go out the door!
Yes, I was kidding and I believe that P2 was done in Verilog not VHDL.
While I think it would be absolutely fantastic to see the VHDL code, be able to modify it, and to play with this in the emulators, can you imagine every man and his dog making variant chips from this?
Imagine 100's of variants of P2 - what a nightmare - all of the reasons the P1 is so loved would go out the door!
I understood what was being asked about the Prop2 being made "open", but at this point, "open" only seems like a great way to make even less money. Of course, making any money from this is still somewhere in the future.
I understood what was being asked about the Prop2 being made "open", but at this point, "open" only seems like a great way to make even less money.
Yes, I'm sure you're right although I doubt if too many people in this forum have enough money to fab their own version of the P2.
I just recently convinced STMicroelectronics to release all of the RTL for a chip my old company, VM Labs, produced back around 2000. This is a four 32 bit core chip that was supposed to go in a DVD player and has MPEG decode hardware and other cool stuff. Unfortunately, I don't know enough to get the RTL working in an FPGA so I'm not sure it will ever actually make it to Open Cores.
Yes, I'm sure you're right although I doubt if too many people in this forum have enough money to fab their own version of the P2.
I just recently convinced STMicroelectronics to release all of the RTL for a chip my old company, VM Labs, produced back around 2000. This is a four 32 bit core chip that was supposed to go in a DVD player and has MPEG decode hardware and other cool stuff. Unfortunately, I don't know enough to get the RTL working in an FPGA so I'm not sure it will ever actually make it to Open Cores.
Is this what you're talking about?:
2001 - "Aries-3" silicon (first fully designed at VM Labs) begins production. This design was faster, lower cost, lower power and more highly integrated than the Motorola versions, and fabricated at TSMC
2001 - "Aries-3" silicon (first fully designed at VM Labs) begins production. This design was faster, lower cost, lower power and more highly integrated than the Motorola versions, and fabricated at TSMC
Yup! That's it. I even have some chips but I'm not a hardware guy so I can't really do much with them. The cores are VLIW and there is a gcc port that Eric worked on.
Yup! That's it. I even have some chips but I'm not a hardware guy so I can't really do much with them. The cores are VLIW and there is a gcc port that Eric worked on.
While I think it would be absolutely fantastic to see the VHDL code, be able to modify it, and to play with this in the emulators, can you imagine every man and his dog making variant chips from this?
The high Setup costs kill this idea of 'free' anyway - having Verilog code is only a small piece of any final chip.
You need to add Silicon place and route and simulate, then fund Ma$k$ (N times?!), and finally develop full test suits, so you know you have working devices.
There could be some educational opening for Verilog to land in FPGA, or high end CPLD, but the MHz and COG numbers would be well behind P2 (or even P1) and you have no Analog - so it is unlikely to have much commercial footprint.
For example, it could be interesting to see just what would fit in LCMXO2-7000HE-B-EVN
jmg: I would like to see what would fit into a large Xilinx Spartan 6. But the Spartan 6 chip cost would most likely prohibit its' use in real life. ANd yes, this is only one part of the equation, but there is a lot of R&D in that VHDL code. Why give an opposition company (read existing micro companies) your R&D on a plate. They would put you out of business in a blink of the eye. At least currently they would have to buy Parallax.
The high Setup costs kill this idea of 'free' anyway - having Verilog code is only a small piece of any final chip.
You need to add Silicon place and route and simulate, then fund Ma$k$ (N times?!), and finally develop full test suits, so you know you have working devices.
There could be some educational opening for Verilog to land in FPGA, or high end CPLD, but the MHz and COG numbers would be well behind P2 (or even P1) and you have no Analog - so it is unlikely to have much commercial footprint.
For example, it could be interesting to see just what would fit in LCMXO2-7000HE-B-EVN
That part only has less than 7k gates, whereas the chip on the DE0-nano has 22k.
Any information regarding power requirements? Just doing some preliminary work for our in-house development boards and need a ball park figure to proceed.
Comments
Hehe, nothing like that, to make you feel like you are using 'trailing edge' technology.
The plus side is, all cost amortizing should have been done long ago...
They are being fabricated in Taiwan at TSMC. We've been dealing with the Bangalore branch of Open-Silicon lately to get the wafer order finalized, so that's probably why Beau is supposing the chips are made in India.
It's actually going to be encapsulated in plastic. I wish it was open, so that we could probe it, in case it doesn't work.
Yeah, I was thinking "Open-Silicon" might be like "Open Cores", the RTL is open source. I think that's highly unlikely with the Propeller though!
http://www.youtube.com/watch?v=NRmGVe0GtpU
Rich
That video is VERY analogous to the e-mail traffic that has been going back-and-forth lately :-)
In an earlier post... Yes Chip is correct, my assumption on the location of where the chips are being FABed was erroneously based on who and where we communicate with.
While I think it would be absolutely fantastic to see the VHDL code, be able to modify it, and to play with this in the emulators, can you imagine every man and his dog making variant chips from this?
Imagine 100's of variants of P2 - what a nightmare - all of the reasons the P1 is so loved would go out the door!
It was ported from AHDL (what chip originally started with) to VHDL.
I understood what was being asked about the Prop2 being made "open", but at this point, "open" only seems like a great way to make even less money. Of course, making any money from this is still somewhere in the future.
It's all in Verilog, except the top part that connects it to the FPGA pins. That part is in Altera AHDL.
I just recently convinced STMicroelectronics to release all of the RTL for a chip my old company, VM Labs, produced back around 2000. This is a four 32 bit core chip that was supposed to go in a DVD player and has MPEG decode hardware and other cool stuff. Unfortunately, I don't know enough to get the RTL working in an FPGA so I'm not sure it will ever actually make it to Open Cores.
Is this what you're talking about?:
2001 - "Aries-3" silicon (first fully designed at VM Labs) begins production. This design was faster, lower cost, lower power and more highly integrated than the Motorola versions, and fabricated at TSMC
Have You any pic with Registers / Cores and any instructions info ?
The high Setup costs kill this idea of 'free' anyway - having Verilog code is only a small piece of any final chip.
You need to add Silicon place and route and simulate, then fund Ma$k$ (N times?!), and finally develop full test suits, so you know you have working devices.
There could be some educational opening for Verilog to land in FPGA, or high end CPLD, but the MHz and COG numbers would be well behind P2 (or even P1) and you have no Analog - so it is unlikely to have much commercial footprint.
For example, it could be interesting to see just what would fit in LCMXO2-7000HE-B-EVN
That part only has less than 7k gates, whereas the chip on the DE0-nano has 22k.
If we could determine the proper time units, yes.
LOL. So microseconds are out then. Perhaps megaseconds?
That made me laugh, which is a good thing (Martha). I imagine those words being said with either a straight face or a sly smile.
They remind me a bit of these words by Henry Ford, "Any customer can have a car painted any colour that he wants so long as it is black. "
Many thanks
Rob