Work is progressing on a Schematic Portfolio, which will include two sections of paper and napkin sketches, and CAD created diagrams.
Schematics will be subdivided into several main areas for matching code. When the Portfolio is completed, the next step is a continuing refinement of the Hybrid Interface.
The Hybrid Interface combines existing interfaces to reduce wiring and complexity.
The SP will go back in time to include test circuits. Completed version ranges may also be included.
If the average person can remain intrigued for half an hour by such a robot and the A-Brain that controls it, then we state that the A-Brain has passed the China Test.
I think there ought to be some conditions on this statement.
I don't think it would be very hard to build a machine that intrigues people for half and hour and still have a relaitive unintellegent machine. I think of some of the contraptions I've seen links to from the forum. The long line of Lego contraptions that moved little ball through a bunch of different devices for sorting, raising, etc. I was intriged watching it but I don't think it was very intellegent.
The China Brain Project is using this robot.
I think getting a robot as simple as this to intrige people for half and hour would be an impressive feat.
Duane wrote: I don't think it would be very hard to build a machine that intrigues people for half and hour and still have a relative unintelligent machine.
I don't know how they came up with that criteria either. Perhaps someone had something stronger than a beer in the left hand and a copy of the Turing Test rules in the other and ironically had this nothing more than extremely amusing outcome. However, the paper makes lots of valid points for their project that would be applicable to other brain projects.
EEPROM Chip as a Pluggable Memory Device Plug & Load
Pencil marks the pluggable EEPROM. At right - eight EEPROMs for eight programs
We talked about a switching crystal circuit but we didn't talk about a switching EEPROM program circuit. The system has now used several EEPROM chips as program storage devices for plug and load performance.
The idea of choose your program, plug it in, and boot it, is a good one for combinations of Brain hardware. The memory chips can hold various tests, neurons, loaders, enumerators, ParaPs, and other code.
This technique uses 24LC256 32K EEPROM chips in DIP configurations which are pluggable. What about the storage of additional data? Use a circuit dedicated second EEPROM.
This works well for solderless breadboard configurations, or simply put a socket on a green board - and it becomes a simple matter to plug in and unplug. Use a system of numbering on the EEPROMS to keep track of which one holds which program.
A small piece of conductive chip foam inside a recycled mini-box can hold these when not in use. They can also be kept plugged into some unused portion of a solderless breadboard or a leftover breadboard dedicated to this sole purpose.
What are the advantages? The Brain can plug and load a program without computer support. It's fast, easy and locks in working programs. It's also great for field use. It can also hold program version until they're EEPROM updated.
(page 54)
1071 Big Brain Power Tower Containment
1072 Brain Cubed
1073 Big Brain Machine Left & Right Hemispheres
1074 Big Brain Netbook Review
1075 Propeller Brain in a Jar Project - Build A Pint Size Machine Brain
1076 Leon
1077 Humanoido
1078 Big Brain Wonder-Board - New BIg Brain Engineered Building Material
1079 Big Brain Servo Stump - Help decide the the Big Brain Robot Stumps!
1080 Brain Shape Shifting
Page 55
1081 The Amazing No Parts Propeller Machine - When Nothing Has Great Value
1082 Multiple PST Instances
1083 12Blocks with Multiple Props?
1084 Hanno
1085 Hanno
1086 Humanoido
1087 Big Brain Reduction Interface RI
1088 A Smaller 800-Cogger Machine
1089 Instructions on Using a Multi Array ParaP System
1090 Hanno
1091 Humanoido
1092 Duane Degn
1093 Hanno
1094 Humanoido
1095 12 Blocks & Propeller - Front End?
1096 Duane Degn
1097 Hanno
1098 SpotLite Index Propeller & AMD Introducing various SpotLite Indices
1099 Designing a Big Robotic Brain Stub
1100 Duane Degn, dynamixel servo
Page 56
1101 Erco
1102 Duane Degn
1103 Erco
1104 Humanoido
1105 LED Brain Application Chronicles - Part 1 What can it do?
1106 Humanoido
1107 To Simulate or Not To Simulate
1108 Can Your Machine Brain Pass the China Test?
1109 Keeping Tabs On Brain Projects
1110 The Ultimate AI Challenge - the Artificial Brain
1111 Parallel Schematic
1112 Schematic Portfolio
1113 List of Big Brain Schematics - Partial List of Back in Time Schematics
1114 Duan Degn
1115 Humanoido
1116 EEPROM Chip as a Pluggable Memory Device - Plug & Load
Big Brain EEPROM Schematic
Schematic Portfolio Series
The EEPROM schematic for each Partition follows the Parallax PEK design
This schematic adds one EEPROM to each Big Brain Partition. The design calls for one EEPROM in each Partition of 50 props. The final Partition with a variable number of props also has one EEPROM. Current Big Brain has 3 Partitions and 3 EEPROMS.
EEPROM purpose includes holding code to load into a Partition and to hold data when loading code is less than 32K. Note that EEPROMs are not required to hold enumerations.
Yes and no. In one way, no, Brain is not solving the many challenges faced by JP Morgan.
On the other hand, yes, Brain is looking at ways to compress space, time and energy required to perform tasks.
No, because Brain does not do Brain pipelining but rather does new faster ParaP as previously discussed which includes Brain invented AtOnce (AO) Technology. See page 48 post 942 for the intro. http://forums.parallax.com/showthrea...g-Brain/page48
Yes, the Brain, in moving up to over 800 combo nodes favorably compares as it has basically become a supercomputer. I fully expect Brain TeraFLOPs power will migrate towards the next level PetaFLOPs.
And yes, very similar in the Hybrid computer design, not with Xenon but with AMD, and not with two TB drives but three.
And finally no, not with 8 cores but with over 1,500 cores (over 800 {Propeller} + 4 {INTEL QUAD} + 720 {AMD GPU}). http://forums.parallax.com/showthread.php?125614-Propeller-supercomputer-hardware-questions/page15
AtOnce
Heater, the intention is to just announce it, however, there's an announcement, definition, and a discussion regarding AtOnce Technology located in the Big Brain thread. Some information about it may also be included with the ParaP discussions. When I have time to make the second round I'll go back, provide links, and spend more time in writing it up and giving it more detail. In a nutshell, it's a Machine Brain technology that can do things at once.
Enter the Left Brain
The Parallax Propeller chips are the first, foremost and main part of the machine. They represent the supermicrocontroller part of the machine and the interfacing to the real world with over 3,200 I/O ports. It has a fundamental theoretical over 160,000 MIPS with over 800 cogs and function mostly in INT. This section can represent greater convenience in programming, has the greatest hard wiring accessibility, and is relatively easy and the fastest for hardware modifications and rewiring as the circuits evolve. This section also represents the power of future prop chip enhancements.
Enter the Right Brain
This FP section is represented by Apple Mac computers, AMD and numerous provided resources. It handles thinking with the add-on TeraFLOPs power, adds numerous parallel processors (over 720), and represents the buildup of supercomputing speed. It has resources to simulate over two million LEDs (2,073,600 with 1920 x 1080 arrays).
If a cog is not running it is consuming minimal power
If a cog is running doing a cogstop on it will get you to 0
If a cog is running then during any waitxxx, will reduce it's consumption to that of 0
Thanks to Mike Green for providing a method to shift in and out of precise timing for asynchronous serial I/O and power savings.http://forums.parallax.com/showthread.php?132961-Propeller-Power-Consumed-Based-on-Code&p=1017605&viewfull=1#post1017605 Overall power consumption is determined mostly by the system clock speed, the number of cogs that are active, and any I/O loads. If you can change to a lower system clock speed, particularly the RCSLOW clock (approximately 32KHz), that will save a lot of power, but you won't be able to do asynchronous serial I/O or other things that require precise timing. Each active cog draws significant power, but a cog waiting with one of the WAITxxx instructions shuts off until the condition is satisfied. An excellent technique when it works for the application is to use the RCSLOW clock and a single active cog waiting with a WAITPNE or WAITPEQ for some I/O condition to occur. The Propeller draws on the order of microAmps most of the time. When the I/O condition is satisfied, the cog "wakes up", changes over to a crystal controlled clock within a few milliseconds, the current drain may increase to a few milliAmps, the cog does whatever work is necessary, switches back to the RCSLOW clock, and waits again.
It's unknown if prop cooling will have any effect on current.
As you have well noted, power must also be kept down. The project has chosen supplementary and peripheral parts that draw minimal current whenever possible, and even disabled twenty PPPB LEDs because they were overly hungry, and a new study goes on because the judicious use of programming can affect power draw in Propeller chips significantly - perhaps seemingly not much in one chip but 100X in a hundred chips and a 1000X in a thousand where the significance goes up.http://forums.parallax.com/showthread.php?125614-Propeller-supercomputer-hardware-questions&p=1017507&viewfull=1#post1017507
"The human brain lays at the foundation of creativity.." (H)
Creativity refers to the phenomenon whereby a person creates something new (a product, a solution, a work of art, etc.) that has some kind of value. What counts as "new" may be in reference to the individual creator, or to the society or domain within which the novelty occurs. What counts as "valuable" is similarly defined in a variety of ways. http://en.wikipedia.org/wiki/Creativity
The project continues with Brain Rounds. The project can have any number of rounds, although there are three primary in use. In the First Round, the idea is established and announced. In the Second Round, all the development ideas are reviewed and analyzed and the best are chosen for continued development. In the Third Round, the chosen task is implemented.
There is some slight overlapping or mixing, even juxtaposition in rounds. For example, round one may include preliminary tests, some rough drawings may be derived, test code samples created, and it may lead to other development ideas. It can include psuedo code and flowcharts. In round two, a database of development ideas inclusive of hardware and software may be created for future programming and hardware machine references. In the third round, final test, final schematics and modular code or integrated code is solidified.
Brain Rounds
Round One - invention, establishment, announcement
Round Two - reviewing, selection, testing, development
Round Three - implementation
Remembering of course only three people work on this project...(me, myself and I). So on the outside things that you see may look slow or sparse but on the inside it seems like a lot is happening. Sometimes I just want to develop and then forget to report and so everything is spread rather thin because it's based on the large number of projects related to the Big Brain. So Brain Rounds will allow the fastest representation of an idea and give it the option to go all the way to completion if found useful.
Round one represents the discovery idea. Reporting on it at the discovery level is not going to create a lot of technical information, if any, but it will document the idea and show directions in which the project is headed. In can open up numerous considerations, many of which are pure thought experiments, like a Chess game, running through various moves and possible plans of design and development contention. Behind the scenes there must be some justification for representing the idea in the first round. Ideas must begin somewhere, and here they begin with documenting round one.
Picasso once said, “It would be very interesting to preserve photographically … the metamorphosis of a picture. Possibly one might then discover the path followed by the brain in materializing a dream.”
Like the metamorphosis of a picture, Brain Rounds materialize into dreams which may come true..
Terms
Brain Rounds - primarily a three step process of establishing and developing ideas, where the idea is established and can undergo a series of rounds of development
Waveform Noise Filter WNF
Schematic Portfolio Series
The Big Brain's Waveform filter development adds one filtering capacitor from pin 31 to ground. Capacitor value is a 10nf. Add one filter to each prop on a multi-prop system. This cleans up noise on the code loading process across physical banks of Propeller chips whose distance can become additive, thereby enabling the loading of programs into more Propeller chips per unit Partition. Tests show reliability of existing Partitions of 50 props per Partition can be extended to much larger numbers. It works so well, that Partitions could be added together and therefore this simple Waveform Filter can result in the design of much larger machines. It's estimated future machines will run at 100 chips (or more) per Partition with an unlimited number of Partitions.
Another use for the Waveform Noise Filter is in the Enumeration function. The filter works well with the Enumeration process and circuit for noise suppression during the enumeration process. The WNF utilizes a capacitor circuit in its most simple form and is designed for use with any Propeller pin and can function with other interfaces to filter out noise.
Create an effective TC timing constant (TC reflects how fast the circuit responds to changes in the voltage level) with the chosen capacitor value to match the circuit. Begin with a .1uF capacitor. Another common value is .01uf. Sometimes you will see a call for a 10nF capacitor measured in nanofarads instead of microfarads.
Individual WNFs use resin coated ceramic disc capacitors to effectively short very high frequency noise spikes to ground. This prevents noise from getting back into the line and traveling to other circuits and chips. The capacitor can act as filter to remove ripple from DC distribution signals or supply and smooth out uneven DC signals. Place multiple DC filters between line and ground.
WFNs work well in the Neural Matter Injector for global distribution and helps de-noise the Hybrid. Additionally as the length of interfacing (wiring) is slightly increased, WFNs will increase signal reliability by cleaning it.
The frequency of the ripple can have a role in choosing the capacitor value. Rule of thumb is the higher the frequency, the smaller the bypass capacitor you need. If you have very high frequency components in your circuit, you might consider a pair of capacitors in parallel. One with a large value, one with a small value. If you have very complex ripple, you may need to add several bypass capacitors. Each cap is targeting a slightly different frequency. You may even need to add a larger electrolytic cap in case the amplitude of the lower frequencys is too great.
Parallel Machine
The Big Brain is a special parallel machine that handles AtOnce technology (AO). AO is specifically developed for the Big Brain. Methods in the past took considerable time to load programs into large numbers of multiple chips and were not practical for the Big Brain.
Enumeration
Enumeration was time consuming as well. One could place a hardware circuit, with added parts, and develop code to read the circuit through pins, such as an R/C circuit, or provide another way, i.e. generate random numbers and hope for no duplicates. Accomplishing code for simple consecutive enumeration in true parallelism that could take place at once without any hardware was not available at that time.
Partition
The Big Brain Propeller machine was developed as a parallel machine. Banks of increasingly large Propeller arrays were introduced with a variety of test brain machines until the Partition was developed, based on a capping of the number of maximum Propeller chips per array.
WFM Waveform Noise Filter
Each Partition increased and was capped at 50 props for reliability, however the introduction of the WFM Waveform Noise Filter opened up capability for much larger Partitions for more massive machines.
Additive Arrays
One spinoff of developing these large array Partitions is that the experimental number of three could operate at the same time, in parallel. Two complete Partitions became the basis of parallel experiments.
Parallel - Parallel, or ParaP
This led to another spinoff of Parallel - Parallel, or ParaP. Things can happen simultaneously in multiple Partitions functioning in parallel. For example, two large Partitions are being designed to load at the same time, enumerate at the same time, inject matter at the same time, and function at the same time.
AtOnce or AO technology
This led to the next step, the technique of AtOnce or AO technology. AO represents things that appear to happen at once, or at the same time in terms of human observation. AO is being geared towards the aforementioned elements, ParaP, Enumeration, Injection, and Loading.
AO & Interfacing
Another use of AO is in interfacing. With a parallel interface as previously discussed, the design is a transmission of data that can be received at the same time by all listening props contained in large arrays.
AO Timing
AO can be defined in terms of timing. At first, the definition simply included things which take place simultaneously in true parallel, however continued definition design development now includes those events around 1 second or less. This will represent the time it takes to complete one task by all props - over the entire range of all combined Partitions.
New Paradigm in Propeller Big Brain Technology
Connecting the brains of Man & Machine
Connecting the Brains of Man and Machine - Discovery Post
(I plan to connect a human brain to the Big Brain)
For years I've though about the ramifications of connecting the human brain to a machine brain and pondered the effects and results of such a connection. It is now possible to develop the tools necessary to make this connection so it's time to begin considerations.
What would you do if you could connect yourself to the machine? This is the beginning of a new era in Brain Technology when man becomes a part of the machine and visa versa.
In a number of Big Brain experiments it was determined that the Big Brain is not unlike the human brain in the emission of brain waves. It is now possible to read and discern the brain waves of both man and machine. (see Brain Wave post)
You probably remember seeing some of my posts about identifying programming functioning in the Big Brain with that of its emitted brain wave activity. These machine brain waves form the basis of a communications link with a biological brain.
Likewise, the brain activity of a biological brain is very specific and forms the basis of a communications link with a machine brain.
This can form a full duplex man and machine brain to brain communications interface.
The cost of supporting parts and tools for the technology of reading and recording brain wave activity in man and machine has reduced to a point of constructive affordability. It can be constructed of DIY and off the shelf materials.
It is at this time we will begin a program to undertake the merging of a human brain to that of a machine brain. (don't worry, the connection will be noninvasive)
The cognitive computing team, led by IBM Research, in collaboration with colleagues from Lawrence Berkeley National Lab, has performed the first near real-time cortical simulation of the brain that exceeds the scale of a cat cortex (PDF) and contains 1 billion spiking neurons and 10 trillion individual learning synapses.
The news is general and we don't know the specifics of the neurons generated for the brain simulation. If the Big Brain project can use it's simplex neurons, perhaps a fractional cat experiment could be achieved.
‘Hand of Man’, an outsized hydraulic arm that can be operated from a little gloved controller nearby. “It’s modeled on the human hand and foreman and has the same range of motions,” says New Mexico-based artist Christian Ristow, who took about six months to build the installation. “It is all hydraulic and powered by diesel engines.”
One/Many Propeller Programmer Big Brain Applications
In the past we required special and sometimes expensive single platform program loaders to place code into chips. If you wanted to place code into more than one chip it was sometimes an arduous manual process of one by one chip insertion. program, remove, then repeat.
The big Brain project is developing an attractive high speed parallel interfacing feature that's advantageous for this application. The project is moving towards the application as a one chip programmer that programs hundreds of chips at the same time.
In the case of large and massive parallel hobby machines with parts reduction, the Propeller Programmer Application can simply load code into hundreds of Propellers by their volatile RAM. In the case of commercial companies seeking to load Propeller product, a more nonvolatile EEPROM can be attached for more permanency of code retainment after the power is removed.
Imagine a simple execution of the app, the first lead propeller is wired to hundreds of others which are all inserted into simple solderless breadboards. The code is loaded along with the Propeller loader and executed. Code is at once distributed into each and every Propeller chip. A second later, a hundred Propellers are ready to roll off the assembly line.
Exponential Do-It-Or-Lose-It Development
Big Brain Development Speed Goes Exponential
In the Beginning
When the project began, it merely inched along like a slug and every step was an effort to put one foot in front of the other. Many things about getting started were unknown and wheels had be invented, tried and tested, not to mention the long hours of research, along with the setback of crashed computers. It seemed to be a slow linear progression of development.
Picking Up Speed
Gradually in the time, the project began to pick up speed. After the main elements of the machine were in place, many machine designs, new tests, algorithms and ideas began to more rapidly appear in a new light and the linear progression line was replaced by a rapidly accelerating curve of development.
Exponential Rate
Forward another two months into the project and an exponential rate of development appeared. Platform begat platform, with ideas upon ideas, even new supporting machines were added, until suddenly there was simply not enough time - hours in a day, weeks, or months to fully document everything that required it.
Do-It-Or-Lose-It
Rather than lose important ideas by bringing rapid development to a suspended halt just to create reams of documents that likely would need rewriting anyway, a do-it-or-lose-it development approach is established which fits, just barely, the exponential development rate. Since this intro of DIOLI, the project is doing its best to continue new developments at full pace, taking on laps like a race car.
Quick Preservations
This at best utilizes memory, personal logs, napkin sketches, scratch paper, pseudo code, simple notes, WP representations, snapshots, and Quick Preservations which are based on establishing Time Lock Stops in time.
Time Lock Stop
If a documentation can be created fast enough to generate a Quick Preservation, a Time Lock Stop will be initiated to accomplished it. Time Lock Stops of only extremely short durations are allowed. Why? When Lock Stops were not in place, an inordinate amount of time was recklessly spent in drafting a schematic in its final form at a time when the project was not in its final form and the schematic would be revised anyway after revisions and thus need redrawing again.
Definitions of Terms Quick Preservation creating documentation quickly in limited fashion, can rely upon memory or napkin sketches Do-It-Or-Lose-It rapid exponential development technique with quick preservation Time Lock Stop short stop in time to provide time frame for development documentation WP word processing SnapShots quick documents made with image capture
What would you do if you could connect yourself to [a machine brain]?
The first thing I would use this for would be to have a direct connection to all necessary information. Like a google in your head. In a meeting where the discussion veers into some issue that was not on the agenda it would be useful to instantly look up (without having to fiddle with a laptop) the technical details of whatever instead of deferring it to an action for later. Heck, even being able to always know the name of everyone you met..
Big Brain Prop Plug Schematic
Schematic Portfolio Series
Big Brain schematic shows connection for one Parallax Prop Plug, part number 32201, LED device on P15, R2 dropping resistor, and C1 decoupling capacitor. P28 and P29 plus power rails VDD and VSS lead to the EEPROM (not shown).
Refer to the following post for information about selecting a decoupling capacitor value: Big Brain Decoupling Capacitor Schematic
Schematic Portfolio Series
Use a Multilayer ceramic capacitor, Nanjing Chiyang Electronics, CT4-0805-Y5V, P/N 63V-104-M 10nF or .1uF. Dropping resistors are 10K ohm. Note the schematic shows the first Propeller chip in a Big Brain Partition.
Edit: Note - remember to install a decoupling capacitor on both sides of each Propeller chip.
The Big Brain project is now introducing the Schematic Portfolio Series. The SPS is designed to show a comprehensive circuit-by-circuit drawing series, as a collection of individual schematics.
The first schematics introduced are for those circuits which are not expected to be modified. The idea is to create this first phase drawing program and then later advance to a planar multi-layer system. What will this lead to?
After the multi-layer schematic system is completed, it is expected to advance to schematic extrusion in three dimensions. Beyond that, we have the Genetic Schematic, proposed earlier, which can be reproduced from DNA constructs. That's intended to be read by Big Brains that need to procreate and duplicate circuits.
DNA mapping for reconstruction from DNA schematic constructs is extremely important for rebuilding a damaged brain section, cloning new circuits and internal brain hardware, and storing, memorizing, archiving a genetic code.
Definitions & Terms
SPS schematic portfolio series, a collection of schematics in various forms Multi-Layer Schematic layers of schematic can be placed one on top of another to see the entire machine or looked at one at a time to reduce complexity Schematic Extrusion a schematic is represented in 3D space Genetic Schematic a machine DNA schematic of genetic code numbers that allows reconstruction, birth, procreation
Both power and ground pins should be connected, and decoupled.
The actual machine has both chip sides decoupled. This is also shown in schematic post 1121. The quick schematic for the prop plug should not show the LED or any decoupling capacitors (they are shown in their own schematics) and will be redrawn to reflect this during the next revision. A note is now added to the post.
The first thing I would use this for would be to have a direct connection to all necessary information. Like a google in your head. In a meeting where the discussion veers into some issue that was not on the agenda it would be useful to instantly look up (without having to fiddle with a laptop) the technical details of whatever instead of deferring it to an action for later. Heck, even being able to always know the name of everyone you met.. -Tor
Tor: I absolutely agree. Right now brain technologists can access simple image shapes, feelings, senses, (moods), light and dark, and do some controlling the other way around with brain waves. I'm not going to say it's far off, but we have a small way to go before full implementing of a Google-like brain to brain transfer.
In fact, the human brain will likely need some enhancement in terms of speed and memory storage and retention - however a brain transfer is an important future topic. Once we begin developing various machines of interfacing and the software to brain tap - sensing and communicating with regions of the brain - it will become more easy to transfer data. But the human brain is really slow. It has this vast storage capacity but its access time is deplorable. That's why some human brain enhancement will be required for accessing Google data bases.
For now, there are human brain techniques for remembering the names of everyone you will ever meet from this day forward. It is my belief that everything experienced from birth is stored into the brain, biologically compressed in folds and recesses - it's all a matter of access to remember it.
It is also interesting to know that clinical psychologists have shown that memories and experiences of our ancestors are stored in our brain but only come out under special circumstances. IMO, there's a lot to the human brain that will be explored in the near the future and harnessed for improvements in quality of living.
Comments
Work is progressing on a Schematic Portfolio, which will include two sections of paper and napkin sketches, and CAD created diagrams.
Schematics will be subdivided into several main areas for matching code. When the Portfolio is completed, the next step is a continuing refinement of the Hybrid Interface.
The Hybrid Interface combines existing interfaces to reduce wiring and complexity.
The SP will go back in time to include test circuits. Completed version ranges may also be included.
SpotLite Index - Partial List of Back in Time Schematics
Page 6 112 All About Brain Serial Interfacing
- Two Pin Bi Directional Modes True/Inverted
- One Pin Bi Directional True Mode
- One Pin Uni Directional True/Inverted Mode
- One Pin Bi Directional Inverted Mode
Page 06 #117 LED Schematic Sketch for modifying the LEDPage 06 #116 Connector Pictorial
Page 06 #119 PPPB Sketchings & Schematics Useful data notes for hookup
Page 07 121 LED 2nd Mod Schematic
Page 07 128 Pinout of 1st Connector
Page 09 #171 Round Robin Rings Schematic Brain Blob Basic New Design
Page 10 #200 Color Coded Wiring
Page 12 #222 Brain Logical Addressing Idea for identifying locations
Page 12 #223 Brain Data Light Measurements Setup
Page 13 #254 Brain Schematic Drawing
Page 18 353 Brain Base Communications - schematics
Page 18 355 Brain Stem Wiring Diagram
Page 33 647 Schematic Request Related to Brain Development
Page 34 676 Big Brain Genome Maps Instead of Schematics
Page 42 826 Enumeration Schematic - 6 pin method with two lines
Page 49 969 Brain Mapping with 3D Extrusion - Transcending Traditional Schematics
Page 52 1027 Brain Pre Schematic Appearance
Page 56 1111 Parallel Schematic
Page 56 1112 Schematic Portfolio
Other Sources
The Demo Board Schematic - Mic Input Sound Circuit Included
http://www.parallax.com/Portals/0/Do...DemoDschem.pdf
PPPB
See post 1098 for more SpotLite Index
I think there ought to be some conditions on this statement.
I don't think it would be very hard to build a machine that intrigues people for half and hour and still have a relaitive unintellegent machine. I think of some of the contraptions I've seen links to from the forum. The long line of Lego contraptions that moved little ball through a bunch of different devices for sorting, raising, etc. I was intriged watching it but I don't think it was very intellegent.
The China Brain Project is using this robot.
I think getting a robot as simple as this to intrige people for half and hour would be an impressive feat.
Duane
I don't know how they came up with that criteria either. Perhaps someone had something stronger than a beer in the left hand and a copy of the Turing Test rules in the other and ironically had this nothing more than extremely amusing outcome. However, the paper makes lots of valid points for their project that would be applicable to other brain projects.
Plug & Load
Pencil marks the pluggable EEPROM. At right - eight EEPROMs for eight programs
We talked about a switching crystal circuit but we didn't talk about a switching EEPROM program circuit. The system has now used several EEPROM chips as program storage devices for plug and load performance.
The idea of choose your program, plug it in, and boot it, is a good one for combinations of Brain hardware. The memory chips can hold various tests, neurons, loaders, enumerators, ParaPs, and other code.
This technique uses 24LC256 32K EEPROM chips in DIP configurations which are pluggable. What about the storage of additional data? Use a circuit dedicated second EEPROM.
This works well for solderless breadboard configurations, or simply put a socket on a green board - and it becomes a simple matter to plug in and unplug. Use a system of numbering on the EEPROMS to keep track of which one holds which program.
A small piece of conductive chip foam inside a recycled mini-box can hold these when not in use. They can also be kept plugged into some unused portion of a solderless breadboard or a leftover breadboard dedicated to this sole purpose.
What are the advantages? The Brain can plug and load a program without computer support. It's fast, easy and locks in working programs. It's also great for field use. It can also hold program version until they're EEPROM updated.
(page 54)
1071 Big Brain Power Tower Containment
1072 Brain Cubed
1073 Big Brain Machine Left & Right Hemispheres
1074 Big Brain Netbook Review
1075 Propeller Brain in a Jar Project - Build A Pint Size Machine Brain
1076 Leon
1077 Humanoido
1078 Big Brain Wonder-Board - New BIg Brain Engineered Building Material
1079 Big Brain Servo Stump - Help decide the the Big Brain Robot Stumps!
1080 Brain Shape Shifting
Page 55
1081 The Amazing No Parts Propeller Machine - When Nothing Has Great Value
1082 Multiple PST Instances
1083 12Blocks with Multiple Props?
1084 Hanno
1085 Hanno
1086 Humanoido
1087 Big Brain Reduction Interface RI
1088 A Smaller 800-Cogger Machine
1089 Instructions on Using a Multi Array ParaP System
1090 Hanno
1091 Humanoido
1092 Duane Degn
1093 Hanno
1094 Humanoido
1095 12 Blocks & Propeller - Front End?
1096 Duane Degn
1097 Hanno
1098 SpotLite Index Propeller & AMD Introducing various SpotLite Indices
1099 Designing a Big Robotic Brain Stub
1100 Duane Degn, dynamixel servo
Page 56
1101 Erco
1102 Duane Degn
1103 Erco
1104 Humanoido
1105 LED Brain Application Chronicles - Part 1 What can it do?
1106 Humanoido
1107 To Simulate or Not To Simulate
1108 Can Your Machine Brain Pass the China Test?
1109 Keeping Tabs On Brain Projects
1110 The Ultimate AI Challenge - the Artificial Brain
1111 Parallel Schematic
1112 Schematic Portfolio
1113 List of Big Brain Schematics - Partial List of Back in Time Schematics
1114 Duan Degn
1115 Humanoido
1116 EEPROM Chip as a Pluggable Memory Device - Plug & Load
http://forums.parallax.com/showthread.php?125614-Propeller-supercomputer-hardware-questions&p=1017248&viewfull=1#post1017248
Schematic Portfolio Series
The EEPROM schematic for each Partition follows the Parallax PEK design
This schematic adds one EEPROM to each Big Brain Partition. The design calls for one EEPROM in each Partition of 50 props. The final Partition with a variable number of props also has one EEPROM. Current Big Brain has 3 Partitions and 3 EEPROMS.
EEPROM purpose includes holding code to load into a Partition and to hold data when loading code is less than 32K. Note that EEPROMs are not required to hold enumerations.
Schematic Portfolio Series
Big Brain crystal schematic - adapted from PEK
Each Partition has one crystal wired according to this schematic.
Schematic Portfolio Series
Big Brain Decoupling Capacitor Schematic. Connect
two capacitors to every Propeller chip
Add two .1uF decoupling capacitors to every prop. Refer to all decoupling capacitors posts for the latest information.
Capacitor Converter
http://www.translatorscafe.com/cafe/units-converter/electrostatic-capacitance/calculator/nanofarad-%5BnF%5D-to-farad-%5BF%5D/
Yes and no. In one way, no, Brain is not solving the many challenges faced by JP Morgan.
On the other hand, yes, Brain is looking at ways to compress space, time and energy required to perform tasks.
No, because Brain does not do Brain pipelining but rather does new faster ParaP as previously discussed which includes Brain invented AtOnce (AO) Technology. See page 48 post 942 for the intro. http://forums.parallax.com/showthrea...g-Brain/page48
Yes, the Brain, in moving up to over 800 combo nodes favorably compares as it has basically become a supercomputer. I fully expect Brain TeraFLOPs power will migrate towards the next level PetaFLOPs.
And yes, very similar in the Hybrid computer design, not with Xenon but with AMD, and not with two TB drives but three.
And finally no, not with 8 cores but with over 1,500 cores (over 800 {Propeller} + 4 {INTEL QUAD} + 720 {AMD GPU}).
http://forums.parallax.com/showthread.php?125614-Propeller-supercomputer-hardware-questions/page15
AtOnce
Heater, the intention is to just announce it, however, there's an announcement, definition, and a discussion regarding AtOnce Technology located in the Big Brain thread. Some information about it may also be included with the ParaP discussions. When I have time to make the second round I'll go back, provide links, and spend more time in writing it up and giving it more detail. In a nutshell, it's a Machine Brain technology that can do things at once.
Enter the Left Brain
The Parallax Propeller chips are the first, foremost and main part of the machine. They represent the supermicrocontroller part of the machine and the interfacing to the real world with over 3,200 I/O ports. It has a fundamental theoretical over 160,000 MIPS with over 800 cogs and function mostly in INT. This section can represent greater convenience in programming, has the greatest hard wiring accessibility, and is relatively easy and the fastest for hardware modifications and rewiring as the circuits evolve. This section also represents the power of future prop chip enhancements.
Enter the Right Brain
This FP section is represented by Apple Mac computers, AMD and numerous provided resources. It handles thinking with the add-on TeraFLOPs power, adds numerous parallel processors (over 720), and represents the buildup of supercomputing speed. It has resources to simulate over two million LEDs (2,073,600 with 1920 x 1080 arrays).
based on techniques of coding the Propeller
http://forums.parallax.com/showthread.php?132961-Propeller-Power-Consumed-Based-on-Code&p=1017510#post1017510
Steps to Reduce Power Consumed
- Lower the clock frequency
- Choose lower power consuming pins (see data sheet)
- Choose lowest power pin state (high, low, input, floating)
- Select WAITLOOP, ASSEMBLY, or SPIN for lowest I
- Examine boot sequence profile for lowest I
- Choose a lower current consumptive Cog
- Reduce the number of Cogs in use
- Use WAITs instead of POLLing
- Do less, more statements = more switching = more current
- Decrease the number of chips
Refer to this document Propeller Data Sheet for more information and to cover the many points mentioned above. http://www.parallax.com/Portals/0/Do...eet-v1.4.0.pdfThanks to Duane Degn and Tracey Allen (see chart below) for running actual power tests.
Duane provides Spin test code for varying the frequency and the valuable measured results.
http://forums.parallax.com/showthread.php?132961-Propeller-Power-Consumed-Based-on-Code&p=1017562&viewfull=1#post1017562
Thanks to Heater for providing these three methods for Cog power reduction:
http://forums.parallax.com/showthread.php?132961-Propeller-Power-Consumed-Based-on-Code&p=1017564&viewfull=1#post1017564
- If a cog is not running it is consuming minimal power
- If a cog is running doing a cogstop on it will get you to 0
- If a cog is running then during any waitxxx, will reduce it's consumption to that of 0
Thanks to Mike Green for providing a method to shift in and out of precise timing for asynchronous serial I/O and power savings.http://forums.parallax.com/showthread.php?132961-Propeller-Power-Consumed-Based-on-Code&p=1017605&viewfull=1#post1017605 Overall power consumption is determined mostly by the system clock speed, the number of cogs that are active, and any I/O loads. If you can change to a lower system clock speed, particularly the RCSLOW clock (approximately 32KHz), that will save a lot of power, but you won't be able to do asynchronous serial I/O or other things that require precise timing. Each active cog draws significant power, but a cog waiting with one of the WAITxxx instructions shuts off until the condition is satisfied. An excellent technique when it works for the application is to use the RCSLOW clock and a single active cog waiting with a WAITPNE or WAITPEQ for some I/O condition to occur. The Propeller draws on the order of microAmps most of the time. When the I/O condition is satisfied, the cog "wakes up", changes over to a crystal controlled clock within a few milliseconds, the current drain may increase to a few milliAmps, the cog does whatever work is necessary, switches back to the RCSLOW clock, and waits again.It's unknown if prop cooling will have any effect on current.
Tracy Allen of emesystems.com has created this exemplary chart of power tests (with Spin code). It compares the current at 80MHz with that at 5MHz (with and without pllx1) and at 10MHz. Also with 1, 2 or 3 cogs running with 0, 1, 2, or 3 of them in a waitxxx state. http://forums.parallax.com/showthread.php?132961-Propeller-Power-Consumed-Based-on-Code&p=1017658&viewfull=1#post1017658
mA_exploration.spin http://forums.parallax.com/attachment.php?attachmentid=82953&d=1310588076
Power tests by Tracey Allen, emesystems.com
http://forums.parallax.com/attachment.php?attachmentid=82955&d=1310588476
http://forums.parallax.com/showthread.php?132961-Propeller-Power-Consumed-Based-on-Code&p=1017658&viewfull=1#post1017658
New chart with more data
As you have well noted, power must also be kept down. The project has chosen supplementary and peripheral parts that draw minimal current whenever possible, and even disabled twenty PPPB LEDs because they were overly hungry, and a new study goes on because the judicious use of programming can affect power draw in Propeller chips significantly - perhaps seemingly not much in one chip but 100X in a hundred chips and a 1000X in a thousand where the significance goes up. http://forums.parallax.com/showthread.php?125614-Propeller-supercomputer-hardware-questions&p=1017507&viewfull=1#post1017507
Adding New Threads Rearding Low Power Props
http://forums.parallax.com/showthread.php?129731-Prop-Limbo!-how-low-(power-voltage)-can-it-go!/page2
http://forums.parallax.com/showthread.php?116578-Low-power-usage-of-the-Propeller-current-draw-avoid-using-PLL-3.6vNiMh-3.7vL&highlight=Propeller+current+draw
http://forums.parallax.com/showthread.php?84907-Propeller-Current-Draw&p=582072&viewfull=1#post582072
http://forums.parallax.com/showthread.php?84115-Effect-on-power-consumption-in-control-applications&p=576072
http://forums.parallax.com/showthread.php?132961-Propeller-Power-Consumed-Based-on-Code
This thread has escalated into discussion on how to put the EEPROM to sleep in very low power mode!
The idea is to load the Propeller array Partition first, then sleep the EEPROM at extremely low power, until it's required for use.
http://forums.parallax.com/showthread.php?132961-Propeller-Power-Consumed-Based-on-Code/page4
Where ideas are born
"The human brain lays at the foundation of creativity.." (H)
Creativity refers to the phenomenon whereby a person creates something new (a product, a solution, a work of art, etc.) that has some kind of value. What counts as "new" may be in reference to the individual creator, or to the society or domain within which the novelty occurs. What counts as "valuable" is similarly defined in a variety of ways.
http://en.wikipedia.org/wiki/Creativity
The project continues with Brain Rounds. The project can have any number of rounds, although there are three primary in use. In the First Round, the idea is established and announced. In the Second Round, all the development ideas are reviewed and analyzed and the best are chosen for continued development. In the Third Round, the chosen task is implemented.
There is some slight overlapping or mixing, even juxtaposition in rounds. For example, round one may include preliminary tests, some rough drawings may be derived, test code samples created, and it may lead to other development ideas. It can include psuedo code and flowcharts. In round two, a database of development ideas inclusive of hardware and software may be created for future programming and hardware machine references. In the third round, final test, final schematics and modular code or integrated code is solidified.
Brain Rounds
- Round One - invention, establishment, announcement
- Round Two - reviewing, selection, testing, development
- Round Three - implementation
Remembering of course only three people work on this project...(me, myself and I). So on the outside things that you see may look slow or sparse but on the inside it seems like a lot is happening. Sometimes I just want to develop and then forget to report and so everything is spread rather thin because it's based on the large number of projects related to the Big Brain. So Brain Rounds will allow the fastest representation of an idea and give it the option to go all the way to completion if found useful.Round one represents the discovery idea. Reporting on it at the discovery level is not going to create a lot of technical information, if any, but it will document the idea and show directions in which the project is headed. In can open up numerous considerations, many of which are pure thought experiments, like a Chess game, running through various moves and possible plans of design and development contention. Behind the scenes there must be some justification for representing the idea in the first round. Ideas must begin somewhere, and here they begin with documenting round one.
Picasso once said, “It would be very interesting to preserve photographically … the metamorphosis of a picture. Possibly one might then discover the path followed by the brain in materializing a dream.”
Like the metamorphosis of a picture, Brain Rounds materialize into dreams which may come true..
Terms
Brain Rounds - primarily a three step process of establishing and developing ideas, where the idea is established and can undergo a series of rounds of development
Schematic Portfolio Series
The Big Brain's Waveform filter development adds one filtering capacitor from pin 31 to ground. Capacitor value is a 10nf. Add one filter to each prop on a multi-prop system. This cleans up noise on the code loading process across physical banks of Propeller chips whose distance can become additive, thereby enabling the loading of programs into more Propeller chips per unit Partition. Tests show reliability of existing Partitions of 50 props per Partition can be extended to much larger numbers. It works so well, that Partitions could be added together and therefore this simple Waveform Filter can result in the design of much larger machines. It's estimated future machines will run at 100 chips (or more) per Partition with an unlimited number of Partitions.
Another use for the Waveform Noise Filter is in the Enumeration function. The filter works well with the Enumeration process and circuit for noise suppression during the enumeration process. The WNF utilizes a capacitor circuit in its most simple form and is designed for use with any Propeller pin and can function with other interfaces to filter out noise.
Create an effective TC timing constant (TC reflects how fast the circuit responds to changes in the voltage level) with the chosen capacitor value to match the circuit. Begin with a .1uF capacitor. Another common value is .01uf. Sometimes you will see a call for a 10nF capacitor measured in nanofarads instead of microfarads.
Individual WNFs use resin coated ceramic disc capacitors to effectively short very high frequency noise spikes to ground. This prevents noise from getting back into the line and traveling to other circuits and chips. The capacitor can act as filter to remove ripple from DC distribution signals or supply and smooth out uneven DC signals. Place multiple DC filters between line and ground.
WFNs work well in the Neural Matter Injector for global distribution and helps de-noise the Hybrid. Additionally as the length of interfacing (wiring) is slightly increased, WFNs will increase signal reliability by cleaning it.
This source about Bypass Capacitors provides background information:
http://www.seattlerobotics.org/encoder/jun97/basics.html
The frequency of the ripple can have a role in choosing the capacitor value. Rule of thumb is the higher the frequency, the smaller the bypass capacitor you need. If you have very high frequency components in your circuit, you might consider a pair of capacitors in parallel. One with a large value, one with a small value. If you have very complex ripple, you may need to add several bypass capacitors. Each cap is targeting a slightly different frequency. You may even need to add a larger electrolytic cap in case the amplitude of the lower frequencys is too great.
Terms
TC - Capacitor Timing Constant
WNF - Waveform Noise Filter
Step by Step development - Understanding the Big Brain
Discovery post
http://forums.parallax.com/showthread.php?124495-Fill-the-Big-Brain&p=1009101&viewfull=1#post1009101
Parallel Machine
The Big Brain is a special parallel machine that handles AtOnce technology (AO). AO is specifically developed for the Big Brain. Methods in the past took considerable time to load programs into large numbers of multiple chips and were not practical for the Big Brain.
Enumeration
Enumeration was time consuming as well. One could place a hardware circuit, with added parts, and develop code to read the circuit through pins, such as an R/C circuit, or provide another way, i.e. generate random numbers and hope for no duplicates. Accomplishing code for simple consecutive enumeration in true parallelism that could take place at once without any hardware was not available at that time.
Partition
The Big Brain Propeller machine was developed as a parallel machine. Banks of increasingly large Propeller arrays were introduced with a variety of test brain machines until the Partition was developed, based on a capping of the number of maximum Propeller chips per array.
WFM Waveform Noise Filter
Each Partition increased and was capped at 50 props for reliability, however the introduction of the WFM Waveform Noise Filter opened up capability for much larger Partitions for more massive machines.
Additive Arrays
One spinoff of developing these large array Partitions is that the experimental number of three could operate at the same time, in parallel. Two complete Partitions became the basis of parallel experiments.
Parallel - Parallel, or ParaP
This led to another spinoff of Parallel - Parallel, or ParaP. Things can happen simultaneously in multiple Partitions functioning in parallel. For example, two large Partitions are being designed to load at the same time, enumerate at the same time, inject matter at the same time, and function at the same time.
AtOnce or AO technology
This led to the next step, the technique of AtOnce or AO technology. AO represents things that appear to happen at once, or at the same time in terms of human observation. AO is being geared towards the aforementioned elements, ParaP, Enumeration, Injection, and Loading.
AO & Interfacing
Another use of AO is in interfacing. With a parallel interface as previously discussed, the design is a transmission of data that can be received at the same time by all listening props contained in large arrays.
AO Timing
AO can be defined in terms of timing. At first, the definition simply included things which take place simultaneously in true parallel, however continued definition design development now includes those events around 1 second or less. This will represent the time it takes to complete one task by all props - over the entire range of all combined Partitions.
There are other uses of AO.
Timeline Evolution of AO Technology
- Parallel Machine
- Partition
- Additive Arrays
- ParaP Parallel-Parallel
- AO Technology
Uses of AO TechnologyConnecting the brains of Man & Machine
Connecting the Brains of Man and Machine - Discovery Post
(I plan to connect a human brain to the Big Brain)
For years I've though about the ramifications of connecting the human brain to a machine brain and pondered the effects and results of such a connection. It is now possible to develop the tools necessary to make this connection so it's time to begin considerations.
What would you do if you could connect yourself to the machine? This is the beginning of a new era in Brain Technology when man becomes a part of the machine and visa versa.
In a number of Big Brain experiments it was determined that the Big Brain is not unlike the human brain in the emission of brain waves. It is now possible to read and discern the brain waves of both man and machine. (see Brain Wave post)
You probably remember seeing some of my posts about identifying programming functioning in the Big Brain with that of its emitted brain wave activity. These machine brain waves form the basis of a communications link with a biological brain.
Likewise, the brain activity of a biological brain is very specific and forms the basis of a communications link with a machine brain.
This can form a full duplex man and machine brain to brain communications interface.
The cost of supporting parts and tools for the technology of reading and recording brain wave activity in man and machine has reduced to a point of constructive affordability. It can be constructed of DIY and off the shelf materials.
It is at this time we will begin a program to undertake the merging of a human brain to that of a machine brain. (don't worry, the connection will be noninvasive)
Thoughts on brain machine interfacing.
http://www.slideshare.net/vishnu2kh/brain-machin-interfacing
http://en.wikipedia.org/wiki/Brain-computer_interface
http://www.robaid.com/bionics/147000-cpus-are-as-smart-as-a-cat-ibm-research-simulates-cats-brain.htm
The cognitive computing team, led by IBM Research, in collaboration with colleagues from Lawrence Berkeley National Lab, has performed the first near real-time cortical simulation of the brain that exceeds the scale of a cat cortex (PDF) and contains 1 billion spiking neurons and 10 trillion individual learning synapses.
The news is general and we don't know the specifics of the neurons generated for the brain simulation. If the Big Brain project can use it's simplex neurons, perhaps a fractional cat experiment could be achieved.
Sometimes you just need a giant helping hand!
Work continues on the giant Big Brain robotic Brain Stub, but it's not nearly as big as this working hydraulic hand:
Put your hand inside a glove and make this giant robot hand move!
http://rds.yahoo.com/_ylt=A2KJkK5YHyBOGwQAwi2jzbkF/SIG=139jgnqbm/EXP=1310756824/**http%3a//www.wired.com/gadgetlab/2009/05/hand-of-man-robot-tries-to-reach-for-the-gods/
‘Hand of Man’, an outsized hydraulic arm that can be operated from a little gloved controller nearby. “It’s modeled on the human hand and foreman and has the same range of motions,” says New Mexico-based artist Christian Ristow, who took about six months to build the installation. “It is all hydraulic and powered by diesel engines.”
Big Brain Applications
In the past we required special and sometimes expensive single platform program loaders to place code into chips. If you wanted to place code into more than one chip it was sometimes an arduous manual process of one by one chip insertion. program, remove, then repeat.
The big Brain project is developing an attractive high speed parallel interfacing feature that's advantageous for this application. The project is moving towards the application as a one chip programmer that programs hundreds of chips at the same time.
In the case of large and massive parallel hobby machines with parts reduction, the Propeller Programmer Application can simply load code into hundreds of Propellers by their volatile RAM. In the case of commercial companies seeking to load Propeller product, a more nonvolatile EEPROM can be attached for more permanency of code retainment after the power is removed.
Imagine a simple execution of the app, the first lead propeller is wired to hundreds of others which are all inserted into simple solderless breadboards. The code is loaded along with the Propeller loader and executed. Code is at once distributed into each and every Propeller chip. A second later, a hundred Propellers are ready to roll off the assembly line.
Big Brain Development Speed Goes Exponential
In the Beginning
When the project began, it merely inched along like a slug and every step was an effort to put one foot in front of the other. Many things about getting started were unknown and wheels had be invented, tried and tested, not to mention the long hours of research, along with the setback of crashed computers. It seemed to be a slow linear progression of development.
Picking Up Speed
Gradually in the time, the project began to pick up speed. After the main elements of the machine were in place, many machine designs, new tests, algorithms and ideas began to more rapidly appear in a new light and the linear progression line was replaced by a rapidly accelerating curve of development.
Exponential Rate
Forward another two months into the project and an exponential rate of development appeared. Platform begat platform, with ideas upon ideas, even new supporting machines were added, until suddenly there was simply not enough time - hours in a day, weeks, or months to fully document everything that required it.
Do-It-Or-Lose-It
Rather than lose important ideas by bringing rapid development to a suspended halt just to create reams of documents that likely would need rewriting anyway, a do-it-or-lose-it development approach is established which fits, just barely, the exponential development rate. Since this intro of DIOLI, the project is doing its best to continue new developments at full pace, taking on laps like a race car.
Quick Preservations
This at best utilizes memory, personal logs, napkin sketches, scratch paper, pseudo code, simple notes, WP representations, snapshots, and Quick Preservations which are based on establishing Time Lock Stops in time.
Time Lock Stop
If a documentation can be created fast enough to generate a Quick Preservation, a Time Lock Stop will be initiated to accomplished it. Time Lock Stops of only extremely short durations are allowed. Why? When Lock Stops were not in place, an inordinate amount of time was recklessly spent in drafting a schematic in its final form at a time when the project was not in its final form and the schematic would be revised anyway after revisions and thus need redrawing again.
Definitions of Terms
Quick Preservation creating documentation quickly in limited fashion, can rely upon memory or napkin sketches
Do-It-Or-Lose-It rapid exponential development technique with quick preservation
Time Lock Stop short stop in time to provide time frame for development documentation
WP word processing
SnapShots quick documents made with image capture
-Tor
Schematic Portfolio Series
Big Brain schematic shows connection for one Parallax Prop Plug, part number 32201, LED device on P15, R2 dropping resistor, and C1 decoupling capacitor. P28 and P29 plus power rails VDD and VSS lead to the EEPROM (not shown).
Refer to the following post for information about selecting a decoupling capacitor value:
Big Brain Decoupling Capacitor Schematic
Schematic Portfolio Series
Use a Multilayer ceramic capacitor, Nanjing Chiyang Electronics, CT4-0805-Y5V, P/N 63V-104-M 10nF or .1uF. Dropping resistors are 10K ohm. Note the schematic shows the first Propeller chip in a Big Brain Partition.
Edit: Note - remember to install a decoupling capacitor on both sides of each Propeller chip.
Discovery Post
http://forums.parallax.com/showthread.php?124495-Fill-the-Big-Brain&p=1016668&viewfull=1#post1016668
The Big Brain project is now introducing the Schematic Portfolio Series. The SPS is designed to show a comprehensive circuit-by-circuit drawing series, as a collection of individual schematics.
The first schematics introduced are for those circuits which are not expected to be modified. The idea is to create this first phase drawing program and then later advance to a planar multi-layer system. What will this lead to?
After the multi-layer schematic system is completed, it is expected to advance to schematic extrusion in three dimensions. Beyond that, we have the Genetic Schematic, proposed earlier, which can be reproduced from DNA constructs. That's intended to be read by Big Brains that need to procreate and duplicate circuits.
DNA mapping for reconstruction from DNA schematic constructs is extremely important for rebuilding a damaged brain section, cloning new circuits and internal brain hardware, and storing, memorizing, archiving a genetic code.
Definitions & Terms
SPS schematic portfolio series, a collection of schematics in various forms
Multi-Layer Schematic layers of schematic can be placed one on top of another to see the entire machine or looked at one at a time to reduce complexity
Schematic Extrusion a schematic is represented in 3D space
Genetic Schematic a machine DNA schematic of genetic code numbers that allows reconstruction, birth, procreation
Tor: I absolutely agree. Right now brain technologists can access simple image shapes, feelings, senses, (moods), light and dark, and do some controlling the other way around with brain waves. I'm not going to say it's far off, but we have a small way to go before full implementing of a Google-like brain to brain transfer.
In fact, the human brain will likely need some enhancement in terms of speed and memory storage and retention - however a brain transfer is an important future topic. Once we begin developing various machines of interfacing and the software to brain tap - sensing and communicating with regions of the brain - it will become more easy to transfer data. But the human brain is really slow. It has this vast storage capacity but its access time is deplorable. That's why some human brain enhancement will be required for accessing Google data bases.
For now, there are human brain techniques for remembering the names of everyone you will ever meet from this day forward. It is my belief that everything experienced from birth is stored into the brain, biologically compressed in folds and recesses - it's all a matter of access to remember it.
It is also interesting to know that clinical psychologists have shown that memories and experiences of our ancestors are stored in our brain but only come out under special circumstances. IMO, there's a lot to the human brain that will be explored in the near the future and harnessed for improvements in quality of living.
It sleeps all day?
http://www.eetimes.com/electronics-news/4217840/Million-ARM-cores-brain-simulator