@evanh said:
You've forgotten. That's only for Command and Address. And that streamer mode, X_IMM_8X4_LUT, will drive 32 consecutive pins if its data says so.
Oh yeah, you are right. LUT streaming output modes do drive 32 pins.
' 1 x 4-bit: $0000,$0001,$0002,$0003,$0004,$0005,$0006,$0007,$0008,$0009,$000a,$000b,$000c,$000d,$000e,$000f
' 1 x 4-bit: $0000,$0010,$0020,$0030,$0040,$0050,$0060,$0070,$0080,$0090,$00a0,$00b0,$00c0,$00d0,$00e0,$00f0
' 2 x 4-bit: $0000,$0011,$0022,$0033,$0044,$0055,$0066,$0077,$0088,$0099,$00aa,$00bb,$00cc,$00dd,$00ee,$00ff
' 4 x 4-bit: $0000,$1111,$2222,$3333,$4444,$5555,$6666,$7777,$8888,$9999,$aaaa,$bbbb,$cccc,$dddd,$eeee,$ffff
Well, I've improved the tester error checking so that a bunch of the bordering 100% readings are now 99% instead. A single bit error of the whole 100 kBytes/chip tested will produce a 99% result. Basically, the scoring always rounds down now. Previously, it was actually a logical flaw that counted any score for a block as a percentage success, which should have been only for perfect scores ... Oops. It now sums all the individual block scores first.
@evanh said:
This is rearing its head mostly now because I'm trying to move to doing the 16-bit wide bus. And what's changed is the defined constant for the 16 data pins. It now has an ADDPINS 15 so it exceeds the 9-bit limit of a single # immediate. This has had catastrophic repercussions on timing when compiling with Flexspin.
And there is another issue, actually even worse, where a local register variable will be used if the passed in constant is non-zero. But if it's zero then the optimiser will generate an immediate operand with ## instead. This one occurs when selecting individual chips in SPI interface mode.
Would some compiler control help here ?
I've seen compilers that allow in-line control of optimize levels, (so you disable then enable again past the critical section) ?
Those problems have gone away. I hadn't actually proven my ideas either, sorry. So it can't have been as bad as I was thinking. I've used many more local variables, replacing all ## immediates, to work around the original issue and that seems to clean it up.
Aside, because it's Spin, I also want the source code to be 100% compatible with Pnut/Proptool as well. So far so good. The current release is working as expected and doing a great job of what I set out to do. ... Ha, forgot to date the release last night ... done.
Comments
You've forgotten. That's only for Command and Address. And that streamer mode,
X_IMM_8X4_LUT, will drive 32 pins if its data says so.Oh yeah, you are right. LUT streaming output modes do drive 32 pins.
Here's all four possible tables:
' 1 x 4-bit: $0000,$0001,$0002,$0003,$0004,$0005,$0006,$0007,$0008,$0009,$000a,$000b,$000c,$000d,$000e,$000f ' 1 x 4-bit: $0000,$0010,$0020,$0030,$0040,$0050,$0060,$0070,$0080,$0090,$00a0,$00b0,$00c0,$00d0,$00e0,$00f0 ' 2 x 4-bit: $0000,$0011,$0022,$0033,$0044,$0055,$0066,$0077,$0088,$0099,$00aa,$00bb,$00cc,$00dd,$00ee,$00ff ' 4 x 4-bit: $0000,$1111,$2222,$3333,$4444,$5555,$6666,$7777,$8888,$9999,$aaaa,$bbbb,$cccc,$dddd,$eeee,$ffffI don't use the LUT in 4 bit modes as Immediates can be used instead.
I suppose that involves skip patterns. Oh, of course, you've got separate drivers.
Well, I've improved the tester error checking so that a bunch of the bordering 100% readings are now 99% instead. A single bit error of the whole 100 kBytes/chip tested will produce a 99% result. Basically, the scoring always rounds down now. Previously, it was actually a logical flaw that counted any score for a block as a percentage success, which should have been only for perfect scores ... Oops. It now sums all the individual block scores first.
So, the reports are even gnarlier now. Although, with both data registration states now included in the single report, it make it look smoother. Comparing Rayman's 96 MB add-on from the prior report - https://forums.parallax.com/discussion/comment/1541329/#Comment_1541329
usb-Parallax_Inc_Propeller_P2-ES_EVAL_P23YOO42-if00-port0 DATA_PIN = 32 addpins 7 CLK_PIN = 40 addpins 1 CE_PIN = 43 addpins 0 SPI cmode: 3 CLK_REGD = 1 TX_REGD = 1 SPI clock ratio: 2 (sysclock/2) bus[7:4] Chip ID: 0d 5d 52 f6 08 39 c5 84 bus[3:0] Chip ID: 0d 5d 52 f6 08 37 ca 46 Test data length: 100 x 2048 = 204800 bytes Frequency dependent lag compensation Sysclock u0 r0 u1 r1 u2 r2 u3 r3 u4 r4 u5 r5 60 MHz 100% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 0% 62 MHz 100% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 0% 64 MHz 100% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 0% 66 MHz 99% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 0% 68 MHz 92% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 0% 70 MHz 65% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 0% 72 MHz 43% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 0% 74 MHz 40% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 0% 76 MHz 42% 99% 100% 100% 0% 0% 0% 0% 0% 0% 0% 0% 78 MHz 45% 99% 100% 100% 0% 0% 0% 0% 0% 0% 0% 0% 80 MHz 41% 95% 100% 100% 0% 0% 0% 0% 0% 0% 0% 0% 82 MHz 30% 85% 100% 100% 0% 0% 0% 0% 0% 0% 0% 0% 84 MHz 6% 68% 100% 100% 0% 0% 0% 0% 0% 0% 0% 0% 86 MHz 0% 50% 100% 100% 0% 0% 0% 0% 0% 0% 0% 0% 88 MHz 0% 45% 100% 100% 0% 0% 0% 0% 0% 0% 0% 0% 90 MHz 0% 45% 100% 100% 1% 0% 0% 0% 0% 0% 0% 0% 92 MHz 0% 46% 100% 100% 44% 0% 0% 0% 0% 0% 0% 0% 94 MHz 0% 46% 100% 100% 99% 0% 0% 0% 0% 0% 0% 0% 96 MHz 0% 43% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 98 MHz 0% 38% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 100 MHz 0% 28% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 102 MHz 0% 10% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 104 MHz 0% 2% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 106 MHz 0% 0% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 108 MHz 0% 0% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 110 MHz 0% 0% 100% 100% 100% 0% 0% 0% 0% 0% 0% 0% 112 MHz 0% 0% 100% 100% 100% 1% 0% 0% 0% 0% 0% 0% 114 MHz 0% 0% 100% 100% 100% 10% 0% 0% 0% 0% 0% 0% 116 MHz 0% 0% 100% 100% 100% 47% 0% 0% 0% 0% 0% 0% 118 MHz 0% 0% 100% 100% 100% 91% 0% 0% 0% 0% 0% 0% 120 MHz 0% 0% 100% 100% 100% 99% 0% 0% 0% 0% 0% 0% 122 MHz 0% 0% 100% 100% 100% 100% 0% 0% 0% 0% 0% 0% 124 MHz 0% 0% 100% 100% 100% 100% 0% 0% 0% 0% 0% 0% 126 MHz 0% 0% 100% 100% 100% 100% 0% 0% 0% 0% 0% 0% 128 MHz 0% 0% 100% 100% 100% 100% 0% 0% 0% 0% 0% 0% 130 MHz 0% 0% 99% 100% 100% 100% 0% 0% 0% 0% 0% 0% 132 MHz 0% 0% 99% 100% 100% 100% 0% 0% 0% 0% 0% 0% 134 MHz 0% 0% 99% 100% 100% 100% 0% 0% 0% 0% 0% 0% 136 MHz 0% 0% 97% 100% 100% 100% 0% 0% 0% 0% 0% 0% 138 MHz 0% 0% 92% 100% 100% 100% 0% 0% 0% 0% 0% 0% 140 MHz 0% 0% 80% 100% 100% 100% 0% 0% 0% 0% 0% 0% 142 MHz 0% 0% 56% 100% 100% 100% 0% 0% 0% 0% 0% 0% 144 MHz 0% 0% 38% 100% 100% 100% 0% 0% 0% 0% 0% 0% 146 MHz 0% 0% 28% 100% 100% 100% 0% 0% 0% 0% 0% 0% 148 MHz 0% 0% 22% 100% 100% 100% 0% 0% 0% 0% 0% 0% 150 MHz 0% 0% 18% 100% 100% 100% 0% 0% 0% 0% 0% 0% 152 MHz 0% 0% 15% 99% 100% 100% 0% 0% 0% 0% 0% 0% 154 MHz 0% 0% 13% 99% 100% 100% 0% 0% 0% 0% 0% 0% 156 MHz 0% 0% 12% 99% 100% 100% 0% 0% 0% 0% 0% 0% 158 MHz 0% 0% 11% 99% 100% 100% 0% 0% 0% 0% 0% 0% 160 MHz 0% 0% 9% 97% 100% 100% 0% 0% 0% 0% 0% 0% 162 MHz 0% 0% 7% 92% 100% 100% 0% 0% 0% 0% 0% 0% 164 MHz 0% 0% 5% 85% 100% 100% 0% 0% 0% 0% 0% 0% 166 MHz 0% 0% 4% 75% 100% 100% 0% 0% 0% 0% 0% 0% 168 MHz 0% 0% 3% 65% 100% 100% 0% 0% 0% 0% 0% 0% 170 MHz 0% 0% 1% 53% 100% 100% 0% 0% 0% 0% 0% 0% 172 MHz 0% 0% 0% 42% 100% 100% 0% 0% 0% 0% 0% 0% 174 MHz 0% 0% 0% 37% 100% 100% 0% 0% 0% 0% 0% 0% 176 MHz 0% 0% 0% 33% 100% 100% 0% 0% 0% 0% 0% 0% 178 MHz 0% 0% 0% 32% 100% 100% 0% 0% 0% 0% 0% 0% 180 MHz 0% 0% 0% 30% 100% 100% 0% 0% 0% 0% 0% 0% 182 MHz 0% 0% 0% 29% 100% 100% 3% 0% 0% 0% 0% 0% 184 MHz 0% 0% 0% 27% 100% 100% 23% 0% 0% 0% 0% 0% 186 MHz 0% 0% 0% 24% 100% 100% 65% 0% 0% 0% 0% 0% 188 MHz 0% 0% 0% 20% 100% 100% 95% 0% 0% 0% 0% 0% 190 MHz 0% 0% 0% 17% 100% 100% 99% 0% 0% 0% 0% 0% 192 MHz 0% 0% 0% 13% 100% 100% 100% 0% 0% 0% 0% 0% 194 MHz 0% 0% 0% 10% 100% 100% 100% 0% 0% 0% 0% 0% 196 MHz 0% 0% 0% 8% 100% 100% 100% 0% 0% 0% 0% 0% 198 MHz 0% 0% 0% 6% 100% 100% 100% 0% 0% 0% 0% 0% 200 MHz 0% 0% 0% 4% 99% 100% 100% 0% 0% 0% 0% 0% 202 MHz 0% 0% 0% 3% 98% 100% 100% 0% 0% 0% 0% 0% 204 MHz 0% 0% 0% 2% 93% 100% 100% 0% 0% 0% 0% 0% 206 MHz 0% 0% 0% 1% 81% 100% 100% 0% 0% 0% 0% 0% 208 MHz 0% 0% 0% 0% 67% 100% 100% 0% 0% 0% 0% 0% 210 MHz 0% 0% 0% 0% 57% 100% 100% 0% 0% 0% 0% 0% 212 MHz 0% 0% 0% 0% 47% 100% 100% 0% 0% 0% 0% 0% 214 MHz 0% 0% 0% 0% 38% 100% 100% 0% 0% 0% 0% 0% 216 MHz 0% 0% 0% 0% 33% 100% 100% 0% 0% 0% 0% 0% 218 MHz 0% 0% 0% 0% 30% 100% 100% 0% 0% 0% 0% 0% 220 MHz 0% 0% 0% 0% 29% 100% 100% 0% 0% 0% 0% 0% 222 MHz 0% 0% 0% 0% 29% 100% 100% 0% 0% 0% 0% 0% 224 MHz 0% 0% 0% 0% 30% 100% 100% 0% 0% 0% 0% 0% 226 MHz 0% 0% 0% 0% 31% 100% 100% 0% 0% 0% 0% 0% 228 MHz 0% 0% 0% 0% 34% 100% 100% 1% 0% 0% 0% 0% 230 MHz 0% 0% 0% 0% 37% 99% 100% 4% 0% 0% 0% 0% 232 MHz 0% 0% 0% 0% 40% 100% 100% 14% 0% 0% 0% 0% 234 MHz 0% 0% 0% 0% 42% 99% 100% 33% 0% 0% 0% 0% 236 MHz 0% 0% 0% 0% 43% 99% 100% 57% 0% 0% 0% 0% 238 MHz 0% 0% 0% 0% 44% 99% 100% 79% 0% 0% 0% 0% 240 MHz 0% 0% 0% 0% 44% 99% 100% 91% 0% 0% 0% 0% 242 MHz 0% 0% 0% 0% 43% 98% 100% 96% 0% 0% 0% 0% 244 MHz 0% 0% 0% 0% 41% 96% 100% 98% 0% 0% 0% 0% 246 MHz 0% 0% 0% 0% 37% 94% 100% 99% 0% 0% 0% 0% 248 MHz 0% 0% 0% 0% 31% 90% 100% 99% 0% 0% 0% 0% 250 MHz 0% 0% 0% 0% 22% 84% 100% 100% 0% 0% 0% 0% 252 MHz 0% 0% 0% 0% 12% 78% 100% 100% 0% 0% 0% 0% 254 MHz 0% 0% 0% 0% 4% 70% 100% 100% 0% 0% 0% 0% 256 MHz 0% 0% 0% 0% 1% 63% 100% 100% 0% 0% 0% 0% 258 MHz 0% 0% 0% 0% 0% 56% 100% 100% 0% 0% 0% 0% 260 MHz 0% 0% 0% 0% 0% 51% 100% 100% 0% 0% 0% 0% 262 MHz 0% 0% 0% 0% 0% 48% 100% 100% 0% 0% 0% 0% 264 MHz 0% 0% 0% 0% 0% 46% 99% 100% 0% 0% 0% 0% 266 MHz 0% 0% 0% 0% 0% 45% 99% 100% 0% 0% 0% 0% 268 MHz 0% 0% 0% 0% 0% 45% 99% 100% 0% 0% 0% 0% 270 MHz 0% 0% 0% 0% 0% 46% 99% 100% 1% 0% 0% 0% 272 MHz 0% 0% 0% 0% 0% 46% 98% 100% 6% 0% 0% 0% 274 MHz 0% 0% 0% 0% 0% 47% 97% 100% 16% 0% 0% 0% 276 MHz 0% 0% 0% 0% 0% 48% 95% 100% 38% 0% 0% 0% 278 MHz 0% 0% 0% 0% 0% 49% 92% 100% 65% 0% 0% 0% 280 MHz 0% 0% 0% 0% 0% 50% 89% 100% 87% 0% 0% 0% 282 MHz 0% 0% 0% 0% 0% 51% 84% 100% 97% 0% 0% 0% 284 MHz 0% 0% 0% 0% 0% 51% 78% 100% 99% 0% 0% 0% 286 MHz 0% 0% 0% 0% 0% 52% 72% 100% 99% 0% 0% 0% 288 MHz 0% 0% 0% 0% 0% 52% 68% 100% 100% 0% 0% 0% 290 MHz 0% 0% 0% 0% 0% 52% 65% 100% 100% 0% 0% 0% 292 MHz 0% 0% 0% 0% 0% 53% 63% 100% 100% 0% 0% 0% 294 MHz 0% 0% 0% 0% 0% 53% 63% 100% 100% 0% 0% 0% 296 MHz 0% 0% 0% 0% 0% 52% 63% 99% 100% 0% 0% 0% 298 MHz 0% 0% 0% 0% 0% 51% 65% 99% 100% 0% 0% 0% 300 MHz 0% 0% 0% 0% 0% 49% 65% 99% 99% 0% 0% 0% 302 MHz 0% 0% 0% 0% 0% 45% 66% 99% 100% 0% 0% 0% 304 MHz 0% 0% 0% 0% 0% 39% 68% 99% 99% 0% 0% 0% 306 MHz 0% 0% 0% 0% 0% 32% 69% 99% 99% 0% 0% 0% 308 MHz 0% 0% 0% 0% 0% 24% 69% 99% 99% 0% 0% 0% 310 MHz 0% 0% 0% 0% 0% 16% 69% 99% 99% 0% 0% 0% 312 MHz 0% 0% 0% 0% 0% 10% 69% 98% 99% 0% 0% 0% 314 MHz 0% 0% 0% 0% 0% 5% 68% 96% 99% 0% 0% 0% 316 MHz 0% 0% 0% 0% 0% 2% 67% 94% 99% 0% 0% 0% 318 MHz 0% 0% 0% 0% 0% 1% 66% 91% 99% 0% 0% 0% 320 MHz 0% 0% 0% 0% 0% 0% 64% 89% 99% 0% 0% 0% 322 MHz 0% 0% 0% 0% 0% 0% 61% 86% 99% 0% 0% 0% 324 MHz 0% 0% 0% 0% 0% 0% 55% 84% 99% 0% 0% 0% 326 MHz 0% 0% 0% 0% 0% 0% 47% 82% 98% 0% 0% 0% 328 MHz 0% 0% 0% 0% 0% 0% 37% 80% 97% 0% 0% 0% 330 MHz 0% 0% 0% 0% 0% 0% 27% 77% 96% 0% 0% 0% 332 MHz 0% 0% 0% 0% 0% 0% 18% 74% 95% 0% 0% 0% 334 MHz 0% 0% 0% 0% 0% 0% 10% 71% 93% 0% 0% 0% 336 MHz 0% 0% 0% 0% 0% 0% 5% 68% 91% 1% 0% 0% 338 MHz 0% 0% 0% 0% 0% 0% 2% 66% 90% 2% 0% 0% 340 MHz 0% 0% 0% 0% 0% 0% 1% 66% 88% 4% 0% 0% 342 MHz 0% 0% 0% 0% 0% 0% 0% 65% 85% 9% 0% 0% 344 MHz 0% 0% 0% 0% 0% 0% 0% 61% 83% 18% 0% 0% 346 MHz 0% 0% 0% 0% 0% 0% 0% 28% 81% 36% 0% 0% 348 MHz 0% 0% 0% 0% 0% 0% 0% 24% 79% 52% 0% 0% 350 MHz 0% 0% 0% 0% 0% 0% 0% 8% 76% 66% 0% 0% 352 MHz 0% 0% 0% 0% 0% 0% 0% 6% 73% 77% 0% 0% 354 MHz 0% 0% 0% 0% 0% 0% 0% 6% 72% 85% 0% 0% 356 MHz 0% 0% 0% 0% 0% 0% 0% 6% 71% 89% 1% 0% 358 MHz 0% 0% 0% 0% 0% 0% 0% 5% 70% 91% 3% 0% 360 MHz 0% 0% 0% 0% 0% 0% 0% 5% 71% 92% 6% 0% DoneLatest source code for above:
Would some compiler control help here ?
I've seen compilers that allow in-line control of optimize levels, (so you disable then enable again past the critical section) ?
Those problems have gone away. I hadn't actually proven my ideas either, sorry. So it can't have been as bad as I was thinking. I've used many more local variables, replacing all ## immediates, to work around the original issue and that seems to clean it up.
Aside, because it's Spin, I also want the source code to be 100% compatible with Pnut/Proptool as well. So far so good. The current release is working as expected and doing a great job of what I set out to do. ... Ha, forgot to date the release last night ... done.
Finally got round to optimising the compare routine so it runs pretty close to same speed compiled with Pnut now. Above attachment is updated.
I've done a limited write-up of how the critical timing works. It doesn't cover the rx turnaround at all but plenty can still be understood educationally from it - https://forums.parallax.com/discussion/comment/1542073/#Comment_1542073
More here - https://forums.parallax.com/discussion/comment/1543542/#Comment_1543542