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Smartpin Diagram (now with %P..P bit mode table) - Page 6 — Parallax Forums

Smartpin Diagram (now with %P..P bit mode table)

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  • evanhevanh Posts: 10,384
    Wow, that's substantial there Chip. So USB mode dynamically adjusts output drive depending on the state?

  • evanhevanh Posts: 10,384
    Rayman wrote: »
    What do you mean by function list?
    Is it doing more than selecting one of several inputs?
    Yep, I've been calling it the F block because it performs the %FFF deglitch function as well.

  • cgraceycgracey Posts: 13,369
    evanh wrote: »
    Wow, that's substantial there Chip. So USB mode dynamically adjusts output drive depending on the state?

    Yes, this is why you don't need external 1.5k or 15k resistors. That's also why we went with 1.5k and 15k instead of 1k and 10k.
  • RaymanRayman Posts: 11,807
    I must be tired... I see deglitch is de-glitch now. Didn’t recognize as one word...
  • evanhevanh Posts: 10,384
    Ah, heh, sorry, probably better with the hyphen. Language isn't my strong suit.

  • evanhevanh Posts: 10,384
    Man, I'm not going to attempt to add the USB conduits for pin mode dynamic config. My diagram doesn't show any WRPIN config paths.

  • RaymanRayman Posts: 11,807
    Ok, here's a new version to match @evanh separation of analog and digital inputs and a MUX to pick between them.
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  • evanhevanh Posts: 10,384
    edited 2020-04-18 22:23
    Hmm, ... there's another loose one with CompDAC - None of the modes that apply to the main DAC apply to the CompDAC. As far as I can see, the level for CompDAC can only be set with an explicit WRPIN. Not even one of the selectable DAC sources, eg: SmartDAC, can be used for it. :(

    I had changed it in my diagram, to 8-bit from analogue, when reading Chip's block diagram and seeing it uses the same 8 bits as the main DAC. But like with "Input", it looks cool this way but it's functionally deceiving.

    Might be best to just remove the CompDAC path altogether.

    Updated:
                .......................                      :               ..........................
                : Custom I/O Pad Ring :                      :               : Synthesised Core Logic :
                '''''''''''''''''''''''                      :               ''''''''''''''''''''''''''
                                                             :
                                                             :                             CogDAC (Streamers/Cogs)
                                                             :          [%%%%%%%%%%%%%]<============================= cog0
                                                             :          [             ]<============================= cog1
                           [%%%%%%%%%%%%%]                   :          [   DAC bus   ]<============================= cog2
                    |      [  Flash DAC  ]<=============================[   select    ]<============================= cog3
                    |<-----[   Network   ]                   :          [             ]<============================= cog4
                    |      [   (%P...P)  ]                   :          [   (%P...P)  ]<============================= cog5
                    |      [             ]<-                 :          [             ]<============================= cog6
                    |      [%%%%%%%%%%%%%]  |                :          [             ]<============================= cog7
                    |                       |                :          [%%%%%%%%%%%%%]<===\\
                    |                       |                :               ^             ||
                    |      [%%%%%%%%%%%%%]  |                :               |   ------------------------------------- RND
                    |      [ Logic Drive ]<-+-------------   :        BitDAC |  | Other    ||
    [%%%%%%%%]      |<-----[   (%P...P)  ]                |  :               |  v          ||SmartDAC
    [        ]      |      [             ]<-------------  |  :          [%%%%%%%%%%%%%]    ||
    [Physical]      |      [%%%%%%%%%%%%%]              | |  :   Enable [             ]<------------------------------ OUT
    [ Even # ]------+            ^                      |  -------------[    Logic    ]    ||
    [ Pin Pad]      |            |                      |    :   Output [    Output   ]<---------------------------+-- DIR
    [        ]      |             -----------            --------+------[             ]    ||                      |
    [%%%%%%%%]      |                        |               :   |      [    (%TT)    ]    ||    [%%%%%%%%%%%%]    |
                    |                        |               :   |      [  (%MMMMM_0) ]    \\====[            ]    |
                    |                        |               :   |  OUT [             ]          [   Even #   ]<---
                    |      [%%%%%%%%%%%%%]   |               :   |   ---[             ]<---------[  Smartpin  ]
                    | PinB [  Comparator ]   |               :   |  |   [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ]
                  -------->[   & Logic   ]   |               :   |  |                            [            ]
                 |  | PinA [  & Schmitt  ]   |               :   |  |                            [  (X reg)===]<==== WXPIN
                 |  +----->[  (%P...P)   ]---+               :   |  |     -1  -2  -3             [  (Y reg)===]<==== WYPIN
                 |  |      [             ]   |Input          :   |  |      |   |   |             [  (Z reg)===]====> RDPIN
                 |  |      [%%%%%%%%%%%%%]   |               :   |  |      v   v   v             [            ]
                 |  |                        |               :   |  |   [%%%%%%%%%%%%%]      A   [            ]
                 |  |                        |   [%%%%%%%%]  :   |   -->[    Mux &    ]--------->[---o----o---]-------> IN
                 |  |      [%%%%%%%%%%%%%]    -->[   Mux  ]  :   |      [  De-glitch  ]      B   [  (M == 0)  ]
                 |  | PinA [ Sigma-Delta ]       [(%P...P)]------------>[   (A_B_F)   ]--------->[            ]
                 |  +----->[     ADC     ]------>[        ]  :   |      [%%%%%%%%%%%%%]          [            ]<------ ACK
                 |  |      [  (%P...P)   ]       [%%%%%%%%]  :   |         ^   ^   ^             [  USB brain ]
                 |  |      [%%%%%%%%%%%%%]                   :   |         |   |   |             [%%%%%%%%%%%%]
                 |  |                                        :   |        +1  +2  +3
                 |  |                                        :   |
                 |  |                                        :   |
                 |  |                                        :   |                         CogDAC (Streamers/Cogs)
                 |  |                                        :   |      [%%%%%%%%%%%%%]<============================= cog0
                 |  |                                        :   |      [             ]<============================= cog1
                 |  |      [%%%%%%%%%%%%%]                   :   |      [   DAC bus   ]<============================= cog2
                 |  |      [  Flash DAC  ]<=============================[   select    ]<============================= cog3
                 |<--------[   Network   ]                   :   |      [             ]<============================= cog4
                 |  |      [   (%P...P)  ]                   :   |      [   (%P...P)  ]<============================= cog5
                 |  |      [             ]<-                 :   |      [             ]<============================= cog6
                 |  |      [%%%%%%%%%%%%%]  |                :   |      [             ]<============================= cog7
                 |  |                       |                :   |      [%%%%%%%%%%%%%]<===\\
                 |  |                       |                :   |              ^          ||
                 |  |      [%%%%%%%%%%%%%]  |                :    -----------   |          ||
                 |  |      [ Logic Drive ]<-+-------------   :         Other |  |BitDAC    || SmartDAC
    [%%%%%%%%]   |<--------[   (%P...P)  ]                |  :               v  |          ||
    [        ]   |  |      [             ]<-------------  |  :          [%%%%%%%%%%%%%]    ||
    [Physical]   |  |      [%%%%%%%%%%%%%]              | |  :   Enable [             ]<------------------------------ OUT
    [ Odd #  ]---+  |            ^                      |  -------------[    Logic    ]    ||
    [ Pin Pad]   |  |            |                      |    :   Output [    Output   ]<---------------------------+-- DIR
    [        ]   |  |             -----------            ---------------[             ]    ||                      |
    [%%%%%%%%]   |  |                        |               :          [    (%TT)    ]    ||    [%%%%%%%%%%%%]    |
                 |  |                        |               :          [  (%MMMMM_0) ]    \\====[            ]    |
                 |  |                        |               :      OUT [             ]          [   Odd #    ]<---
                 |  |      [%%%%%%%%%%%%%]   |               :       ---[             ]<---------[  Smartpin  ]
                 |  | PinB [  Comparator ]   |               :      |   [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ]
                 |   ----->[   & Logic   ]   |               :      |                            [            ]
                 |    PinA [  & Schmitt  ]   |               :      |                            [  (X reg)===]<==== WXPIN
                 +-------->[  (%P...P)   ]---+               :      |     -1  -2  -3             [  (Y reg)===]<==== WYPIN
                 |         [             ]   |Input          :      |      |   |   |             [  (Z reg)===]====> RDPIN
                 |         [%%%%%%%%%%%%%]   |               :      |      v   v   v             [            ]
                 |                           |               :      |   [%%%%%%%%%%%%%]      A   [            ]
                 |                           |   [%%%%%%%%]  :       -->[    Mux &    ]--------->[---o----o---]-------> IN
                 |         [%%%%%%%%%%%%%]    -->[   Mux  ]  :          [  De-glitch  ]      B   [  (M == 0)  ]
                 |    PinA [ Sigma-Delta ]       [(%P...P)]------------>[   (A_B_F)   ]--------->[            ]
                  -------->[     ADC     ]------>[        ]  :          [%%%%%%%%%%%%%]          [            ]<------ ACK
                           [  (%P...P)   ]       [%%%%%%%%]  :             ^   ^   ^             [ USB passive]
                           [%%%%%%%%%%%%%]                   :             |   |   |             [%%%%%%%%%%%%]
                                                             :            +1  +2  +3
                                                             :
                .......................                      :               ..........................
                : Custom I/O Pad Ring :                      :               : Synthesised Core Logic :
                '''''''''''''''''''''''                      :               ''''''''''''''''''''''''''
    
  • RaymanRayman Posts: 11,807
    Ok, that was easy enough.
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  • RaymanRayman Posts: 11,807
    edited 2020-04-22 22:02
    Here's a slight tweak to hopefully clarify the A/B inputs connected to the physical pins.
    Also, put a slight shade difference on USB functions to differentiate even and odd smartpin USB functions...

    Maybe I should show a not connected B input to ADC?
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  • evanhevanh Posts: 10,384
    edited 2020-04-23 00:01
  • RaymanRayman Posts: 11,807
    Ok, now back to PinA/B and also SmartA/B.
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  • RaymanRayman Posts: 11,807
    Changed Smart to SMART_ to match other signals...
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  • RaymanRayman Posts: 11,807
    Hmm... SMART looks like an initialism there... Better make one up...

    How about "Semi-autonomous Multi-purpose Ancillary with Realtime Telemetry" ?
  • evanhevanh Posts: 10,384
    LOL! Got me giggling.

    Might be a stretch of the meaning of the word telemetry, though.

  • evanhevanh Posts: 10,384
    Oh! The 'S' has to be short for symmetric. Symmetric Multi-purpose Ancillary with Realtime Telemetry"
  • Symmetric Multi-purpose Automaton (RealTime)

    :-P
  • RaymanRayman Posts: 11,807
    Changed the title for clarity.
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  • RaymanRayman Posts: 11,807
    edited 2020-04-23 19:34
    evanh wrote: »
    Rayman wrote: »
    Ok, I have to read what BitDAC pin mode is... Guess it turns single bit into 8 bits at two different levels or something...
    Spot on. That's the whole function of that pin mode.

    @evanh: Can you please tell me more about this BitDAC using mode? I'm looking through the docs but can figure out where it is...
  • In the docs its "bit_dac" with the underscore

    The output is driven by one of the 2 main dacs (75/123/600/1k impedance), rather than the normal digital pin drive.

    There are 16 discrete dac levels that can be independently chosen for high and low signal levels (the levels are around 0.2v apart)

    It should be useful for say driving 1v8 external chips, because the drive impedance is much stronger than if you lowered VIO to 1v8 like you might do with an fpga.
  • RaymanRayman Posts: 11,807
    edited 2020-04-23 21:41
    Thanks. I see it now... You just set PPP to a DAC output mode and then use TT to enable Bit_DAC mode and then:
    'BIT_DAC' outputs {2{P[7:4]}} for 'high' or {2{P[3:0]}} for 'low' in DAC_MODE
    

    So, you get 4 bit resolution this way. Instead of the D...D being an 8-bit level, it's two 4-bit levels.

    I think I remember Chip saying it's usefulness for 1v8 chips might be limited due to this being more slow than the regular drive...
    Regular is something like 30 Ohm impedance and DAC is 75 Ohm at best...
  • Yes, two course levels, now. It changed somewhere along the way (prior to any silicon) from (high=8 bit level, low = 0.0v)

    What I remember Chip saying was that if you set VIO to 1v8, instead of 3v3, the outputs would be slow and weak, i think due to the level translators having no margin to operate with. However using the bit_dac mode, with 3v3 VIO supply to the pins, the outputs to the pins still have a fast settling time (its what we use for video).

    Regular strong drive is closer to 20 ohms (i think I measured 19)

    There is a question mark about how fast the comparator is that receives say 1v8 logic signals and compares to the 'slow dac', ie could this keep up with 1v8 hyperram data signals coming into the P2. We don't know the answer to this yet.

    There are new "version 2" 1v8 Hyperrams S27KS0642 available that are rated at a faster clock speed, but there will likely be new "version 2" 3v3 Hyperrams S27KL0642 before too long, so its not really worth trying the 1v8 right now
  • RaymanRayman Posts: 11,807
    I seem to remember both bad things about 1v8 logic interface but maybe you don’t know until you try...
  • We can try with a 1v8 version of the same W25Q flash we're already familiar with, thats easy to hook up and we have code already. A bit OT for this thread but I'll order some in and kick off a new thread
  • evanhevanh Posts: 10,384
    BitDAC change from one 8-bit to two 4-bit levels between Rev A and Rev B silicon.

  • RaymanRayman Posts: 11,807
    Is it done? I think it's finally done...
  • evanhevanh Posts: 10,384
    Yep. I'd need to ask a lot more questions of Chip to go further in to the hub, streamers and cogs.
  • evanhevanh Posts: 10,384
    Here's an example logic diagram of the input selector mux and de-glitch filter (F-block):
    f-block.png
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  • evanhevanh Posts: 10,384
    edited 2020-04-27 10:11
    Added the AND/OR/XOR functions:
    f-block.png

    EDIT: Updated with OUTin naming.
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  • evanhevanh Posts: 10,384
    edited 2020-04-27 10:14
    Here's the Logisim work file. If you load it into Logisim then you can toggle the inputs and see the signal flow. Logisim webpage - https://sourceforge.net/projects/circuit/

    EDIT: Updated with OUTin naming. Also added the T-block circuit.
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