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Smartpin Diagram (now with %P..P bit mode table)

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  • cgraceycgracey Posts: 13,631
    evanh wrote: »
    I prefer Smartpin over Smartcell.

    I've always called it "smart pin", as an adjective, rather than "smartpin", which is a registered trademark.
  • evanhevanh Posts: 12,021
    Thanks. I know Chip has used the term in both contexts but I'd like to see "Smartpin" be used for only one meaning. The docs generally support my interpretation even if not explicitly declared.

  • evanhevanh Posts: 12,021
    edited 2020-04-17 00:13
    cgracey wrote: »
    rather than "smartpin", which is a registered trademark.
    Oh. is that the problem. ... does a google ... LOL, so many of them. There is lots of different trademarks of that name. I doubt that's a concern, they aren't copyright claims.

    And Smartcell is a company name. So that's no better.

  • RaymanRayman Posts: 12,316
    Maybe OUT should be OUTA/B ....
    Same for IN
  • RaymanRayman Posts: 12,316
    edited 2020-04-17 00:16
    I figured that is why Chip always puts it as two words...

    But we don’t have to
  • evanhevanh Posts: 12,021
    Rayman wrote: »
    Maybe OUT should be OUTA/B ....
    Same for IN
    No, OUTA and OUTB covers 32 pins each. Likewise for INA and INB.

  • RaymanRayman Posts: 12,316
    Ok, Maybe IN[n] for even and IN[n+1] for odd?
  • RaymanRayman Posts: 12,316
    What modes use the feedback signal?
  • evanhevanh Posts: 12,021
    edited 2020-04-17 00:26
    Rayman wrote: »
    What modes use the feedback signal?
    Every entry containing "Input" in the "PinA Output" column of the Pad IO Modes table.

    Symbol name "INPUT" in Chip's block diagram.

  • evanhevanh Posts: 12,021
    edited 2020-04-17 00:35
    Rayman wrote: »
    Ok, Maybe IN[n] for even and IN[n+1] for odd?
    Extraneous, IN and IN[n] are the same. EDIT: Okay, I guess that is technically better since it does show the two IN's in the block diagram are distinct paths.

    EDIT2: You'll be doing it for every label if go down that path though.

  • RaymanRayman Posts: 12,316
    Maybe I’ll draw a horizontal line to separate the pins and label one n and the lower one n+1
  • RaymanRayman Posts: 12,316
    I could define the range of n that way too
  • evanhevanh Posts: 12,021
    Yep, just as long as it's clear that the top one is all even numbered pins and the bottom one is all odd numbered pins.
  • evanhevanh Posts: 12,021
    edited 2020-04-17 02:12
    An alternative is pack the diagram down to one pin and somehow detail the odd/even differences.

    In Chip's schematic for the whole custom pin cell he's used the symbols PA and PB. There is no odd/even naming because there is no difference other than being a pin pair. In the odd # pin PB is the even # pin, and in the even # pin PB is the odd # pin.

    Really, the main difference between odd and even pins is how "Other" is treated.

  • RaymanRayman Posts: 12,316
    I think the smartpin is different between odd and even too right? I think usb mode has only one being in charge...
  • evanhevanh Posts: 12,021
    Good question. I haven't tried to comprehend any of the USB capabilities.

  • RaymanRayman Posts: 12,316
    Ok, added even/odd barrier. Maybe this is the final version?
    1384 x 1594 - 221K
  • RaymanRayman Posts: 12,316
    edited 2020-04-17 14:46
    I think we should say something about USB... I'm not exactly sure how even and odd are connected in this mode, but the even pin is D- (master Brain) and the odd pin is D+ (slave Passive).
    Added this to Smart Pin sections
    1386 x 1595 - 228K
  • RaymanRayman Posts: 12,316
    Is HDMI in here somewhere as well?
  • evanhevanh Posts: 12,021
    Chip will need to comment on whether USB has a difference in the smartpins or if it's just the PinA/B pairing that makes the diff.

    TDMS encoding for DVI/HDMI is done in the CMOD hardware, which is a stage of the streamers.

  • RaymanRayman Posts: 12,316
    Ok, thanks. I'll consider this done for now then.
  • evanhevanh Posts: 12,021
    edited 2020-04-17 21:27
    Oh, you know how I've said "PI" and "Input" are practically the same signal in Chip's block diagram. Lets just make it so in ours. This means that my "Feedback" is the same as the logic input crossing the dotted line. ie: They can be made the same and it'll look clearer what the feedback is and also match up with the Pad IO Modes sheet.
          [%%%%%%%%%%%%%]  |   ||  :               v  |      
          [    Logic    ]  |   ||  :          [%%%%%%%%%%%%%]
          [    Drive    ]  |   ||  :   Enable [             ]
          [             ]<-+------------------[    Logic    ]
    ------[   (%P...P)  ]      ||  :   Output [    Output   ]
          [             ]<--------------------[             ]
          [%%%%%%%%%%%%%]      ||  :          [    (%TT)    ]
                ^              ||  :          [  (%MMMMM_0) ]
                |              ||  :      OUT [             ]
                |              ||  :       ---[             ]
                 -----------   ||  :      |   [%%%%%%%%%%%%%]
                            |  ||  :      |                  
          [%%%%%%%%%%%%%]   |  ||  :      |                  
          [  Comparator ]<=====//  :      |     -1  -2  -3   
          [             ]   |      :      |      |   |   |   
          [             ]   |      :      |      v   v   v   
     PinB [  Pin Input  ]   |      :      |   [%%%%%%%%%%%%%]
    ----->[   (%P...P)  ]   |      :       -->[ Logic Input ]
     PinA [             ]   |      :          [   (A_B_F)   ]
    ----->[             ]---+---------------->[             ]
          [ Sigma-Delta ]  Input   :          [%%%%%%%%%%%%%]
          [     ADC     ]          :             ^   ^   ^   
          [%%%%%%%%%%%%%]          :             |   |   |
                                   :            +1  +2  +3
    
  • RaymanRayman Posts: 12,316
    Ok, here it is like that. Not calling it done this time.... That seems to be bad luck..
    1330 x 1596 - 226K
  • evanhevanh Posts: 12,021
    edited 2020-04-17 22:20
    Oh, bugger, maybe I've put you wrong. It seemed a good idea for a short while. The problem with this new diagram arrangement is it makes it look like the ADC bitstream can reach the feedback when it really can't. That's the one actual difference between Chip's INPUT and the Input I've got there.

    Do we care? It looks tidy right now.

    EDIT: Maybe I should have a go at breaking that block up ... It'll bloat quite a lot I think ...

  • evanhevanh Posts: 12,021
    Okay, done a halfway job of splitting up the Pin Input block. It corrects that "Input" detail. And I've dumped the block name in favour of full mode list instead.
                .......................                       :               ..........................
                : Custom I/O Pad Ring :                       :               : Synthesised Core Logic :
                '''''''''''''''''''''''                       :               ''''''''''''''''''''''''''
                                                              :
                                                              :                             CogDAC (Streamers/Cogs)
                                                              :          [%%%%%%%%%%%%%]<============================= cog0
                                                              :          [             ]<============================= cog1
                           [%%%%%%%%%%%%%]                    :          [   DAC bus   ]<============================= cog2
                    |      [  Flash DAC  ]<=====++=======================[   select    ]<============================= cog3
                    |<-----[   Network   ]      ||            :          [             ]<============================= cog4
                    |      [   (%P...P)  ]      ||            :          [   (%P...P)  ]<============================= cog5
                    |      [             ]<-    ||            :          [             ]<============================= cog6
                    |      [%%%%%%%%%%%%%]  |   ||            :          [             ]<============================= cog7
                    |                       |   ||            :          [%%%%%%%%%%%%%]<===\\
                    |                       |   ||            :               ^             ||
                    |      [%%%%%%%%%%%%%]  |   ||            :               |   ------------------------------------- RND
                    |      [ Logic Drive ]<-+--------------   :        BitDAC |  | Other    ||
    [%%%%%%%%]      |<-----[   (%P...P)  ]      ||         |  :               |  v          ||SmartDAC
    [        ]      |      [             ]<--------------  |  :          [%%%%%%%%%%%%%]    ||
    [Physical]      |      [%%%%%%%%%%%%%]      ||       | |  :   Enable [             ]<------------------------------ OUT
    [ Even # ]------+            ^              ||       |  -------------[    Logic    ]    ||
    [ Pin Pad]      |            |              ||       |    :   Output [    Output   ]<---------------------------+-- DIR
    [        ]      |             -----------   ||        --------+------[             ]    ||                      |
    [%%%%%%%%]      |                        |  ||            :   |      [    (%TT)    ]    ||    [%%%%%%%%%%%%]    |
                    |                        |  ||            :   |      [  (%MMMMM_0) ]    \\====[            ]    |
                    |                        |  ||            :   |  OUT [             ]          [   Even #   ]<---
                    |      [%%%%%%%%%%%%%]   |  || CompDAC    :   |   ---[             ]<---------[  Smartpin  ]
                    | PinB [  Comparator ]<=====//            :   |  |   [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ]
                  -------->[   & Logic   ]   |                :   |  |                            [            ]
                 |  | PinA [  & Schmitt  ]   |                :   |  |                            [  (X reg)===]<==== WXPIN
                 |  +----->[  (%P...P)   ]---+                :   |  |     -1  -2  -3             [  (Y reg)===]<==== WYPIN
                 |  |      [             ]   |"Input"         :   |  |      |   |   |             [  (Z reg)===]====> RDPIN
                 |  |      [%%%%%%%%%%%%%]   |                :   |  |      v   v   v             [            ]
                 |  |                        |                :   |  |   [%%%%%%%%%%%%%]      A   [            ]
                 |  |                        |    [%%%%%%%%]  :   |   -->[ Logic Input ]--------->[---o----o---]-------> IN
                 |  |      [%%%%%%%%%%%%%]    --->[   Mux  ]  :   |      [   (A_B_F)   ]      B   [  (M == 0)  ]
                 |  | PinA [ Sigma-Delta ]        [(%P...P)]------------>[             ]--------->[            ]
                 |  +----->[     ADC     ]------->[        ]  :   |      [%%%%%%%%%%%%%]          [            ]<------ ACK
                 |  |      [  (%P...P)   ]        [%%%%%%%%]  :   |         ^   ^   ^             [   USB D-   ]
                 |  |      [%%%%%%%%%%%%%]                    :   |         |   |   |             [   brain    ]
                 |  |                                         :   |        +1  +2  +3             [%%%%%%%%%%%%]
                 |  |                                         :   |
                 |  |                                         :   |
                 |  |                                         :   |                         CogDAC (Streamers/Cogs)
                 |  |                                         :   |      [%%%%%%%%%%%%%]<============================= cog0
                 |  |                                         :   |      [             ]<============================= cog1
                 |  |      [%%%%%%%%%%%%%]                    :   |      [   DAC bus   ]<============================= cog2
                 |  |      [  Flash DAC  ]<=====++=======================[   select    ]<============================= cog3
                 |<--------[   Network   ]      ||            :   |      [             ]<============================= cog4
                 |  |      [   (%P...P)  ]      ||            :   |      [   (%P...P)  ]<============================= cog5
                 |  |      [             ]<-    ||            :   |      [             ]<============================= cog6
                 |  |      [%%%%%%%%%%%%%]  |   ||            :   |      [             ]<============================= cog7
                 |  |                       |   ||            :   |      [%%%%%%%%%%%%%]<===\\
                 |  |                       |   ||            :   |              ^          ||
                 |  |      [%%%%%%%%%%%%%]  |   ||            :    -----------   |          ||
                 |  |      [ Logic Drive ]<-+--------------   :         Other |  |BitDAC    || SmartDAC
    [%%%%%%%%]   |<--------[   (%P...P)  ]      ||         |  :               v  |          ||
    [        ]   |  |      [             ]<--------------  |  :          [%%%%%%%%%%%%%]    ||
    [Physical]   |  |      [%%%%%%%%%%%%%]      ||       | |  :   Enable [             ]<------------------------------ OUT
    [ Odd #  ]---+  |            ^              ||       |  -------------[    Logic    ]    ||
    [ Pin Pad]   |  |            |              ||       |    :   Output [    Output   ]<---------------------------+-- DIR
    [        ]   |  |             -----------   ||        ---------------[             ]    ||                      |
    [%%%%%%%%]   |  |                        |  ||            :          [    (%TT)    ]    ||    [%%%%%%%%%%%%]    |
                 |  |                        |  ||            :          [  (%MMMMM_0) ]    \\====[            ]    |
                 |  |                        |  ||            :      OUT [             ]          [   Odd #    ]<---
                 |  |      [%%%%%%%%%%%%%]   |  || CompDAC    :       ---[             ]<---------[  Smartpin  ]
                 |  | PinB [  Comparator ]<=====//            :      |   [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ]
                 |   ----->[   & Logic   ]   |                :      |                            [            ]
                 |    PinA [  & Schmitt  ]   |                :      |                            [  (X reg)===]<==== WXPIN
                 +-------->[  (%P...P)   ]---+                :      |     -1  -2  -3             [  (Y reg)===]<==== WYPIN
                 |         [             ]   |"Input"         :      |      |   |   |             [  (Z reg)===]====> RDPIN
                 |         [%%%%%%%%%%%%%]   |                :      |      v   v   v             [            ]
                 |                           |                :      |   [%%%%%%%%%%%%%]      A   [            ]
                 |                           |    [%%%%%%%%]  :       -->[ Logic Input ]--------->[---o----o---]-------> IN
                 |         [%%%%%%%%%%%%%]    --->[   Mux  ]  :          [   (A_B_F)   ]      B   [  (M == 0)  ]
                 |    PinA [ Sigma-Delta ]        [(%P...P)]------------>[             ]--------->[            ]
                  -------->[     ADC     ]------->[        ]  :          [%%%%%%%%%%%%%]          [            ]<------ ACK
                           [  (%P...P)   ]        [%%%%%%%%]  :             ^   ^   ^             [   USB D+   ]
                           [%%%%%%%%%%%%%]                    :             |   |   |             [  passive   ]
                                                              :            +1  +2  +3             [%%%%%%%%%%%%]
                                                              :
                .......................                       :               ..........................
                : Custom I/O Pad Ring :                       :               : Synthesised Core Logic :
                '''''''''''''''''''''''                       :               ''''''''''''''''''''''''''
    
  • evanhevanh Posts: 12,021
    Note I've made the ADC pin connection correct for Rev C silicon. Rev A and B would have both PinA and PinB connected.

  • RaymanRayman Posts: 12,316
    Maybe "Logic Input" can be "Logic Mux"?
  • evanhevanh Posts: 12,021
    edited 2020-04-18 00:38
    Okay, yeah, could go with function list there too "Mux & Deglitch"
  • RaymanRayman Posts: 12,316
    What do you mean by function list?
    Is it doing more than selecting one of several inputs?
  • cgraceycgracey Posts: 13,631
    edited 2020-04-18 01:08
    smartpi
    evanh wrote: »
    Chip will need to comment on whether USB has a difference in the smartpins or if it's just the PinA/B pairing that makes the diff.

    TDMS encoding for DVI/HDMI is done in the CMOD hardware, which is a stage of the streamers.

    In an even/odd pair, all the USB smart pin logic is in the even pin. The odd pin just has conduit for control from the even pin. The even pin controls HHH and LLL modes for both pins in the pair.
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